DG611/612/613 Vishay Siliconix High-Speed, Low-Glitch D/CMOS Analog Switches Fast Switching— tON: 12 ns Low Charge Injection: 2 pC Wide Bandwidth: 500 MHz 5-V CMOS Logic Compatible Low rDS(on): 18 Low Quiescent Power : 1.2 nW Single Supply Operation Improved Data Throughput Minimal Switching Transients Improved System Performance Easily Interfaced Low Insertion Loss Minimal Power Consumption Fast Sample-and-Holds Synchronous Demodulators Pixel-Rate Video Switching Disk/Tape Drives DAC Deglitching Switched Capacitor Filters GaAs FET Drivers Satellite Receivers The DG611/612/613 feature high-speed low-capacitance lateral DMOS switches. Charge injection has been minimized to optimize performance in fast sample-and-hold applications. switching FETs with low-power CMOS control logic and drivers. An epitaxial layer prevents latchup. The DG611 and DG612 differ only in that they respond to opposite logic levels. The versatile DG613 has two normally open and two normally closed switches. It can be given various configurations, including four SPST, two SPDT, one DPDT. Each switch conducts equally well in both directions when on and blocks up to 16 Vp-p when off. Capacitances have been minimized to ensure fast switching and low-glitch energy. To achieve such fast and clean switching performance, the DG611/612/613 are built on the Vishay Siliconix proprietary D/CMOS process. This process combines n-channel DMOS For additional information see Applications Note AN207 (FaxBack number 70605). DG611 DG611 D1 IN1 NC IN2 D2 Key 3 2 1 20 19 IN1 1 16 IN2 D1 2 15 D2 S1 4 18 S2 Four SPST Switches per Package S1 3 14 S2 V– 5 17 V+ V– 4 13 V+ NC 6 16 NC GND 5 12 VL 15 VL S4 6 11 S3 Dual-In-Line and SOIC Top View D4 7 10 D3 IN4 8 9 IN3 GND S4 LCC Top View 7 8 14 9 10 11 12 13 S3 Logic DG611 DG612 0 ON OFF 1 OFF ON Logic “0” 1 V Logic “1” 4 V D4 IN4 NC IN3 D3 Document Number: 70057 S-00399—Rev. G, 13-Sep-99 www.vishay.com FaxBack 408-970-5600 4-1 DG611/612/613 Vishay Siliconix DG613 IN1 1 DG613 16 IN2 D1 2 15 D2 S1 3 14 S2 V– 4 Dual-In-Line and SOIC 13 V+ 5 Top View 12 VL GND S4 6 11 S3 D4 7 10 D3 IN4 8 9 IN3 D1 IN1 NC Key 3 2 1 IN2 D2 20 19 Four SPST Switches per Package S1 4 18 S2 V– 5 17 V+ NC 6 16 NC 15 VL GND S4 LCC Top View 7 8 14 9 10 11 12 Logic SW1, SW4 0 OFF ON 1 ON OFF S3 SW2, SW3 Logic “0” 1 V Logic “1” 4 V 13 D4 IN4 NC IN3 D3 Temp Range Package Part Number DG611/612 DG611DJ 16-Pin Plastic DIP DG612DJ 40 to 85 85_C C –40 16-Pin Narrow SOIC DG611DY DG612DY DG611AK/883, 5962-9325501MEA 16-Pin CerDIP DG612AK/883, 5962-9325502MEA 55 to 125 C –55 125_C DG611AZ/883, 5962-9325501M2A LCC-20 DG612AZ/883, 5962-9325502M2A DG613 –40 to 85_C –55 to 125_C 16-Pin Plastic DIP DG613DJ 16-Pin Narrow SOIC DG613DY 16-Pin CerDIP DG613AK/883, 5962-9325503MEA LCC-20 DG613AZ/883, 5962-9325503M2A V+ to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 21 V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 21 V V– to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –19 V to 0.3 V VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to (V+) + 1 V or 20 mA, whichever occurs first VINa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –1 V to (V+) + 1 V or 20 mA, whichever occurs first VS, VDa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –0.3 V to (V–) + 16 V or 20 mA, whichever occurs first Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Current, S or D (Pulsed at 1 ms, 10% Duty Cycle) . . . . . . . . . . . . . 100 mA Storage Temperature: CerDIP . . . . . . . . . . . . . . . . . . . . . –65 to 150_C Plastic . . . . . . . . . . . . . . . . . . . . . . –65 to 125_C Power Dissipation (Package)b 16-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Pin Narrow SOICd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Pin CerDIPe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-Pin LCCe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW 600 mW 900 mW 900 mW Notes: a. Signals on SX, DX, or INX exceeding V+ or V– will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 6 mW/_C above 75_C d. Derate 7.6 mW/_C above 75_C e. Derate 12 mW/_C above 75_C V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 21 V V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to 0 V VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V to V+ www.vishay.com S FaxBack 408-970-5600 4-2 VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VL VANALOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V– to (V+) – 5 V Document Number: 70057 S-00399—Rev. G, 13-Sep-99 DG611/612/613 Vishay Siliconix Test Conditions Unless Otherwise Specified P Parameter S b l Symbol V = 15 V, V+ V V– V = –3 3V VL = 5 V, VIN = 4 V, 1 Vf VANALOG V– = –5 V, V+ = 12 V Tempb T Typc T A Suffix D Suffix –55 to 125_C –40 to 85_C Mind Maxd Mind Maxd Unit U i Analog Switch Analog Signal Rangee Switch On-Resistance Resistance Match Bet Ch. rDS(on) IS = –1 mA, VD = 0 V DrDS(on) Full –5 Room Full 18 Room 2 7 –5 45 60 7 45 60 Source Off Leakage IS(off) VS = 0 V, VD = 10 V Room Hot 0.001 –0.25 –20 0.25 20 –0.25 –20 0.25 20 Drain Off Leakage Current ID(off) VS = 10 V, VD = 0 V Room Hot 0.001 –0.25 –20 0.25 20 –0.25 –20 0.25 20 Switch On Leakage Current ID(on) VS = VD = 0 V Room Hot 0.001 –0.4 –40 0.4 40 –0.4 –40 0.4 40 V W nA A Digital Control Input Voltage High VIH Full Input Voltage Low VIL Full 4 Input Current IIN Room Hot 0.005 Input Capacitance CIN Room 5 3 4 1 –1 –20 1 20 1 –1 –20 1 20 V mA pF Dynamic Characteristics Off State Input Capacitance CS(off) VS = 0 V Room Off State Output Capacitance CD(off) VD = 0 V Room 2 On State Input Capacitance CS(on) VS = VD = 0 V Room 10 Bandwidth BW RL = 50 W Room 500 Turn-On Timee tON 12 25 25 Turn-Off Timee tOFF RL = 300 W , CL = 3 pF, p , VS = 2 V S T Ci it Figure Fi See Testt Circuit, 2 Room Room 8 20 20 Turn-On Time tON Room Full 19 35 50 35 50 Turn-Off Time tOFF Room Full 16 25 35 25 35 4 4 Charge Injectione RL = 300 W , CL = 75 pF VS = 2 V See Test Circuit, Figure 2 Q CL = 1 nF, VS= 0 V Room 4 DQ CL = 1 nF, VS 3 V Room 3 Off Isolatione OIRR RIN = 50 W , RL = 50 W f = 5 MHz Room 74 Crosstalke XTALK RIN = 10 W , RL = 50 W , f = 5 MHz Room 87 Ch. Injection Changee, g pF F MHz ns pC dB Power Supplies Positive Supply Curent I+ Room Full 0.005 Negative Supply Current I– Room Full –0.005 Logic Supply Current IL Room Full 0.005 IGND Room Full –0.005 Ground Current Document Number: 70057 S-00399—Rev. G, 13-Sep-99 VIN = 0 V or 5 V 1 5 –1 –5 1 5 –1 –5 1 5 –1 –5 1 5 A mA –1 –5 www.vishay.com S FaxBack 408-970-5600 4-3 DG611/612/613 Vishay Siliconix Test Conditions Unless Otherwise Specified P Parameter S b l Symbol A Suffix D Suffix –55 to 125_C –40 to 85_C V+ = 15 V, V– = –3 V VL = 5 V, VIN = 4 V, 1 Vf Tempb T 7 V IS = –1 mA, VD = 1 V Room 25 60 60 W RL = 300 W , CL = 3 pF, p , VS = 2 V S Test See T t Circuit, Ci it Figure Fi 2 Room 15 30 30 Room 10 25 25 Typc T Mind Maxd Mind 7 0 Maxd U i Unit Analog Switch Analog Signal Rangee VANALOG Switch On-Resistance rDS(on) Full 0 Dynamic Characteristics Turn-On Timee tON Turn-Off Timee tOFF ns Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. g. DQ = Q at VS = 3 V – Q at VS = –3 V. www.vishay.com S FaxBack 408-970-5600 4-4 Document Number: 70057 S-00399—Rev. G, 13-Sep-99 DG611/612/613 Vishay Siliconix _ rDS(on) vs. VD and Power Supply Voltages rDS(on) vs. VD and Temperature 400 IS = –1 mA r DS(on)– Drain-Source On-Resistance ( ) r DS(on)– Drain-Source On-Resistance ( ) 400 350 V+ = 12 V V– = –5 V 300 V+ = 5 V V– = –5 V 250 V+ = 15 V V– = –3 V 200 150 100 50 0 V+ = 15 V V– = –3 V IS = –1 mA 350 300 250 200 150 25_C 100 125_C 50 –55_C 0 –5 –4 –2 0 2 4 6 VD – Drain Voltage (V) 8 10 12 –4 Leakage Current vs. Analog Voltage 2 4 6 8 VD – Drain Voltage (V) 10 12 Leakage Currents vs. Temperature V+ = 15 V V– = –3 V 1 nA I S(off), I D(off)– Leakage (A) 2 I S, I D – Leakage Current (pA) 0 10 nA 3 1 IS(off), ID(off) 0 –1 ID(on) –2 –3 100 pA ID(on) 10 pA IS(off), ID(off) 1 pA 0.1 pA –4 –2 0 2 4 6 8 VD or VS – Drain or Source Voltage (V) 10 –55 –25 0 25 50 Temperature (_C) 75 100 125 Switching Times vs. Temperature Input Switching Threshold vs. VL 6 24 22 V+ = 15 V V– = –3 V 5 20 tON 18 4 16 Time (ns) V TH – Logic Input Voltage (V) –2 3 2 14 tOFF 12 10 8 V+ = 15 V V– = –3 V RL = 300 CL = 10 pF 6 1 4 2 0 0 0 5 10 VL – Logic Supply Voltage (V) Document Number: 70057 S-00399—Rev. G, 13-Sep-99 15 –55 –35 –15 5 25 45 65 85 105 125 Temperature (_C) www.vishay.com S FaxBack 408-970-5600 4-5 DG611/612/613 Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Charge Injection vs. Analog Voltage Crosstalk and Off Isolation vs. Frequency –120 20 V+ = 15 V V– = –3 V V+ = 15 V V– = –3 V –100 10 Crosstalk –80 (dB) Charge (pC) Qd 0 –60 Qs Off Isolation –10 –40 –20 –20 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 1 10 VANALOG – Analog Voltage (V) –3 dB Bandwidth/Insertion Loss vs. Frequency Supply Currents vs. Switching Frequency 0 6 RL = 50 V+ = 15 V V– = –3 V VL = 5 V CX = 0, 5 V 5 –4 4 3 –8 Supply Current (mA) Insertion Loss (dB) 100 f – Frequency (MHz) –12 –3 dB Point –16 I+ 2 1 IL 0 –1 I– –2 –3 –20 –4 –24 –5 1 10 100 1k 1000 f – Frequency (MHz) 100 k 100 k 1M 10 M f – Frequency (Hz) SCHEMATIC DIAGRAM (TYPICAL CHANNEL) V+ VL S INX Input Logic Level Translator Driver D DMOS Switch V– FIGURE 1. www.vishay.com S FaxBack 408-970-5600 4-6 Document Number: 70057 S-00399—Rev. G, 13-Sep-99 DG611/612/613 Vishay Siliconix +5 V +15 V VL V+ D tr < 10 ns tf < 10 ns 5V 50% Logic Input 2 V S VO 0V VS= 2 V 90% IN GND V– RL 300 CL Switch Output 20% 0V tON tOFF V– CL (includes fixture and stray capacitance) VO = VS RL RL + rDS(on) FIGURE 2. Switching Time C +5 V +15 V Rg V+ D IN Vg C V+ D1 50 IN1 1 V, 4 V NC CL 1 nF 5V GND VO +15 V VL S1 VS Rg = 50 VL S +5 V 1 V, 4 V V– S2 RL IN2 GND –3 V XTALK Isolation = 20 log VO D2 V– C VS VO –3 V C = RF bypass FIGURE 3. Charge Injection FIGURE 4. Crosstalk High-Speed Sample-and-Hold In a fast sample-and-hold application, the analog switch characteristics are critical. A fast switch reduces aperture uncertainty. A low charge injection eliminates offset (step) errors. A low leakage reduces droop errors. The CLC111, a fast input buffer, helps to shorten acquisition and settling times. A low leakage, low dielectric absorption hold capacitor must be used. Polycarbonate, polystyrene and polypropylene are good choices. The JFET output buffer reduces droop due to its low input bias current. (See Figure 5.) GaAs FET Drivers Figure 7 illustrates a high-speed GaAs FET driver. To turn the GaAs FET on 0 V are applied to its gate via S1, whereas to turn it off, –8 V are applied via S2. This high-speed, low-power driver is especially suited for applications that require a large number of RF switches, such as phased array radars. Pixel-Rate Switch Windows, picture-in-picture, title overlays are economically generated using a high-speed analog switch such as the DG613. For this application the two video sources must be sync locked. The glitch-less analog switch eliminates halos. (See Figure 6.) Document Number: 70057 S-00399—Rev. G, 13-Sep-99 www.vishay.com FaxBack 408-970-5600 4-7 DG611/612/613 Vishay Siliconix +5 V Input Buffer +12 V Output Buffer Analog Input S CLC111 D + 5 V Output to A/D LF356 – 75 IN 5 V Control 1/ 4 CHOLD 650 pF Polystyrene DG611 –5 V FIGURE 5. High-Speed Sample-and-Hold +5 V +12 V Output Buffer Background D + Composite Output 75 CLC410 – 75 1/ CLC114 2 250 Titles 250 75 5 V Control 1/ 2 DG613 –5 V FIGURE 6. A Pixel-Rate Switch Creates Title Overlays +5 V S1 VL V+ D1 RF IN GaAs RF OUT IN1 1/ 2 DG613 S2 5V D2 IN2 GND V– –8 V FIGURE 7. A High-Speed GaAs FET Driver that Saves Power www.vishay.com FaxBack 408-970-5600 4-8 Document Number: 70057 S-00399—Rev. G, 13-Sep-99