ON MC74VHCT138ADT 3-to-8 line decoder Datasheet

 SEMICONDUCTOR TECHNICAL DATA
The MC74VHCT138A is an advanced high speed CMOS 3–to–8 decoder
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 – A2)
determine which one of the outputs (Y0 – Y7) will go Low. When enable input
E3 is held Low or either E2 or E1 is held High, decoding function is inhibited
and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade
connection and for use as an address decoder for memory systems.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V, because they have full 5V
CMOS level output swings.
The VHCT138A input structures provide protection when voltages
between 0V and 5.5V are applied, regardless of the supply voltage. The
output structures also provide protection when VCC = 0V. These input and
output structures help prevent device destruction caused by supply voltage
– input/output voltage mismatch, battery backup, hot insertion, etc.
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D SUFFIX
16–LEAD SOIC PACKAGE
CASE 751B–05
DT SUFFIX
16–LEAD TSSOP PACKAGE
CASE 948F–01
M SUFFIX
16–LEAD SOIC EIAJ PACKAGE
CASE 966–01
High Speed: tPD = 7.6ns (Typ) at VCC = 5V
Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 4.5V to 5.5V Operating Range
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 122 FETs or 30.5 Equivalent Gates
ORDERING INFORMATION
MC74VHCTXXXAD
MC74VHCTXXXADT
MC74VHCTXXXAM
SOIC
TSSOP
SOIC EIAJ
PIN ASSIGNMENT
A0
1
16
VCC
A1
2
15
Y0
A2
3
14
Y1
E1
4
13
Y2
E2
5
12
Y3
E3
6
11
Y4
Y7
7
10
Y5
GND
8
9
Y6
FUNCTION TABLE
Inputs
15
Outputs
E3
E2
E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
X
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
A0
SELECT
INPUTS
A1
A2
ENABLE
INPUTS
E3
E2
E1
Y0
14
Y1
13
Y2
12
Y3
11
Y4
10
Y5
9
Y6
7
Y7
1
2
3
6
5
LOGIC DIAGRAM
4
H = high level (steady state); L = low level (steady state); X = don’t care
6/97
 Motorola, Inc. 1997
1
ACTIVE–LOW
OUTPUTS
REV 0
MC74VHCT138A
EXPANDED LOGIC DIAGRAM
15
14
A0
A1
13
1
12
2
11
A2
3
10
E2
E1
MOTOROLA
Y1
Y2
Y3
Y4
Y5
5
4
9
7
E3
Y0
Y6
Y7
6
2
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
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MC74VHCT138A
MAXIMUM RATINGS*
Symbol
Value
Unit
DC Supply Voltage
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
– 20
mA
IOK
Output Diode Current (VOUT < GND; VOUT > VCC)
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
VCC
Parameter
VCC = 0
High or Low State
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
v
v
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may adversely
affect device reliability. Functional operation under absolute–maximum–rated conditions is not
implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
Max
Unit
4.5
5.5
V
0
5.5
V
0
0
5.5
VCC
V
– 40
+ 85
_C
0
20
ns/V
DC Supply Voltage
Vin
DC Input Voltage
Vout
DC Output Voltage
TA
Operating Temperature
tr, tf
Input Rise and Fall Time
VCC = 0
High or Low State
VCC =5.0V ±0.5V
DC ELECTRICAL CHARACTERISTICS
S b l
Symbol
P
Parameter
T
Test
C
Conditions
di i
VCC
V
TA = 25°C
Min
VIH
Minimum High–Level
Input Voltage
4.5 to
5.5
VIL
Maximum Low–Level
Input Voltage
4.5 to
5.5
VOH
Minimum High–Level
Output Voltage
Vin = VIH or VIL
IOH = – 50µA
4.5
4.4
IOH = – 8mA
4.5
3.94
Maximum Low–Level
Output Voltage
Vin = VIH or VIL
IOL = 50µA
4.5
IOL = 8mA
VOL
Typ
TA = – 40 to 85°C
Max
2.0
Min
Max
2.0
0.8
4.5
U i
Unit
V
0.8
4.4
V
V
3.80
0.0
0.1
0.1
4.5
0.36
0.44
V
Maximum Input
Leakage Current
Vin = 5.5 V or GND
0 to 5.5
± 0.1
± 1.0
µA
Maximum Quiescent
Supply Current
Vin = VCC or GND
5.5
4.0
20.0
µA
ICCT
Quiescent Supply
Current
Per Input: VIN = 3.4V
Other Input: VCC or GND
5.5
1.35
1.50
mA
IOPD
Output Leakage
Current
VOUT = 5.5V
0
0.5
5.0
µA
Iin
ICC
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
3
MOTOROLA
MC74VHCT138A
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
S b l
Symbol
P
Parameter
T
Test
C
Conditions
di i
Min
TA = – 40 to 85°C
Typ
Max
Min
Max
U i
Unit
tPLH,
tPHL
Maximum Propagation Delay,
A to Y
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
7.6
8.1
10.4
11.4
1.0
1.0
12.0
13.0
ns
tPLH,
tPHL
Maximum Propagation Delay,
E3 to Y
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
6.6
7.1
9.1
10.1
1.0
1.0
10.5
11.5
ns
tPLH,
tPHL
Maximum Propagation Delay,
E2 or E1 to Y
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
7.0
7.5
9.6
10.6
1.0
1.0
11.0
12.0
ns
Cin
Maximum Input Capacitance
4
10
10
pF
Typical @ 25°C, VCC = 5.0V
CPD
P
Power
Dissipation
Di i i Capacitance
C
i
(N
(Note NO TAG)
pF
F
49
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no–load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
SWITCHING WAVEFORMS
VALID
A
VALID
3V
3V
E3
1.5V
GND
GND
tPLH
Y
tPHL
tPHL
VOH
1.5V
1.5V
tPLH
Y
VOH
1.5V
VOL
VOL
Figure 1.
Figure 2.
3V
E2 or E1
1.5V
GND
tPHL
tPLH
VOH
Y
1.5V
VOL
Figure 3.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
Figure 4. Test Circuit
MOTOROLA
4
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
MC74VHCT138A
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
DIM
A
B
C
D
F
G
J
K
M
P
R
F
R X 45°
C
–T
SEATING
–
J
M
PLANE
D 16 PL
0.25 (0.010)
M
T
B
A
S
S
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉ
ÇÇ
ÇÇ
ÉÉ
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
M
N
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
DETAIL E
H
D
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
G
5
MOTOROLA
MC74VHCT138A
OUTLINE DIMENSIONS
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 966–01
ISSUE O
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
9
Q1
M_
E HE
1
L
8
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
–––
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
–––
0.78
INCHES
MIN
MAX
–––
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
–––
0.031
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MOTOROLA
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6
MC74VHCT138A/D
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
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