Cypress CY62136CV30LL-70BVXI 2-mbit (128k x 16) static ram Datasheet

CY62136CV30 MoBL®
2-Mbit (128K x 16) Static RAM
Features
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O0 through
I/O15) are placed in a high-impedance state when: deselected
(CE HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW, and WE LOW).
• Very high speed
— 55 ns
• Voltage range
— 2.7V – 3.3V
• Pin-compatible with the CY62136V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 7 mA @ f = fMax (55 ns speed)
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball VFBGA
package
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Functional Description[1]
The CY62136CV30 is high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
128K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
A16
A14
A15
A13
A12
A11
COLUMN DECODER
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05199 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 19, 2006
CY62136CV30 MoBL®
Product Portfolio
Power Dissipation
Operating, ICC (mA)
VCC Range (V)
Product
VCC(min.)
CY62136CV30LL
2.7
f = 1 MHz
VCC(typ.)[2] VCC(max.)
3.0
3.3
f = fMax
Standby, ISB2 (µA)
Speed
(ns)
Typ.[2]
Max.
Typ.[2]
Max.
Typ.[2]
Max.
55
1.5
3
7
15
2
10
70
1.5
3
5.5
12
Pin Configuration[3, 4]
48-ball VFBGA
Top View
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
NC
A7
I/O3
VCC
D
VCC
I/O12 DNU
A16
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
3. NC pins are not connected to the die.
4. E3 (DNU) pin have to be left floating or tied to VSS to ensure proper operation.
Document #: 38-05199 Rev. *E
Page 2 of 12
CY62136CV30 MoBL®
DC Input Voltage[5] ................................ –0.5V to VCC + 0.3V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage to Ground Potential–0.5V to VCC(max) + 0.5V
DC Voltage Applied to Outputs
in High-Z State[5] ....................................–0.5V to VCC + 0.3V
Device
Range
CY62136CV30
Ambient
Temperature
VCC
Industrial –40°C to +85°C 2.7V to 3.3V
Electrical Characteristics Over the Operating Range
CY62136CV30-55
Parameter
Description
Test Conditions
Min.
Typ.
[2]
Max.
VOH
Output HIGH Voltage
IOH = –1.0 mA
VCC = 2.7V
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = 2.7V
VIH
Input HIGH Voltage
2.2
VCC +
0.3V
VIL
Input LOW Voltage
–0.3
IIX
Input Leakage Current GND < VI < VCC
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply
Current
f = fMax = 1/tRC
f = 1 MHz
2.4
CY62136CV30-70
Min.
Typ.[2] Max.
Unit
2.4
V
0.4
0.4
V
2.2
VCC +
0.3V
V
0.8
–0.3
0.8
V
–1
+1
–1
+1
µA
–1
+1
–1
+1
µA
mA
VCC = 3.3V
IOUT = 0 mA
CMOS Levels
7
15
5.5
12
1.5
3
1.5
3
ISB1
Automatic CE
CE > VCC – 0.2V
Power-down Current — VIN > VCC – 0.2V or VIN < 0.2V,
CMOS Inputs
f = fMax (Address and Data Only),
f = 0 (OE, WE, BHE, and BLE)
2
10
2
10
µA
ISB2
Automatic CE
CE > VCC – 0.2V
Power-down Current — VIN > VCC – 0.2V or VIN < 0.2V,
CMOS Inputs
f = 0, VCC = 3.3V
2
10
2
10
µA
Capacitance[7]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = VCC(typ.)
Max.
Unit
6
pF
8
pF
VFBGA
Unit
55
°C/W
16
°C/W
Thermal Resistance[7]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 x 4.5 inch,
2-layer printed circuit board
Notes:
5. VIL(min.) = –2.0V for pulse durations less than 20 ns.
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
Document #: 38-05199 Rev. *E
Page 3 of 12
CY62136CV30 MoBL®
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
VCC Typ
OUTPUT
30 pF
R2
90%
10%
90%
10%
GND
Rise TIme: 1 V/ns
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
3.0V
Unit
R1
1105
Ω
R2
1550
Ω
RTH
645
Ω
VTH
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[7]
Chip Deselect to Data
Retention Time
tR[7]
Operation Recovery Time
Conditions
Min.
Typ.[2]
1.5
VCC= 1.5V, CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
1
Max.
Unit
Vcc(max)
V
6
µA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
CE
Document #: 38-05199 Rev. *E
Page 4 of 12
CY62136CV30 MoBL®
Switching Characteristics Over the Operating Range[8]
55 ns
Parameter
Description
Min.
70 ns
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
55
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to Low-Z[9]
55
10
OE HIGH to
tLZCE
CE LOW to Low-Z[9]
70
10
ns
25
10
ns
ns
tHZCE
CE HIGH to
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
55
70
ns
tDBE
BHE/BLE LOW to Data Valid
25
35
ns
Low-Z[9]
tLZBE
BHE/BLE LOW to
tHZBE
BHE/BLE HIGH to High-Z[9, 10]
Write
20
ns
ns
5
20
High-Z[9, 10]
ns
10
5
High-Z[9, 10]
tHZOE
70
0
25
0
5
ns
5
20
ns
ns
25
ns
Cycle[11]
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
45
60
ns
tAW
Address Set-up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
45
ns
tBW
BHE/BLE Pulse Width
50
60
ns
tSD
Data Set-up to Write End
25
30
ns
tHD
Data Hold from Write End
0
0
ns
High-Z[9, 10]
tHZWE
WE LOW to
tLZWE
WE HIGH to Low-Z[9]
20
10
25
10
ns
ns
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30 pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
10. ItHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05199 Rev. *E
Page 5 of 12
CY62136CV30 MoBL®
Switching Waveforms
Read Cycle No. 1(Address Transition Controlled)[12, 13]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
ttLZOE
LZOE
BHE/BLE
tHZOE
tDOE
tHZBE
tDBE
tLZBE
HIGH IMPEDANCE
DATA OUT
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
ICC
50%
50%
ISB
Notes:
12. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
Document #: 38-05199 Rev. *E
Page 6 of 12
CY62136CV30 MoBL®
Switching Waveforms
Write Cycle No. 1 (WE Controlled)[11, 15, 16]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tSD
DATA I/O
NOTE 17
tHD
DATAIN VALID
tHZOE
Write Cycle No. 2 (CE Controlled)[11, 15, 16]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
DATAIN
NOTE 17
tHD
VALID
tHZOE
Notes:
15. Data I/O is high-impedance if OE = VIH
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05199 Rev. *E
Page 7 of 12
CY62136CV30 MoBL®
Switching Waveforms
Write Cycle No. 3 (WE Controlled, OE LOW)[16]
tWC
ADDRESS
CE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 17
tHD
DATAIN VALID
tLZWE
tHZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[16]
tWC
ADDRESS
CE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 17
DATAIN VALID
tHZWE
Document #: 38-05199 Rev. *E
tHD
tLZWE
Page 8 of 12
CY62136CV30 MoBL®
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C)
14.0
12.0
12.0
10.0
MoBL
(f = fMax,
55 ns)
8.0
6.0
ICC (mA)
ICC (mA)
Operating Current vs. Supply Voltage
14.0
8.0
MoBL
6.0
(f = fMax,
70 ns)
4.0
10.0
(f = fMax,
55 ns)
(f = fMax,
70 ns)
4.0
2.0
(f = 1 MHz)
0.0
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
2.0
(f = 1 MHz)
0.0
3.6
2.7 3.0 3.3
SUPPLY VOLTAGE (V)
Standby Current vs. Supply Voltage
12.0
MoBL
8.0
MoBL
ISB (µA)
ISB (µA)
12.0
10.0
6.0
10.0
8.0
6.0
4.0
4.0
2.0
2.0
0
2.7
3.0
0
3.3
2.7 3.0 3.3 3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
60
MoBL
50
50
40
40
30
30
20
TAA (ns)
TAA (ns)
60
20
10
10
0
0
2.7 3.0
3.3
SUPPLY VOLTAGE (V)
Document #: 38-05199 Rev. *E
MoBL
3.6
2.7
3.0 3.3
SUPPLY VOLTAGE (V)
Page 9 of 12
CY62136CV30 MoBL®
Truth Table
CE
WE
OE
BHE
BLE
Inputs/Outputs
Mode
Power
H
X
X
X
X
High-Z
Deselect/Power-down Standby (ISB)
L
X
X
H
H
High-Z
Output Disabled
Active (ICC)
L
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
High Z (I/O8–I/O15);
Data Out (I/O0–I/O7)
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
High Z (I/O0–I/O7)
Read
Active (ICC)
L
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
High Z (I/O8–I/O15);
Data In (I/O0–I/O7)
Write
Active (ICC)
L
L
X
L
H
Data in (I/O8–I/O15);
High Z (I/O0–I/O7)
Write
Active (ICC)
L
H
H
L
L
High-Z
Output Disabled
Active (ICC)
L
H
H
H
L
High-Z
Output Disabled
Active (ICC)
L
H
H
L
H
High-Z
Output Disabled
Active (ICC)
Ordering Information
Speed
(ns)
Ordering Code
55
CY62136CV30LL-55BVI
70
CY62136CV30LL-70BVXI
Package
Name
51-85150
Package Type
48-ball Fine Pitch BGA (6 x 8 x 1 mm)
Operating
Range
Industrial
48-ball Fine Pitch BGA (6 x 8 x 1 mm) Pb-free
Please contact your local Cypress sales representative for availability of these parts
Document #: 38-05199 Rev. *E
Page 10 of 12
CY62136CV30 MoBL®
Package Diagram
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
4
5
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
6.00±0.10
0.15(4X)
0.10 C
0.21±0.05
0.25 C
0.55 MAX.
B
51-85150-*D
C
1.00 MAX
0.26 MAX.
SEATING PLANE
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05199 Rev. *E
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62136CV30 MoBL®
Document History Page
Document Title: CY62136CV30 2-Mbit (128K x 16) Static RAM
Document Number: 38-05199
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
112379
02/19/02
GAV
New Data Sheet (advance information)
*A
114023
04/25/02
JUI
Added BV package diagram
Changed Advance Information to Preliminary
*B
117063
07/12/02
MGN
Changed Preliminary to Final
*C
118121
08/26/02
MGN
Added new part numbers: CY62136CV with wider voltage (2.7V – 3.6V);
CY62136CV33 narrower voltage range (3.0V – 3.6V)
For TAA = 55 ns, improved tPWE Min from 45 ns to 40 ns
For TAA = 70 ns, improved tPWE Min from 50 ns to 45 ns
For TAA = 70 ns, improved tLZWE Min from 5 ns to 10 ns
*D
118622
10/3/02
MGN
Improved Typ. ICC spec. to 7 mA (for 55 ns) and 5.5 mA (for 70 ns)
Improved Max ICC spec. to 15 mA (for 55 ns) and 12 mA (for 70 ns)
For TAA = 55 ns, improved tLZWE min. from 5 ns to 10 ns
Changed upper spec. for Supply Voltage to Ground Potential to VCC(max) + 0.5V
Changed upper spec. for DC Voltage Applied to Outputs in High-Z State and DC
Input Voltage to VCC + 0.3V
*E
486789
SEE ECN
VKN
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed Part numbers: CY62136CV and CY62136CV33
Updated Ordering Information table
Document #: 38-05199 Rev. *E
Page 12 of 12
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