NSC MM74C86N Quad 2-input exclusive-or gate Datasheet

MM54C86/MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
General Description
Features
Employing complementary MOS (CMOS) transistors to
achieve wide power supply operating range, low power consumption and high noise margin these gates provide basic
functions used in the implementation of digital integrated
circuit systems. The N- and P-channel enhancement mode
transistors provide a symmetrical circuit with output swing
essentially equal to the supply voltage. No DC power other
than that caused by leakage current is consumed during
static condition. All inputs are protected from damage due
to static discharge by diode clamps to VCC and GND.
Y
Y
Y
Y
Y
Y
Wide supply voltage range
3.0V to 15V
Guaranteed noise margin
1.0V
High noise immunity
0.45 VCC (typ.)
Low power
Fan out of 2
TTL compatibility
driving 74L
Low power consumption
10 nW/package (typ.)
The MM54C86/MM74C86 follows the
MM54LS86/MM74LS86 Pinout
Connection Diagram
Dual-In-Line Package
TL/F/5887 – 1
Top View
Order Number MM54C86 or MM74C86
Truth Table
Inputs
B
Y
L
L
H
H
L
H
L
H
L
H
H
L
H e High Level
C1995 National Semiconductor Corporation
TL/F/5887
Output
A
L e Low Level
RRD-B30M105/Printed in U. S. A.
MM54C86/MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
February 1988
Absolute Maximum Ratings
Power Dissipation (PD)
Dual-In-Line Package
Small Outline
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at any Pin (Note 1)
Operating Range (VCC)
b 0.3V to VCC a 0.3V
Operating Temperature Range
MM54C86
MM74C86
b 55§ C to a 125§ C
b 40§ C to a 85§ C
Storage Temperature Range
b 65§ C to a 150§ C
700 mW
500 mW
Absolute Maximum (VCC)
Lead Temperature (Soldering, 10 seconds)
3.0V to 15V
18V
260§ C
DC Electrical Characteristics Min/max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
VIN(1)
Logical ‘‘1’’ Input Voltage
VCC e 5.0V
VCC e 10V
3.5
8.0
VIN(0)
Logical ‘‘0’’ Input Voltage
VCC e 5.0V
VCC e 10V
VOUT(1)
Logical ‘‘1’’ Output Voltage
VCC e 5.0V, IO e b10 mA
VCC e 10V, IO e b10 mA
VOUT(0)
Logical ‘‘0’’ Output Voltage
VCC e 5.0V, IO e a 10 mA
VCC e 10V, IO e a 10 mA
IIN(1)
Logical ‘‘1’’ Input Current
VCC e 15V, VIN e 15V
IIN(0)
Logical ‘‘0’’ Input Current
VCC e 15V, VIN e 0V
ICC
Supply Current
VCC e 15V
V
V
1.5
2.0
4.5
9.0
V
V
0.5
1.0
0.005
b 1.0
V
V
1.0
b 0.005
0.01
V
V
mA
mA
15
mA
CMOS/LPTTL INTERFACE
VIN(1)
Logical ‘‘1’’ Input Voltage
54C, VCC e 4.5V
74C, VCC e 4.75V
VIN(0)
Logical ‘‘0’’ Input Voltage
54C, VCC e 4.5V
74C, VCC e 4.75V
VOUT(1)
Logical ‘‘1’’ Output Voltage
54C, VCC e 4.5V, IO e b360 mA
74C, VCC e 4.75V, IO e b360 mA
VOUT(0)
Logical ‘‘0’’ Output Voltage
54C, VCC e 4.5V, IO e 360 mA
74C, VCC e 4.75V, IO e 360 mA
VCCb1.5
VCCb1.5
V
V
0.8
0.8
2.4
2.4
V
V
V
V
0.4
0.4
V
V
OUTPUT DRIVE (See 54/74C Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCE
Output Source Current
(P-Channel)
VCC e 5.0V, VOUT e 0V
TA e 25§ C
b 1.75
b 3.3
mA
ISOURCE
Output Source Current
(P-Channel)
VCC e 10V, VOUT e 0V
TA e 25§ C
b 8.0
b 15
mA
ISINK
Output Sink Current
(N-Channel)
VCC e 5.0V, VOUT e VCC
TA e 25§ C
1.75
3.6
mA
ISINK
Output Sink Current
(N-Channel)
VCC e 10V, VOUT e VCC
TA e 25§ C
8.0
16
mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
2
AC Electrical Characteristics* (MM54C86/MM74C86) TA e 25§ C, CL e 50 pF, unless otherwise specified
Typ
Max
Units
tpd
Symbol
Propagation Time to Logical
‘‘1’’ or ‘‘0’’
Parameter
VCC e 5.0V
VCC e 10V
Conditions
Min
110
50
185
90
ns
ns
CIN
Input Capacitance
Note 2
5.0
pF
CPD
Power Dissipation Capacitance
(Note 3) Per Gate
20
pF
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application
NoteÐAN-90.
Typical Performance Characteristics
Propagation Delay Time vs
Load Capacitance
MM54C86/MM74C86
TL/F/5887 – 2
AC Test Circuit
TL/F/5887 – 3
Note: Delays Measured with Input tr, tf e 20 ns
Switching Time Waveforms
TL/F/5887 – 4
3
MM54C86/MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C86J or MM74C86J
NS Package Number J14A
Molded Dual-In-Line Package (N)
Order Number MM54C86N or MM74C86N
NS Package Number N14A
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