ICST ICS932S825 Low power clock chip for serverworks ht2400 server Datasheet

ICS932S825
Integrated
Circuit
Systems, Inc.
Low Power Clock Chip for Serverworks HT2400 Servers
Serverworks HT2400-based systems using AMD Opteron
processors
Output Features:
•
7 - Pairs of AMD Low Power K8 Greyhound
compliant clocks
7 - Pair of SRC/PCI Express* Gen 2 clocks
3 - 14.318 MHz REF clocks including 1 free-running
2 - 48MHz clocks
2 - PCI 33 MHz clocks
2 - 25MHz clocks
•
•
•
•
•
Features:
•
•
•
•
•
Spread Spectrum for EMI reduction
Outputs may be disabled via SMBus
M/N programming via SMBus
PCIe clocks meet PCIe Gen 2.
Low Power differential outputs
Functionality
CPU
(MHz)
Hi-Z
X/6
180.00
220.00
100.00
133.33
Reserved
200.00
FS2 FS1 FS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X1
X2
VDDREF_STB
REF0_RUN_2x
FS1/REF1_2x
FS2/REF2_2x
GNDREF
VDD48
48MHz_0_2x
48MHz_1_2x
GND48
SCLK
SDATA
VDDPCI
PCICLK0_2x
PCICLK1_2x
GNDPCI
CLKPWRGD/PD#
GND
VDDA
GNDA
GND
PCIeT_L0
PCIeC_L0
PCIeT_L1
PCIeC_L1
GND
VDDPCIe
PCIeT_L2
PCIeC_L2
PCIeT_L3
PCIeC_L3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
932S825
Pin Configuration
Recommended Application:
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD25MHz
FS0/25MHz_0_2x
25MHz_1_2x
GND25MHz
SPREAD_EN
CPUK8GT_L6
CPUK8GC_L6
CPUK8GT_L5
CPUK8GC_L5
VDDCPU
GND
CPUK8GT_L4
CPUK8GC_L4
CPUK8GT_L3
CPUK8GC_L3
CPUK8GT_L2
CPUK8GC_L2
VDDCPU
GND
CPUK8GT_L1
CPUK8GC_L1
CPUK8GT_L0
CPUK8GC_L0
GND
PCIeT_L6
PCIeC_L6
PCIeT_L5
PCIeC_L5
VDDPCIe
GND
PCIeT_L4
PCIeC_L4
64-TSSOP
Power Groups
Pin Number
VDD
8
64
14
20
36, 28
55, 47
3
1276D—10/25/07
GND
11
61
17
21
35, 27
54, 46
7
Description
48MHz Clocks
25MHz Clocks
33 MHz PCI Clocks
Analog Core
PCIe clocks
K8G CPU Clocks
REF Clocks, Xtal Osc.
*Other names and brands may be claimed as the property of others.
ICS932S825
Pin Description
PIN #
PIN NAME
TYPE
1
2
3
X1
X2
VDDREF_STB
IN
OUT
PWR
4
REF0_RUN_2x
OUT
5
FS1/REF1_2x
I/O
6
FS2/REF2_2x
I/O
7
8
9
10
11
12
13
14
15
16
17
GNDREF
VDD48
48MHz_0_2x
48MHz_1_2x
GND48
SCLK
SDATA
VDDPCI
PCICLK0_2x
PCICLK1_2x
GNDPCI
PWR
PWR
OUT
OUT
PWR
IN
I/O
PWR
OUT
OUT
PWR
18
CLKPWRGD/PD#
19
20
21
22
GND
VDDA
GNDA
GND
PWR
PWR
PWR
PWR
23
PCIeT_L0
OUT
24
PCIeC_L0
OUT
25
PCIeT_L1
OUT
26
PCIeC_L1
OUT
27
28
GND
VDDPCIe
PWR
PWR
29
PCIeT_L2
OUT
30
PCIeC_L2
OUT
31
PCIeT_L3
OUT
32
PCIeC_L3
OUT
IN
DESCRIPTION
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ref, XTAL power supply, nominal 3.3V standby power
14.318MHz Free Running XTAL Output. This output runs as long as
standby VDD is applied to the part. Default drive is 2 loads.
Frequency select latch input pin / 14.318 MHz reference clock. Default 2
load drive.
Frequency select latch input pin / 14.318 MHz reference clock. Default 2
load drive.
Ground pin for the REF outputs.
Power pin for the 48MHz output.3.3V
48MHz clock output. Default 2 load drive strength
48MHz clock output. Default 2 load drive strength
Ground pin for the 48MHz outputs
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Power supply for PCI clocks, nominal 3.3V
3.3V PCI clock output. Default 2 load drive strength.
3.3V PCI clock output. Default 2 load drive strength.
Ground pin for the PCI outputs
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active high
input. / Asynchronous active low input pin used to power down the device
into a low power state.
Ground pin.
3.3V power for the PLL core.
Ground pin for the PLL core.
Ground pin.
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
Ground pin.
Power supply for PCI Express clocks, nominal 3.3V
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
1276D—10/25/07
2
ICS932S825
Pin Description (continued)
PIN #
PIN NAME
TYPE
33
PCIeC_L4
OUT
34
PCIeT_L4
OUT
35
36
GND
VDDPCIe
PWR
PWR
37
PCIeC_L5
OUT
38
PCIeT_L5
OUT
39
PCIeC_L6
OUT
40
PCIeT_L6
OUT
41
GND
PWR
42
CPUK8GC_L0
OUT
43
CPUK8GT_L0
OUT
44
CPUK8GC_L1
OUT
45
46
47
CPUK8GT_L1
GND
VDDCPU
OUT
PWR
PWR
48
CPUK8GC_L2
OUT
49
CPUK8GT_L2
OUT
50
CPUK8GC_L3
OUT
51
CPUK8GT_L3
OUT
52
CPUK8GC_L4
OUT
53
54
55
CPUK8GT_L4
GND
VDDCPU
OUT
PWR
PWR
56
CPUK8GC_L5
OUT
57
CPUK8GT_L5
OUT
58
CPUK8GC_L6
OUT
59
60
61
62
CPUK8GT_L6
SPREAD_EN
GND25MHz
25MHz_1_2x
OUT
IN
PWR
OUT
63
FS0/25MHz_0_2x
64
VDD25MHz
I/O
PWR
DESCRIPTION
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
Ground pin.
Power supply for PCI Express clocks, nominal 3.3V
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
Ground pin.
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Ground pin.
Supply for CPU clocks, 3.3V nominal
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Ground pin.
Supply for CPU clocks, 3.3V nominal
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Asynchronous, active high input to enable spread spectrum functionality.
Ground pin for the 25Mhz outputs
25MHz clock output, 3.3V. Default 2 load drive
Frequency select latch input pin / Fixed 25MHz 3.3V clock output. Default 2
load drive
Power supply for 25MHz clocks, 3.3V nominal.
1276D—10/25/07
3
ICS932S825
General Description
The ICS932S825 is a main clock synthesizer chip that all clocks required by Serverworks HT2400-based servers.
An SMBus interface allows full control of the device.
Block Diagram
REF (2:1), REF 0_RUN
X1
X2
FS(2:0)
CKPWRGD/PD#
SPREAD_EN
XTAL
OSC.
48MHz(1:0)
FIXED PLL
25MHz PLL
25M
DIV
CPU/SRC/
PCI PLL
CPU
DIV
25MHz(1:0)
CPUK8G(6:0)
CONTROL
LOGIC
PCI33
DIV
SDATA
SCLK
SRC
DIV
Single-ended Terminations (All Single-Ended Outputs)
Series Resistor for Proper Termination
Single-ended
Number of
Zo = 50 ohms
Output Strength Loads on Board
1 Load
1
33
2 Load
1
39
(Default)
2
22
Differential Terminations
Number of
Differential
Series Resistor for Proper Termination
Zo = 50 ohms
Loads on Board
Output
CPUK8Gx
1
33
PCIe_Lx
1
33
1276D—10/25/07
4
PCICLK(1:0)
PCIe(6:0)
ICS932S825
Frequency Selection Table
Byte 0
Bit 4 Bit 3 Bit2 Bit1 Bit0
SS_EN FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
SRC
(MHz)
Hi-Z
X/4
180.00
220.00
100.00
133.33
Hi-Z
X/8
90.00
110.00
100.00
100.00
200.00
184.00
188.00
192.00
196.00
204.00
208.00
212.00
216.00
Hi-Z
X/4
180.00
220.00
100.00
133.33
100.00
92.00
94.00
96.00
98.00
102.00
104.00
106.00
108.00
Hi-Z
X/8
90.00
110.00
100.00
100.00
200.00
184.00
188.00
192.00
196.00
204.00
208.00
212.00
216.00
100.00
92.00
94.00
96.00
98.00
102.00
104.00
106.00
108.00
PCI
(MHz)
Hi-Z
x/24
30.00
36.67
33.33
33.33
Reserved
33.33
30.67
31.33
32.00
32.67
34.00
34.67
35.33
36.00
Hi-Z
x/24
30.00
36.67
33.33
33.33
Reserved
33.33
30.67
31.33
32.00
32.67
34.00
34.67
35.33
36.00
1276D—10/25/07
5
Spread
%
OverClock
Amount
N/A
N/A
0
0
0
0
N/A
N/A
0.90
1.10
1.00
1.00
0
0
0
0
0
0
0
0
0
N/A
N/A
-0.5%
-0.5%
-0.5%
-0.5%
1.00
0.92
0.94
0.96
0.98
1.02
1.04
1.06
1.08
N/A
N/A
1.00
1.00
1.00
1.00
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
1.00
0.92
0.94
0.96
0.98
1.02
1.04
1.06
1.08
ICS932S825
CPU Divider Ratios
Divider (1:0)
Divider (3:2)
Bit
00
01
10
11
LSB
00
0000
0001
0010
0011
Address
2
3
5
15
Div
01
0100
0101
0110
0111
Address
4
3
5
15
Div
01
0100
0101
0110
0111
Address
4
6
10
30
Div
10
1000
1001
1010
1011
Address
8
12
20
60
Div
11
1100
1101
1110
1111
Address
MSB
16
24
40
120
Div
10
1000
1001
1010
1011
Address
16
12
20
60
Div
11
1100
1101
1110
1111
Address
MSB
32
24
40
120
Div
10
1000
1001
1010
1011
Address
8
12
20
28
Div
11
1100
1101
1110
1111
Address
MSB
16
24
40
56
Div
PCI Divider Ratios
Divider (1:0)
Divider (3:2)
Bit
00
01
10
11
LSB
00
0000
0001
0010
0011
Address
8
6
10
30
Div
SRC Divider Ratios
Divider (1:0)
Divider (3:2)
Bit
00
01
10
11
LSB
00
0000
0001
0010
0011
Address
2
3
5
7
Div
01
0100
0101
0110
0111
Address
4
6
10
14
Div
1276D—10/25/07
6
ICS932S825
Absolute Maximum Ratings
Parameter
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
Ambient Operating Temp
Ts
Input ESD protection human body model
1
Symbol
Min
Max
Units Notes
VDDA
GND + 4.5V
V
1
VDD
GND +4.5V
V
1
-50
150
°C
Tambient
0
70
°C
ESD prot
2000
V
1
Operation at these extremes is neither implied nor guaranteed
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
Input High Voltage
VIH
Input Low Voltage
Input High Current
VIL
IIH
IIL1
Input Low Current
IIL2
Operating Current
Powerdown Current
3
Input Frequency
1
Pin Inductance
Input Capacitance1
Clk Stabilization1,2
Modulation Frequency
SMBus Voltage
Low-level Output Voltage
Current sinking at
VOL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time3
SCLK/SDATA
3
Clock/Data Fall Time
IDD3.3OP
IDD3.3PD
Fi
Lpin
CIN
COUT
CINX
TSTAB
VDD
VOL
Conditions
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
all outputs driven
all diff pairs Low/Low
VDD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de-assertion
of PD# to 1st clock
Triangular Modulation
MIN
2
TYP
VSS - 0.3
-5
MAX
UNITS NOTES
VDD + 0.3
V
1
0.8
5
V
uA
1
1
-5
uA
1
-200
uA
1
7
5
6
5
mA
mA
MHz
nH
pF
pF
pF
3
1
1
1
1
3
ms
1,2
33
5.5
0.4
kHz
V
V
1
1
1
mA
1
250
15
14.318
30
2.7
@ IPULLUP
4
IPULLUP
TRI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
TFI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
1
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
2
1276D—10/25/07
7
ICS932S825
AC Electrical Characteristics - Low Power Differential PCIe Outputs
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Rising Edge Slew Rate
t SLR
Differential Measurement
0.5
2
V/ns
1,2
Falling Edge Slew Rate
tFLR
Differential Measurement
0.5
2
V/ns
1,2
Slew Rate Variation
Maximum Output
Voltage
t SLVAR
Single-ended Measurement
20
%
1
VHIGH
Includes overshoot
1150
mV
1
Minimum Output Voltage
VLOW
Includes undershoot
mV
1
mV
1
550
140
55
mV
mV
%
1,3,4
1,3,5
1
125
ps
1
250
ps
1
-300
Differential Voltage
VSWING
Differential Measurement
400
Swing
Single-ended Measurement
300
Crossing Point Voltage
VXABS
Single-ended Measurement
Crossing Point Variation
VXABSVAR
Differential Measurement
45
Duty Cycle
DCYC
PCIe Jitter - Cycle to
Differential Measurement
PCIeJ C2C
Cycle
Differential Measurement
PCIe[6:0] Skew
PCIeSKEW
Notes on Electrical Characteristics:
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through Vswing centered around differential zero
3
Vxabs is defined as the voltage where CLK = CLK#
4
Only applies to the differential rising edge (CLK rising and CLK# falling)
5
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling.
6
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is
at 14.31818MHz
PCIe Phase Jitter Impact
Parameter
Conditions
Min
Typical
Max
Units
Notes
Output phase jitter
impact – PCIe* Gen1
θPCIe1
(including PLL BW 1.5-22 MHz, z =
0.54, Td=10 ns, Ftrk=1.5 MHz )
0
108
ps
1,2,3,4
Output phase jitter
impact - PCIe Gen2
θPCIe2
(including PLL BW5-16 MHz,
8 – 16 MHz, z = 0.54, Td=10 ns)
0
3.1
ps
RMS
1,2,3,4
NOTES:
1. Post processed evaluation through Intel supplied Matlab scripts.
2. PCIe* Gen2 filter characteristics are subject to final ratification by PC ISIG. Please check the PCI* SIG for the latest specification.
3. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be extrapolated to this BER target.
4. Guaranteed by design and characterization, not 100% tested in production.
1276D—10/25/07
8
ICS932S825
AC Electrical Characteristics - Low Power Differential CPU Outputs
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =AMD64 Processor Test Load
PARAMETER
SYMBOL
CONDITIONS
∆VCROSS
Crossing Point Variation
Single-ended Measurement
f
Frequency
Long Term Accuracy
ppm
MIN
TYP
198.8
-300
MAX
140
200
300
UNITS
mV
MHz
ppm
NOTES
1
2
3
Rising Edge Slew Rate
tSLR
Differential Measurement
0.5
10
V/ns
4,5
Falling Edge Slew Rate
tFLR
Differential Measurement
0.5
10
V/ns
4,5
CPU Jitter - Cycle to
Cycle
CPUJC2C
Differential Measurement
150
ps
6
CPU Jitter - Accumulated
CPUJACC
Over a 10 uS period
1
ns
7
Maximum Output Voltage
VHIGH
1150
mV
1
Minimum Output Voltage
VLOW
mV
1
Differential Voltage Swing
Peak-to-Peak
VDPK-PK
mV
8
Includes overshoot, single-ended
measurement
Includes undershoot, single-ended
measurement
Differential Measurement
-1
-300
400
2400
VD
Differential Measurement
200
1200
mV
Differential Voltage
Change in VD DC cycle-to∆VD
Single-ended Measurement
-75
75
mV
cycle
DCYC
Duty Cycle
Differential Measurement
45
55
%
CPUSKEW10
CPU[6:0] Skew
Differential Measurement
250
ps
Notes on Electrical Characteristics (Guaranteed by design and characterization, not 100% tested in production):
1
9
10
11
Single-ended measurement at crossing point. Value is max-min over all time. DC value of common mode is not important due to
the blocking cap.
2
Minimum frequency results from 0.5% down spread.
Measured with spread spectrum off.
4
This parameter is intended to give guidance for simulation.
5
Differential measurement through the range of +/-100mV
6
Between any two adjacent cycles.
7
Accumulated over a 10 uS time periode, measured with JIT2 TIE at 50ps interval.
8
VDPK-PK is the overall magnitude of the differential signal.
9
VDMIN is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross 0V
VD. VDMAX is the largest amplitude allowed.
10
The difference in magnitude of two adjacent VDDC measurements. VDDC is the stable post overshoot and ring-back part
11
Defined as tHIGH/tCYCLE
3
1276D—10/25/07
9
ICS932S825
Electrical Characteristics - 33 MHz PCICLK, 25MHz Outputs
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 5 pF (unless otherwise specified)
1
2
PARAMETER
PCI Long Accuracy
SYMBOL
ppm
PCI Clock period
Tperiod
25MHz Long Accuracy
25MHz Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
VOL
Output High Current
IOH
Output Low Current
IOL
Edge Rate
Edge Rate
Duty Cycle
PCI Skew
25MHz Skew
Jitter, Cycle to cycle
δV/δt
δV/δt
dt1
tsk1
tsk1
tjcyc-cyc
CONDITIONS
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
see Tperiod min-max values
25MHz output nominal
IOH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
MIN
-300
29.9910
29.9910
-50
TYP
40
2.4
-33
30
1
1
45
MAX
UNITS
300
ppm
30.0090
ns
30.1598
ns
50
ns
ns
V
0.55
V
mA
-33
mA
mA
38
mA
4
V/ns
4
V/ns
55
%
250
ps
250
ps
250
ps
Notes
1,2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
Electrical Characteristics - 48MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
ppm
see Tperiod min-max values
Long Accuracy
Tperiod
48.00MHz output nominal
Clock period
IOH = -1 mA
VOH
Output High Voltage
VOL
IOL = 1 mA
Output Low Voltage
V OH @ MIN = 1.0 V
IOH
Output High Current
VOH@ MAX = 3.135 V
VOL @MIN = 1.95 V
IOL
Output Low Current
VOL @ MAX = 0.4 V
Edge Rate
δV/δt
Rising edge rate
Edge Rate
δV/δt
Falling edge rate
VT = 1.5 V
dt1
Duty Cycle
tsk1
VT = 1.5 V
Group Skew
VT = 1.5 V
tjcyc-cyc
Jitter, Cycle to cycle
1
2
MIN
-100
20.8257
2.4
-33
30
1
1
45
TYP
MAX
UNITS
100
ppm
20.8340
ns
V
0.55
V
mA
-33
mA
mA
38
mA
2
V/ns
2
V/ns
55
%
250
ps
250
ps
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
1276D—10/25/07
10
Notes
1,2
2
1
1
1
1
1
1
1
1
1
1
1
ICS932S825
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
ppm
see Tperiod min-max values
Long Accuracy
Tperiod
14.318MHz output nominal
Clock period
IOH = -1 mA
VOH
Output High Voltage
IOL = 1 mA
VOL
Output Low Voltage
V OH @MIN = 1.0 V,
V
IOH
Output High Current
@MAX
=
3.135
V
OH
VOL @MIN = 1.95 V,
VOL
IOL
Output Low Current
@MAX = 0.4 V
Edge Rate
δV/δt
Rising edge rate
Edge Rate
Falling edge rate
δV/δt
tsk1
VT = 1.5 V
Skew
VT = 1.5 V
dt1
Duty Cycle
tjcyc-cyc
VT = 1.5 V
Jitter, Cycle to cycle
1
2
MIN
-300
69.8270
2.4
TYP
MAX
UNITS
300
ppm
69.8550
ns
V
0.4
V
-29
-23
mA
1
29
27
mA
1
1
1
2
2
500
55
1000
V/ns
V/ns
ps
%
ps
1
1
1
1
1
45
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
1276D—10/25/07
11
Notes
1
2
1
1
ICS932S825
General SMBus serial interface information
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
1276D—10/25/07
12
Not acknowledge
stoP bit
ICS932S825
SMBus Table: Frequency Select and Spread Control Register
Pin #
Name
Control Function
Byte 0
Reserved
Reserved
Bit 7
Reserved
Reserved
Bit 6
Reserved
Reserved
Bit 5
SS_EN
Spread Spectrum Enable
Bit 4
FS3
Freq Select Bit 3
Bit 3
FS2
Freq Select Bit 2
Bit 2
FS1
Freq Select Bit 1
Bit 1
FS0
Freq Select Bit 0
Bit 0
Type
0
1
RW
Reserved
Reserved
RW
Reserved
Reserved
RW
Reserved
Reserved
RW
RW
See CPU Frequency Select
RW
Table
RW
RW
SMBus Table: Output Control Register
Byte 1
Pin #
Name
6
REF2
Bit 7
5
REF1
Bit 6
4
REF0_RUN
Bit 5
17
PCICLK1
Bit 4
16
PCICLK0
Bit 3
Reserved
Bit 2
10
48MHz_1
Bit 1
9
48MHz_0
Bit 0
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Reserved
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Hi-Z
Hi-Z
Disable (Low)
Disable (Low)
Disable (Low)
Reserved
Disable (Low)
Disable (Low)
1
Enable
Enable
Enable
Enable
Enable
Reserved
Enable
Enable
PWD
1
1
1
1
1
1
1
1
Control Function
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Reserved
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Reserved
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
0
1
1
1
1
1
1
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Reserved
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Reserved
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
0
1
1
1
1
1
1
1
SMBus Table: Output Control Register
Byte 2
Pin #
Name
Reserved
Bit 7
59/58
CPUK8G_L(6)
Bit 6
57/56
CPUK8G_L(5)
Bit 5
53/52
CPUK8G_L(4)
Bit 4
51/50
CPUK8G_L(3)
Bit 3
47/46
CPUK8G_L(2)
Bit 2
45/44
CPUK8G_L(1)
Bit 1
43/42
CPUK8G_L(0)
Bit 0
SMBus Table: Output Control Register
Byte 3
Pin #
Name
Reserved
Bit 7
40/39
PCIe_L6
Bit 6
38/37
PCIe_L5
Bit 5
PCIe_L4
33/34
Bit 4
31/32
PCIe_L3
Bit 3
29/30
PCIe_L2
Bit 2
25/26
PCIe_L1
Bit 1
23/24
PCIe_L0
Bit 0
Output Enable
When Disabled
CPUK8GT_L = 0
CPUK8GC_L = 0
Control Function
Reserved
Output Enable
When Disabled
PCIeT_L = 0
PCIeC_L = 0
1276D—10/25/07
13
PWD
0
0
0
Latched
0
Latched
Latched
Latched
ICS932S825
SMBus Table: Drive Strength Control Register
Byte 4
Pin #
Name
Control Function
REF2
Drive Strength Select
6
Bit 7
REF1
Drive Strength Select
5
Bit 6
REF0_RUN
Drive Strength Select
4
Bit 5
17
PCICLK1
Drive Strength Select
Bit 4
PCICLK0
Drive Strength Select
16
Bit 3
11
48MHz_2
Drive Strength Select
Bit 2
10
48MHz_1
Drive Strength Select
Bit 1
9
48MHz_0
Drive Strength Select
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1 Load
1 Load
1 Load
1 Load
1 Load
1 Load
1 Load
1 Load
1
2 Loads
2 Loads
2 Loads
2 Loads
2 Loads
2 Loads
2 Loads
2 Loads
PWD
1
1
1
1
1
1
1
1
SMBus Table: Drive Strength Control Register
Pin #
Name
Control Function
Byte 5
62
25MHz_1
Output Enable
Bit 7
63
25MHz_0
Output Enable
Bit 6
62
25MHz_1
Drive Strength Select
Bit 5
63
25MHz_0
Drive Strength Select
Bit 4
Reserved
Reserved
Bit 3
VDIFF2
VDIFF MSB
Bit 2
VDIFF1
VDIFF Select Bit 0
Bit 1
VDIFF0
VDIFF LSB
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Low
Hi-Z
1 Load
1 Load
Reserved
1
Enable
Enable
2 Loads
2 Loads
Reserved
PWD
1
1
1
1
0
1
0
1
SMBus Table: Device ID Register
Byte 6
Pin #
Name
DevID 7
Bit 7
DevID 6
Bit 6
DevID 5
Bit 5
DevID 4
Bit 4
DevID 3
Bit 3
DevID 2
Bit 2
DevID 1
Bit 1
DevID 0
Bit 0
Control Function
Device ID MSB
Device ID 6
Device ID 5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID LSB
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
0
0
1
0
0
1
0
1
Control Function
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
0
0
0
1
0
0
0
1
SMBus Table: Vendor ID Register
Byte 7
Pin #
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
Revision ID
VENDOR ID
(0001 = ICS)
1276D—10/25/07
14
See VDIFF Select Table
ICS932S825
SMBus Table: Byte Count Register
Pin #
Name
Byte 8
BC7
Bit 7
BC6
Bit 6
BC5
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
SMBus Table: Reserved Register
Pin #
Name
Byte 9
Reserved
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Reserved
Bit 1
Reserved
Bit 0
Control Function
Byte Count Programming
b(7:0)
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Table: M/N Programming Enable
Byte 10
Pin #
Name
Control Function
CPU PLL M/N Programming
M/N_EN
Bit 7
Enable
Reserved
Reserved
Bit 6
Reserved
Reserved
Bit 5
Reserved
Reserved
Bit 4
Reserved
Reserved
Bit 3
Reserved
Reserved
Bit 2
Reserved
Reserved
Bit 1
Reserved
Reserved
Bit 0
1276D—10/25/07
15
Type
0
1
RW
RW
Writing to this register will
RW
RW configure how many bytes
RW will be read back, default is
9 bytes.
RW
RW
RW
PWD
0
0
0
0
1
0
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
0
0
0
0
0
0
0
0
Type
0
1
PWD
RW
Disable
Enable
0
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
0
0
0
0
0
ICS932S825
Bytes 11:14 are Reserved Registers
SMBus Table: CPU Frequency Control Register
Byte 15
Pin #
Name
Control Function
N
Div8
N
Divider Prog bit 8
Bit 7
Type
RW
Bit 6
-
N Div9
Bit 5
-
M Div5
RW
Bit 4
-
M Div4
RW
Bit 3
-
M Div3
RW
Bit 2
-
M Div2
Bit 1
-
M Div1
RW
M Div0
RW
Bit 0
N Divider Prog bit 9
M Divider Programming
bit (5:0)
SMBus Table: CPU Frequency Control Register
Pin #
Name
Control Function
Byte 16
N Div7
Bit 7
RW
RW
Type
RW
-
N Div6
Bit 5
-
N Div5
Bit 4
-
N Div4
Bit 3
-
N Div3
Bit 2
-
N Div2
RW
Bit 1
-
N Div1
RW
N Div0
RW
Bit 6
Bit 0
RW
N Divider Programming
Byte12 bit(7:0) and Byte11
bit(7:6)
SMBus Table: CPU Spread Spectrum Control Register
Byte 17
Pin #
Name
Control Function
SSP7
Bit 7
SSP6
Bit 6
SSP5
Bit 5
Spread Spectrum
SSP4
Bit 4
Programming bit(7:0)
SSP3
Bit 3
SSP2
Bit 2
SSP1
Bit 1
SSP0
Bit 0
1276D—10/25/07
16
RW
RW
RW
0
1
The decimal representation
of M and N Divier in Byte 11
and 12 will configure the
CPU VCO frequency.
Default at power up = latchin or Byte 0 Rom table. VCO
Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
0
1
The decimal representation
of M and N Divier in Byte 11
and 12 will configure the
CPU VCO frequency.
Default at power up = latchin or Byte 0 Rom table. VCO
Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
Type
0
1
RW
RW
RW These Spread Spectrum bits
in Byte 13 and 14 will
RW
program the spread
RW
pecentage of CPU
RW
RW
RW
PWD
X
X
X
X
X
X
X
X
PWD
X
X
X
X
X
X
X
X
PWD
X
X
X
X
X
X
X
X
ICS932S825
SMBus Table: CPU Spread Spectrum Control Register
Byte 18
Pin #
Name
Control Function
Reserved
Reserved
Bit 7
SSP14
Bit 6
SSP13
Bit 5
SSP12
Bit 4
Spread Spectrum
SSP11
Bit 3
Programming bit(14:8)
SSP10
Bit 2
SSP9
Bit 1
SSP8
Bit 0
0
1
Type
R
RW
RW
These Spread Spectrum bits
RW
in Byte 13 and 14 will
RW
program the spread
RW
pecentage of CPU
RW
RW
PWD
0
X
X
X
X
X
X
X
SMBus Table: Programmable Output Divider Register
Pin #
Name
Control Function
Byte 19
CPUDiv3
Bit 7
CPU Divider Ratio
CPUDiv2
Bit 6
Programming Bits
CPUDiv1
Bit 5
CPUDiv0
Bit 4
Reserved
Reserved
Bit 3
Reserved
Reserved
Bit 2
Reserved
Reserved
Bit 1
Reserved
Reserved
Bit 0
Type
RW
RW
RW
RW
R
R
R
R
PWD
X
X
X
X
0
0
0
0
SMBus Table: Programmable Output Divider Register
Pin #
Name
Control Function
Byte 20
33MHzDiv3
Bit 7
33MHz Divider Ratio
33MHzDiv2
Bit 6
Programming Bits
33MHzDiv1
Bit 5
33MHzDiv0
Bit 4
SRC_Div3
Bit 3
SRC_ Divider Ratio
SRC_Div2
Bit 2
Programming Bits
SRC_Div1
Bit 1
SRC_Div0
Bit 0
Type
0
1
RW
RW
33MHz Divider Ratio Table
RW
RW
RW
RW
SRC Divider Ratio Table
RW
RW
SMBusTable: Reserved Regsiter
Byte 21 is reserved do not write this register!
1276D—10/25/07
17
0
1
See CPU Divider Ratios
Table
-
-
PWD
X
X
X
X
X
X
X
X
ICS932S825
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) on the
ICS932S825 serve as dual signal functions to the device.
During initial power-up, they act as input pins. The logic
level (voltage) that is present on these pins at this time
is read and stored into a 5-bit internal data latch. At the
end of Power-On reset, (see AC characteristics for timing
values), the device changes the mode of operations for
these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
1276D—10/25/07
18
ICS932S825
c
N
SYMBOL
L
E1
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
E
INDEX
AREA
1 2
D
A
A2
VARIATIONS
A1
e
b
6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
MIN
MAX
-1.20
-.047
0.05
0.15
.002
.006
0.80
1.05
.032
.041
0.17
0.27
.007
.011
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
8.10 BASIC
0.319 BASIC
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
-0.10
-.004
-C-
N
SEATING
PLANE
64
aaa C
D mm.
MIN
16.90
D (inch)
MAX
17.10
MIN
.665
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS932S825yGLFT
Example:
ICS XXXX y G - LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
1276D—10/25/07
19
MAX
.673
ICS932S825
Revision History
Rev.
A
B
C
D
Issue Date Description
1. Updated Electrical Characteristics.
2. Going to Preliminary.
02/28/07 3. Updated Idd to reflect low power outputs
09/11/07 1. Updated pin description
09/12/07 1. Updated quantity of PCIEX outputs listed under "Output Features"
10/25/07
1.
2.
3.
4.
5.
Corrected CPU/SRC/PCI PLL control bytes to B(15:18) from B(11:14)
Changed pin names to indicate default drive strength. NO silicon changes.
Corrected Byte 0 SS_EN and FS3 reference in FS table.
Simplified the Terminations Table..
Release to Final
1276D—10/25/07
20
Page #
Various
2, 3
1
1, 2, 3, 4, 5,
16,17
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