ADS821 ADS 821 U SBAS040B – DECEMBER 1995 – REVISED FEBRUARY 2005 10-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● ● The ADS821 is a low-power, monolithic 10-bit, 40MHz Analog-to-Digital (A/D) converter utilizing a small geometry CMOS process. This complete converter includes a 10-bit quantizer with internal track-and-hold, reference, and a power-down feature. It operates from a single +5V power supply and can be configured to accept either differential or single-ended input signals. NO MISSING CODES INTERNAL REFERENCE LOW POWER: 380mW HIGH SNR: 58dB INTERNAL TRACK-AND-HOLD The ADS821 employs digital error correction to provide excellent Nyquist differential linearity performance for demanding imaging applications. Its low distortion, high SNR, and high oversampling capability give it the extra margin needed for telecommunications and video applications. APPLICATIONS ● ● ● ● ● ● VIDEO DIGITIZING ULTRASOUND IMAGING GAMMA CAMERAS SET-TOP BOXES CABLE MODEMS CCD IMAGING Color Copiers Scanners Camcorders Security Cameras Fax Machines ● IF AND BASEBAND DIGITIZATION ● TEST INSTRUMENTATION This high-performance converter is specified for AC and DCperformance at a 40MHz sampling rate. The ADS821 is available in an SO-28 package. CLK MSBI OE Error Correction Logic 3-State Outputs Timing Circuitry IN Pipeline A/D Converter T&H IN 10-Bit Digital Data +3.25V REFT CM REFB +1.25V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1995-2005, Texas Instruments Incorporated www.ti.com ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY +VS ....................................................................................................... +6V Analog Input ............................................................ 0V to (+VS + 300mV) This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. Logic Input ............................................................... 0V to (+VS + 300mV) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature .................................................................... +125°C ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. External Top Reference Voltage (REFT) ................................. +3.4V max External Bottom Reference Voltage (REFB) ............................ +1.1V min NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. PACKAGE/ORDERING INFORMATION(1) PRODUCT ADS821 PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING SO-8 DW –40°C to +85°C ADS821U ADS821U Rails, 28 " " " " ADS821U/1K Tape and Reel, 1000 " ORDERING NUMBER TRANSPORT MEDIA, QUANTITY NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. ADS821U PARAMETER RESOLUTION Specified Temperature Range ANALOG INPUT Differential Full-Scale Input Range Common-Mode Voltage Analog Input Bandwidth (–3dB) Small-Signal Full-Power Input Impedance DIGITAL INPUT Logic Family Convert Command CONDITIONS TAMBIENT f = 12MHz No Missing Codes Integral Linearity Error at f = 500kHz Spurious-Free Dynamic Range (SFDR) f = 500kHz (–1dBFS input) f = 12MHz (–1dBFS input) TYP –20dBFS(1) Input 0dBFS Input +25°C +25°C Bits °C +3.25 +2.25 V V MHz MHz MΩ || pF TTL/HCT Compatible CMOS Falling Edge ±0.6 ±1.1 ±85 0.01 ±2.1 0.02 +25°C Full ∆ +VS = ±5% UNITS 10 +85 400 65 1.25 || 4 Start Conversion ∆ +VS = ±5% MAX –40 +25°C Full +25°C CONVERSION CHARACTERISTICS Sample Rate Data Latency DYNAMIC CHARACTERISTICS Differential Linearity Error f = 500kHz MIN +1.25 ACCURACY(2) Gain Error Gain Drift Power-Supply Rejection of Gain Input Offset Error Power-Supply Rejection of Offset TEMP 10k ±1.5 ±2.5 0.15 ±3.5 0.15 40M Sample/s Convert Cycle ±1.0 ±1.0 ±1.0 ±1.0 LSB LSB LSB LSB ±2.0 LSB 6.5 tH = 13ns(3) ±0.5 ±0.6 ±0.5 ±0.6 Tested ±0.5 +25°C 0°C to +70°C +25°C 0°C to +70°C 0°C to +70°C 0°C to +70°C +25°C Full +25°C Full 60 54 58 54 70 67 63 62 % % ppm/°C %FSR/% % %FSR/% dBFS dBFS dBFS dBFS NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) Refer to Timing Diagram footnotes for the differential linearity performance conditions for the SO and SSOP packages. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈ 0dB), the intermodulation products will be 7dB lower. (5) Based on (SINAD – 1.76)/6.02. (6) No “rollover” of bits. 2 ADS821 www.ti.com SBAS040B ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. ADS821U PARAMETER CONDITIONS DYNAMIC CHARACTERISTICS (Cont.) 2-Tone Intermodulation Distortion (IMD)(4) f = 4.4MHz and 4.5MHz (–7dBFS each tone) f = 12MHz (–1dBFS input) Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) f = 12MHz (–1dBFS input) OUTPUTS Logic Family Logic Coding Logic Levels NTSC or PAL fIN = 3.58MHz Power Consumption TYP MAX 1.5x Full-Scale Input Logic Selectable Logic LOW, CL = 15pF max Logic HIGH, CL = 15pF max dBc dBc +25°C Full +25°C Full 57 55 56 54 59 59 58 58 dB dB dB dB +25°C Full +25°C Full +25°C NTSC or PAL 56 52 53 50 58.5 58 57 56 0.5 dB dB dB dB % +25°C +25°C +25°C 0.1 9.3 2 +25°C Bits ns 7 2 ns TTL/HCT Compatible CMOS SOB or BTC Full 0 0.4 V Full +2.5 +VS V 20 2 40 10 ns ns +5 76 78 380 390 +5.25 88 90 440 450 75 V mA mA mW mW °C/W Full Operating Operating Operating Operating Operating UNITS –61 –60 +25°C 3-State Enable Time 3-State Disable Time POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS MIN +25°C Full Signal-to-Noise Ratio (SNR) f = 500kHz (–1dBFS input) Differential Gain Error Differential Phase Error Degrees Effective Bits(5) Aperture Delay Time Aperture Jitter ps rms Over-Voltage Recovery Time(6) TEMP Full +25°C Full +25°C Full Thermal Resistance, θJA +4.75 NOTES: (1) dBFS refers to dB below Full Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) Refer to Timing Diagram footnotes for the differential linearity performance conditions for the SO and SSOP packages. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈ 0dB), the intermodulation products will be 7dB lower. (5) Based on (SINAD – 1.76)/6.02. (6) No “rollover” of bits. ADS821 SBAS040B www.ti.com 3 PIN DESCRIPTIONS PIN CONFIGURATION Top View SO GND 1 28 GND Bit 1 (MSB) 2 27 IN Bit 2 3 26 IN Bit 3 4 25 GND Bit 4 5 24 +VS Bit 5 6 23 REFT Bit 6 7 22 CM ADS821 PIN DESIGNATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 DNC DNC GND +VS CLK +VS OE 19 MSBI 20 21 +VS REFB Bit 7 8 21 REFB Bit 8 9 20 +VS Bit 9 10 19 MSBI Bit 10 (LSB) 11 18 OE DNC 12 17 +VS DNC 13 16 CLK 22 CM GND 14 15 +VS 23 REFT 24 25 26 27 28 +VS GND IN IN GND DNC: Do Not Connect DESCRIPTION Ground Bit 1, Most Significant Bit (MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10, Least Significant Bit (LSB) Do Not Connect Do Not Connect Ground +5V Power Supply Convert Clock Input, 50% Duty Cycle +5V Power Supply HIGH: High-Impedance State. LOW or Floating: Normal Operation. Internal pull-down resistor. Most Significant Bit Inversion, HIGH: MSB inverted for complementary output. LOW or Floating: Straight output. Internal pull-down resistor. +5V Power Supply Bottom Reference Bypass. For external bypassing of internal +1.25V reference. Common-Mode Voltage. It is derived by (REFT + REFB)/2. Top Reference Bypass. For external bypassing of internal +3.25V reference. +5V Power Supply Ground Input Complementary Input Ground TIMING DIAGRAM tCONV tL Convert Clock tD tH DATA LATENCY (6.5 Clock Cycles) Hold Hold Hold Hold Hold Hold Track "N + 1" Track "N + 2" Track "N + 3" Track "N + 4" Track "N + 5" Track "N + 6" Track (1) Track Internal Track-and-Hold Hold "N" t2 Output Data Data Valid N–8 Data Valid N–7 Data Valid N–6 N–5 N–4 N–3 N–2 N–1 N t1 Data Invalid SYMBOL tCONV tL tH tD t1 t2 DESCRIPTION MIN Convert Clock Period Clock Pulse LOW Clock Pulse HIGH Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max 25 12 12(2) TYP MAX UNITS 100µs ns ns ns ns ns ns 12.5 12.5 2 3.9 12.5 NOTES: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates. (2) tH must be 13ns minimum if no missing codes is desired only for the conditions of tCONV ≤ 28ns and fIN < 2MHz for the SO package. For best performance in the SSOP package, tH must be 13ns minimum for all input frequencies and tCONV ≤ 28ns. Refer to the Clock Requirements for a possible clock skew circuit for this condition. 4 ADS821 www.ti.com SBAS040B TYPICAL CHARACTERISTICS At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 5MHz –20 –40 –40 Amplitude (dB) Amplitude (dB) fIN = 500kHz –20 –60 –80 –100 –60 –80 –100 –120 –120 0 5 10 15 20 0 5 Frequency (MHz) 10 15 SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 1MHz fS = 10MHz –20 –20 –40 –40 Amplitude (dB) Amplitude (dB) fIN = 12MHz –60 –80 –100 –60 –80 –100 –120 –120 0 5 10 15 20 0 1.0 Frequency (MHz) 2.0 3.0 4.0 5.0 Frequency (MHz) DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR 2.0 2.0 fIN = 500kHz fIN = 12MHz 1.0 DLE (LSB) 1.0 DLE (LSB) 20 Frequency (MHz) 0 –1.0 0 –1.0 –2.0 –2.0 0 256 512 768 1024 0 Code 512 768 1024 Code ADS821 SBAS040B 256 www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. 2-TONE INTERMODULATION DYNAMIC PERFORMANCE vs INPUT FREQUENCY 70 0 f1 = 4.47MHz f2 = 4.39MHz SFDR SFDR, SNR (dB) Amplitude (dB) –20 –40 –60 –80 65 60 SNR –100 55 –120 0.0 5.00 10.00 15.00 20.00 0.1 1 Frequency (MHz) 10 SWEPT POWER SFDR SWEPT POWER SNR 100 60 fIN = 12MHz fIN = 12MHz 50 40 SNR (dB) SFDR (dBFS) 80 60 40 30 20 20 10 0 0 –50 –40 –30 –20 –10 0 10 –50 –40 Input Amplitude (dBm) –30 –20 –10 0 10 Input Amplitude (dBm) DYNAMIC PERFORMANCE vs SINGLE-ENDED FULL-SCALE INPUT RANGE INTEGRAL LINEARITY ERROR 4.0 65 fIN = 500kHz SFDR (fIN = 12MHz) 60 Dynamic Range (dB) 2.0 ILE (LSB) 100 Frequency (MHz) 0 –2.0 SFDR (fIN = 500kHz) SNR (fIN = 12MHz) 55 SNR (fIN = 500kHz) 50 45 NOTE: REFTEXT varied, REFB is fixed at the internal value of +1.25V. –4.0 0.0 0.20 0.40 0.60 0.80 40 1.0 2 Code 6 3 4 Single-Ended Full-Scale Input Range (Vp-p) ADS821 www.ti.com SBAS040B TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. SPURIOUS-FREE DYNAMIC RANGE vs TEMPERATURE DYNAMIC PERFORMANCE vs DIFFERENTIAL FULL-SCALE INPUT RANGE 80 75 SFDR (fIN = 12MHz) 65 60 fIN = 500kHz SFDR (fIN = 500kHz) SFDR (dBFS) Dynamic Range (dB) 70 SNR (fIN = 500kHz) 70 60 fIN = 12MHz SNR (fIN = 12MHz) 55 NOTE: REFTEXT varied, REFB is fixed at internal value of +1.25V. 50 70 2 3 –50 4 –25 0 25 50 75 100 Temperature (°C) Differential Full-Scale Input Range (Vp-p) SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE SIGNAL-TO-NOISE RATIO vs TEMPERATURE 59 60 fIN = 500kHz fIN = 500kHz SNR (dB) SINAD (dB) 59 58 57 58 fIN = 12MHz fIN = 10MHz 56 57 –50 –25 0 25 50 75 –50 100 –25 0 50 75 100 POWER DISSIPATION vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 335 Power (mW) 67 IQ (mA) 25 Temperature (°C) Temperature (°C) 66 65 330 325 –50 –25 0 25 50 75 100 Temperature (°C) –25 0 25 50 75 100 Temperature (°C) ADS821 SBAS040B –50 www.ti.com 7 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. GAIN ERROR vs TEMPERATURE OFFSET ERROR vs TEMPERATURE 0 –1.75 Offset (% FSR) Gain (% FSR) –0.25 –0.5 –0.75 –2.0 –1.0 –1.25 –2.25 –50 –25 0 25 50 75 100 –50 –25 0 Temperature (°C) 0 1M –1 0.8M Counts Track-Mode Input Response (dB) 1.2M –2 0.4M –4 0.2M –5 1M 10M 100M 0.0 N–2 1G Frequency (Hz) 8 75 100 0.6M –3 100k 50 OUTPUT NOISE HISTOGRAM (NO SIGNAL) TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH 1 10k 25 Temperature (°C) N–1 N N+1 N+2 Code ADS821 www.ti.com SBAS040B THEORY OF OPERATION Op Amp Bias The ADS821 is a high-speed, sampling A/D converter with pipelining. It uses a fully differential architecture and digital error correction to ensure 10-bit resolution. The differential track-and-hold circuit is shown in Figure 1. The switches are controlled by an internal clock that has a non-overlapping 2phase signal, φ1 and φ2. At the sampling time, the input signal is sampled on the bottom plates of the input capacitors. In the next clock phase, φ2, the bottom plates of the input capacitors are connected together and the feedback capacitors are switched to the op amp output. At this time, the charge redistributes between CI and CH, completing one track-and-hold cycle. The differential output is a held DC representation of the analog input at the sample time. The track-and-hold circuit can also convert a single-ended input signal into a fully differential signal for the quantizer. The pipelined quantizer architecture has 9 stages with each stage containing a 2-bit quantizer and a 2-bit Digital-toAnalog Converter (DAC), as shown in Figure 2. Each 2-bit quantizer stage converts on the edge of the sub-clock, which is twice the frequency of the externally applied clock. The output of each quantizer is fed into its own delay line to IN IN φ1 φ1 CH φ2 CI IN IN φ1 φ2 OUT φ1 OUT φ1 CI CH φ2 φ1 φ1 Input Clock (50%) Op Amp Bias VCM Internal Non-Overlapping Clock φ1 φ2 φ1 FIGURE 1. Input Track-and-Hold Configuration with Timing Signals. Digital Delay Input T&H 2-Bit Flash Stage 1 VCM 2-Bit DAC + Σ – x2 Digital Delay Stage 2 B1 (MSB) 2-Bit DAC B2 Digital Error Correction 2-Bit Flash + Σ – x2 B3 B4 B5 B6 B7 B8 B9 Digital Delay 2-Bit Flash Stage 8 B10 (LSB) 2-Bit DAC + Σ – x2 Stage 9 2-Bit Flash Digital Delay FIGURE 2. Pipeline A/D Converter Architecture. ADS821 SBAS040B www.ti.com 9 time-align it with the data created from the following quantizer stages. This aligned data is fed into a digital error correction circuit that can adjust the output data based on the information found on the redundant bits. This technique gives the ADS821 excellent differential linearity and ensures no missing-codes at the 10-bit level. • For most applications, the clock duty should be set to 50%. For applications requiring no missing codes, however, a slight skew in the duty cycle will improve DNL performance for conversion rates > 35MHz and input frequencies < 2MHz (see Timing Diagram) in the SO package. For the best performance in the SSOP package, the clock should be skewed under all input frequencies with conversion rates > 35MHz. A possible method for skewing the 50% duty cycle source is shown in Figure 4. The output data is available in Straight Offset Binary (SOB) or Binary Two’s Complement (BTC) format. THE ANALOG INPUT AND INTERNAL REFERENCE The analog input of the ADS821 can be configured in various ways and driven with different circuits, depending on the nature of the signal and the level of performance desired. The ADS821 has an internal reference that sets the full-scale input range of the A/D converter. The differential input range has each input centered around the common-mode of +2.25V, with each of the two inputs having a full-scale range of +1.25V to +3.25V. Since each input is 2Vp-p and 180° out-of-phase with the other, a 4V differential input signal to the quantizer results. As shown in Figure 3, the positive full-scale reference (REFT) and the negative full-scale reference (REFB) are brought out for external bypassing. In addition, the commonmode (CM) voltage may be used as a reference to provide the appropriate offset for the driving circuitry. However, care must be taken not to appreciably load this reference node. For more information regarding external references, single-ended inputs, and ADS821 drive circuits, refer to the applications section. ADS821 +3.25V 23 REFT 0.1µF 2kΩ +2.25V 22 To Internal Comparators CM 2kΩ 21 0.1µF REFB VDD VDD IC1, IC2 = ACT04 RV 2kΩ RV = 217Ω, Typical 0.1µF CLKIN 0.1µF IC1 CLKOUT IC2 FIGURE 4. Clock Skew Circuit. DIGITAL OUTPUT DATA The 10-bit output data is provided at CMOS logic levels. There is a 6.5 clock cycle data latency from the start convert signal to the valid output data. The standard output coding is Straight Offset Binary where a full-scale input signal corresponds to all “1’s” at the output. This condition is met with pin 19 LOW or Floating due to an internal pull-down resistor. By applying a high voltage to this pin, a BTC output will be provided where the most significant bit is inverted. The digital outputs of the ADS821 can be set to a high impedance state by driving OE (pin 18) with a logic HIGH. Normal operation is achieved with pin 18 LOW or Floating due to internal pull-down resistors. This function is provided for testability purposes and is not meant to drive digital buses directly or be dynamically changed during the conversion process. +1.25V OUTPUT CODE FIGURE 3. Internal Reference Structure. DIFFERENTIAL INPUT(1) CLOCK REQUIREMENTS The CLK pin accepts a CMOS level clock input. Both the rising and falling edges of the externally applied clock controls the various interstage conversions in the pipeline. Therefore, the clock signal’s jitter, rise-and-fall times and duty cycle can affect conversion performance. • Low clock jitter is critical to SNR performance in frequency-domain signal environments. • Clock rise and fall times should be as short as possible (< 2ns for best performance). +FS (IN = +3.25V, IN = +1.25V) +FS – 1LSB +FS – 2LSB +3/4 Full-Scale +1/2 Full-Scale +1/4 Full-Scale +1LSB Bipolar Zero (IN = IN = +2.25V) –1LSB –1/4 Full-Scale –1/2 Full-Scale –3/4 Full-Scale –FS + 1LSB –FS (IN = +1.25V, IN = +3.25V) SOB PIN 19 FLOATING or LOW BTC PIN 19 HIGH 1111111111 1111111111 1111111110 1110000000 1100000000 1010000000 1000000001 1000000000 0111111111 0110000000 0100000000 0010000000 0000000001 0000000000 0111111111 0111111111 0111111110 0110000000 0100000000 0010000000 0000000001 0000000000 1111111111 1110000000 1100000000 1010000000 1000000001 1000000000 NOTE: (1) In the single-ended input mode, +FS = +4.25V and –FS = +0.25V. TABLE I. Coding Table for the ADS821. 10 ADS821 www.ti.com SBAS040B APPLICATIONS resistor of the OPA694 from the typical 402Ω to 360Ω resulted in a wider bandwidth, thus improving distortion at higher gains. The gain resistor was scaled to 120Ω, 75Ω, and 50Ω for each of the three gain settings. The two 330Ω resistors set the RC time constant and the values can be varied, although higher values will have the effect of moving the corner frequency of the created high-pass filter down. In Figure 6, the –3dB point is set at 4.2kHz. DRIVING THE ADS821 The ADS821 has a differential input with a common-mode of +2.25V. For AC-coupled applications, the simplest way to create this differential input is to drive the primary winding of a transformer with a single-ended input. A differential output is created on the secondary if the center tap is tied to the common-mode (CM) voltage of +2.25V, as per Figure 5. This transformer-coupled input arrangement provides good highfrequency AC performance. It is important to select a transformer that gives low distortion and does not exhibit core saturation at full-scale voltage levels. Since the transformer does not appreciably load the ladder, there is no need to buffer the CM output in this instance. In general, it is advisable to keep the current draw from the CM output pin below 0.5µA to avoid nonlinearity in the internal reference ladder. A FET input operational amplifier such as the OPA130 can provide a buffered reference for driving external circuitry. The analog IN and IN inputs should be bypassed with 22pF capacitors to minimize track-and-hold glitches and to improve high-input frequency performance. Figure 7 illustrates another possible low-cost interface circuit that utilizes resistors and capacitors in place of a transformer. Depending on the signal bandwidth, the component values should be carefully selected in order to maintain the performance outlined in the data sheet. The input capacitors, CIN, and the input resistors, RIN, create a high-pass filter with the lower corner frequency at fC = 1/(2πRINCIN). The corner frequency can be reduced by either increasing the value of RIN or CIN. If the circuit operates with a 50Ω or 75Ω impedance level, the resistors are fixed and only the value of the capacitor can be increased. Usually AC-coupling capacitors are electrolytic or tantalum capacitors with values of 1mF or higher. It should be noted that these large capacitors become inductive with increased input frequency, which could lead to signal amplitude errors or oscillation. To maintain a low ACcoupling impedance throughout the signal band, a small value (e.g. 1µF) ceramic capacitor could be added in parallel with the polarized capacitor. Figure 6 shows an AC-coupled single-ended input interface circuit using the low-cost, current feedback OPA694 as the active gain stage. When testing this configuration in gains of +4, +5.8, and +8.2, it was noted that reducing the feedback Capacitors CSH1 and CSH2 are used to minimize current glitches resulting from the switching in the input track-andhold stage and to improve signal-to-noise performance. These capacitors can also be used to establish a low-pass filter and effectively reduce the noise bandwidth. In order to create a real pole, resistors RSER1 and RSER2 were added in series with each input. The cut off frequency of the filter is determined by fC = 1/(2πRSER • (CSH + CADC)) where RSER is the resistor in series with the input, CSH is the external capacitor from the input to ground, and CADC is the internal input capacitance of the A/D converter (typically 4pF). 22 CM 0.1µF 26 IN AC Input Signal 22pF ADS821 27 IN Mini-Circuits TT1-6-KK81 or Equivalent 22pF Resistors R1 and R2 are used to derive the necessary common-mode voltage from the buffered top and bottom references. The total load of the resistor string should be selected FIGURE 5. AC-Coupled, Single-Ended to Differential Drive Circuit Using a Transformer. +5V –5V 0.1 || 2.2 0.1 || 2.2 VIN OPA694 49.9Ω IN A1 0.1µF 330Ω 22pF 26 ADS821 I/O 27 22 360Ω RG 330Ω 0.1µF IN CM +2.25V 0.1µF FIGURE 6. Low-Cost, AC-Coupled, Single-Ended Input Circuit. ADS821 SBAS040B www.ti.com 11 C1 0.1µF CIN 0.1µF R1 (6kΩ) RSER1(1) 49.9Ω +3.25V Top Reference IN RIN1 25Ω CIN 0.1µF RIN2 25Ω CSH1 22pF R3 1kΩ RSER2(1) ADS8xx VCM C2 0.1µF 49.9Ω R2 (6kΩ) NOTE: (1) indicates optional component. IN CSH2 22pF +1.25V Bottom Reference C3 0.1µF FIGURE 7. AC-Coupled Differential Input Circuit. so that the current does not exceed 1mA. Although the circuit in Figure 7 uses two resistors of equal value so that the common-mode voltage is centered between the top and bottom reference (+2.25V), it is not necessary to do so. In all cases the center point, VCM, should be bypassed to ground in order to provide a low-impedance AC ground. If the signal needs to be DC-coupled to the input of the ADS821, an operational amplifier input circuit is required. In the differential input mode, any single-ended signal must be modified to create a differential signal. This can be accomplished by using two operational amplifiers, one in the noninverting mode for the input and the other amplifier in the inverting mode for the complementary input. The low-distortion circuit in Figure 8 will provide the necessary input shifting required for signals centered around ground. It also employs a diode for output level shifting to ensure a low-distortion +3.25V output swing. See Figure 9 for another DC-coupled circuit. Other amplifiers can be used in place of the OPA860 if the lowest distortion is not necessary. If output level shifting circuits are not used, care must be taken to select operational amplifiers that give the necessary performance when swinging to +3.25V with a ±5V supply operational amplifier. The OPA620 and OPA621, or the lower power OPA650 or OPA820 can be used in place of the OPA860 in Figure 8. In that configuration, the OPA820 will typically swing to within 100mV of positive full scale. The ADS821 can also be configured with a single-ended input full-scale range of +0.25V to +4.25V by tying the complementary input to the common-mode reference voltage, see Figure 10. This configuration will result in increased even-order harmonics, especially at higher input frequencies. This tradeoff, however, may be quite acceptable for time-domain applications. The driving amplifier must give adequate performance with a +0.25V to +4.25V output swing in this case. 12 EXTERNAL REFERENCES AND ADJUSTMENT OF FULL-SCALE RANGE The internal-reference buffers are limited to approximately 1mA of output current. As a result, these internal +1.25V and +3.25V references may be overridden by external references that have at least 18mA (at room temperature) of output drive capability. In this instance, the common-mode voltage will be set halfway between the two references. This feature can be used to adjust the gain error, improve gain drift, or to change the full-scale input range of the ADS821. Changing the fullscale range to a lower value has the benefit of easing the swing requirements of external input amplifiers. The external references can vary as long as the value of the external top reference (REFTEXT) is less than or equal to +3.4V, the value of the external bottom reference (REFBEXT) is greater than or equal to +1.1V, and the difference between the external references are greater than or equal to 800mV. For the differential configuration, the full-scale input range will be set to the external reference values that are selected. For the single-ended mode, the input range is 2 • (REFTEXT – REFBEXT), with the common-mode being centered at (REFTEXT + REFBEXT)/2. Refer to the Typical Characteristics for expected performance versus full-scale input range. The circuit in Figure 11 works completely on a single +5V supply. As a reference element, it uses the microPower reference REF1004-2.5, which is set to a quiescent current of 0.1mA. Amplifier A2 is configured as a follower to buffer the +1.25V generated from the resistor divider. To provide the necessary current drive, a pull-down resistor (RP) is added. Amplifier A1 is configured as an adjustable gain stage, with a range of approximately 1 to 1.32. The pull-up resistor again relieves the op amp from providing the full current drive. The value of the pull-up, pull-down resistors is not critical and can be varied to optimize power consumption. The need for pullup, pull-down resistors depends only on the drive capability of the selected drive amplifier and thus can be omitted. ADS821 www.ti.com SBAS040B +5V 604Ω +5V 301Ω BAS16(1) Optional High Impedance Input Amplifier 301Ω 27 IN OPA842 301Ω 2.49kΩ 0.1µF +5V(2) 22pF 0.1µF –5V 604Ω DC-Coupled Input Signal +5V OPA842 604Ω ADS821 49.9Ω OPA130 +5V –5V 2.49kΩ +2.25V 22 CM +5V 24.9Ω 301Ω Input Level Shift Buffer 301Ω BAS16(1) 26 IN OPA842 0.1µF –5V 22pF 604Ω NOTES: (1) A Philips BAS16 diode or equivalent may be used. (2) Supply bypassing not shown. 301Ω FIGURE 8. A Low-Distortion DC-Coupled, Single-Ended to Differential Input Driver Circuit. DC-Coupled Input Signal 2kΩ 1 3 243Ω –5V B VOUT C 2 E +1 OTA 6 22pF OPA860 8 200Ω 1nF 5 500Ω +5V 1kΩ ADS821 2 50Ω OPA130 1kΩ C1 15pF 200Ω 8 2 E 3 B 3 22 CM 0.1µF 200Ω 500Ω 26 IN 1kΩ 5 OTA +1 C VOUT 6 243Ω –5V OPA860 27 IN 22pF 1 NOTE: Power supplies and bypassing not shown. The measured SNR performance with 12.5MHz input signal is 57dB with this driver circuit. FIGURE 9. A Wideband DC-Coupled, Single-Ended to Differential Input Driver Circuit. ADS821 SBAS040B www.ti.com 13 results. Highly accurate phase-locked signal sources allow high resolution FFT measurements to be made without using data windowing functions. A low jitter signal generator, such as the HP8644A for the test signal, phase-locked with a low jitter HP8022A pulse generator for the A/D converter clock, gives excellent results. Low-pass filtering (or bandpass filtering) of test signals is absolutely necessary to test the low distortion of the ADS821. Using a signal amplitude slightly lower than full scale will allow a small amount of “headroom” so that noise or DC offset voltage will not overrange the A/D converter and cause clipping on signal peaks. 22 CM 0.1µF ADS821 Single-Ended Input Signal 26 IN 27 IN 22pF Full-Scale = +0.25V to +4.25V with internal references. FIGURE 10. Single-Ended Input Connection. DYNAMIC PERFORMANCE DEFINITIONS 1. Signal-to-Noise-and-Distortion Ratio (SINAD): PC-BOARD LAYOUT AND BYPASSING A well-designed, clean PC-board layout will assure proper operation and clean spectral response. Proper grounding and bypassing, short lead lengths, and the use of ground planes are particularly important for high-frequency circuits. Multilayer PC-boards are recommended for best performance but if carefully designed, a two-sided PC-board with large, heavy ground planes can give excellent results. It is recommended that the analog and digital ground pins of the ADS821 be connected directly to the analog ground plane. In our experience, this gives the most consistent results. The A/D converter power-supply commons should be tied together at the analog ground plane. Power supplies should be bypassed with 0.1µF ceramic capacitors as close to the pin as possible. 10 log Sinewave Signal Power Noise + Harmonic Power (first 15 harmonics) 2. Signal-to-Noise Ratio (SNR): 10 log Sinewave Signal Power Noise Power 3. Intermodulation Distortion (IMD): 10 log Highest IMD Pr oduct Power (to 5th− order) Sinewave Signal Power IMD is referenced to the larger of the test signals f1 or f2. Five “bins” either side of peak are used for calculation of fundamental and harmonic power. The “0” frequency bin (DC) is not included in these calculations as it is of little importance in dynamic signal processing applications. DYNAMIC PERFORMANCE TESTING The ADS821 is a high-performance converter and careful attention to test techniques is necessary to achieve accurate +5V A1 1/2 OPA2234 +5V RP 220Ω Top Reference +2.5V to +3.25V 2kΩ 10kΩ 6.2kΩ 10kΩ REF1004 +2.5V 10kΩ(1) A2 0.1µF 1/2 OPA2234 +1.25V 10kΩ Bottom Reference RP 220Ω 10kΩ(1) NOTE: (1) Use parts alternatively for adjustment capability. FIGURE 11. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp. 14 ADS821 www.ti.com SBAS040B FIGURE 12. ADS821 Interface Schematic with AC-Coupling and External Buffers. ADS821 SBAS040B www.ti.com 15 R2 50Ω AC Input Signal Mini-Circuits TT1-6-KK81 or equivalent 0.1µF 0.1µF Ext Clk 22pF R1 50Ω 22pF (1) GND IN IN GND +VS REFT CM REFB +VS MSBI OE +VS CLK +VS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ADS821 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND MSB LSB DNC DNC GND NOTE: (1) All capacitors should be located as close to the pins as the manufacturing process will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended. 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF +5V Dir –541 4 16 19 1 Dir G+ 2 3 17 18 4 5 15 16 7 6 13 8 12 14 9 2 11 19 1 18 G+ 5 15 3 6 14 17 8 7 12 13 9 –541 11 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS821E OBSOLETE SSOP DB 28 TBD Call TI Call TI -40 to 85 ADS821E/1K OBSOLETE SSOP DB 28 TBD Call TI Call TI -40 to 85 ADS821U ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS821U ADS821UG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS821U (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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Addendum-Page 1 Samples MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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