LINER LTC4300A-1 Hot swappable 2-wire bus buffer Datasheet

LTC4300A-1/LTC4300A-2
Hot Swappable
2-Wire Bus Buffers
FEATURES
DESCRIPTION
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The LTC®4300A series hot swappable 2-wire bus buffers
allow I/O card insertion into a live backplane without corruption of the data and clock busses. When the connection is
made, the LTC4300A-1/LTC4300A-2 provide bidirectional
buffering, keeping the backplane and card capacitances
isolated. Rise-time accelerator circuitry* allows the use of
weaker DC pull-up currents while still meeting rise-time
requirements. During insertion, the SDA and SCL lines are
precharged to 1V to minimize bus disturbances.
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Bidirectional Buffer for SDA and SCL Lines
Increases Fanout
Prevents SDA and SCL Corruption During Live
Board Insertion and Removal from Backplane
Isolates Input SDA and SCL Lines from Output
Compatible with I2C, I2C Fast Mode and SMBus
Standards (Up to 400kHz Operation)
Low ICC Chip Disable: <1μA (LTC4300A-1)
READY Open Drain Output (LTC4300A-1)
1V Precharge on all SDA and SCL Lines
Supports Clock Stretching, Arbitration and
Synchronization
5V to 3.3V Level Translation (LTC4300A-2)
High Impedance SDA, SCL Pins for VCC = 0V
Small MSOP 8-Pin Package
APPLICATIONS
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Hot Board Insertion
Servers
Capacitance Buffer/Bus Extender
Desktop Computer
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot
Swap and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are
the property of their respective owners. *Protected by U.S. Patents, including 6650174.
The LTC4300A-1 incorporates a CMOS threshold digital
ENABLE input pin, which forces the part into a low current
mode when driven to ground and sets normal operation
when driven to VCC. It also includes an open drain READY
output pin, which indicates that the backplane and card
sides are connected together. The LTC4300A-2 replaces
the ENABLE pin with a dedicated supply voltage pin, VCC2,
for the card side, providing level shifting between 3.3V
and 5V systems. Both the backplane and card may be
powered with supply voltages ranging from 2.7V to 5.5V,
with no constraints on which supply voltage is higher. The
LTC4300A-2 also replaces the READY pin with a digital
CMOS input pin, ACC, which enables and disables the
rise-time accelerator currents.
The LTC4300A is available in a small 8-pin MSOP package.
TYPICAL APPLICATION
Input–Output Connection t PLH
VCC
3.3V
R1
10k
R2
10k
C1
0.01μF
R3
10k
R4
10k
SCLIN
SCLOUT
SDAIN
SDAOUT
LTC4300A-1
ENABLE
READY
GND
OUTPUT
SIDE
50pF
INPUT
SIDE
150pF
4300a12 TA02
4300a12 TA01
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1
LTC4300A-1/LTC4300A-2
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
VCC to GND .................................................... –0.3 to 7V
VCC2 to GND (LTC4300A-2)............................ –0.3 to 7V
SDAIN, SCLIN, SDAOUT, SCLOUT.................. –0.3 to 7V
READY, ENABLE (LTC4300A-1) ...................... –0.3 to 7V
ACC (LTC4300A-2) ......................................... –0.3 to 7V
Operating Temperature Range
LTC4300A-1C/LTC4300A-2C .................... 0°C to 70°C
LTC4300A-1I/LTC4300A-2I ..................–40°C to 85°C
Storage Temperature Range .................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec)................... 300°C
ENABLE/VCC2*
SCLOUT
SCLIN
GND
1
2
3
4
8
7
6
5
VCC
SDAOUT
SDAIN
READY/ACC*
MS8 PACKAGE
8-LEAD PLASTIC MSOP
*LTC4300A-2
TJMAX = 125°C, θJA = 200°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4300A-1CMS8#PBF
LTC4300A-1CMS8#TRPBF
LTABF
8-Lead Plastic MSOP
0°C to 70°C
LTC4300A-1IMS8#PBF
LTC4300A-1IMS8#TRPBF
LTABG
8-Lead Plastic MSOP
–40°C to 85°C
LTC4300A-2CMS8#PBF
LTC4300A-2CMS8#TRPBF
LTACF
8-Lead Plastic MSOP
0°C to 70°C
LTC4300A-2IMS8#PBF
LTC4300A-2IMS8#TRPBF
LTACG
8-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
l
VCC
Positive Supply Voltage
ICC
Supply Current
VCC = 5.5V, VSDAIN = VSCLIN = 0V, LTC4300A-1
ISD
Supply Current in Shutdown Mode
VENABLE = 0V, LTC4300A-1
VCC2
Card Side Supply Voltage
LTC4300A-2
IVCC1
VCC Supply Current
VSDAIN = VSCLIN = 0V, VCC1 = VCC2 = 5.5V,
LTC4300A-2
IVCC2
VCC2 Supply Current
VSDAOUT = VSCLOUT = 0V, VCC1 = VCC2 = 5.5V,
LTC4300A-2
2.7
l
5.5
5.1
7
0.1
l
2.7
V
mA
μA
5.5
V
3
4.1
mA
2.1
2.9
mA
1.0
1.2
V
95
150
μs
0.5 • VCC
0.9 • VCC
V
Start-Up Circuitry
VPRE
Precharge Voltage
SDA, SCL Floating
tIDLE
Bus Idle Time
VEN
ENABLE Threshold Voltage
LTC4300A-1
VDIS
Disable Threshold Voltage
LTC4300A-1, ENABLE Pin
IEN
ENABLE Input Current
ENABLE from 0V to VCC, LTC4300A-1
l
0.8
l
50
0.1 • VCC
0.5 • VCC
±0.1
V
±1
μA
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LTC4300A-1/LTC4300A-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
SYMBOL PARAMETER
tPHL
tPLH
CONDITIONS
MIN
TYP
MAX
UNITS
ENABLE Delay, On-Off
LTC4300A-1
10
ns
READY Delay, Off-On
LTC4300A-1
10
ns
ENABLE Delay, Off-On
LTC4300A-1
95
μs
READY Delay, On-Off
LTC4300A-1
10
ns
IOFF
READY OFF State Leakage Current
LTC4300A-1
VOL
READY Output Low Voltage
IPULLUP = 3mA, LTC4300A-1
±0.1
l
μA
0.4
V
Rise-Time Accelerators
IPULLUPAC Transient Boosted Pull-Up Current
VACCDIS
Accelerator Disable Threshold
Positive Transition on SDA,SCL, VCC = 2.7V,
Slew Rate = 1.25V/μs (Note 2),
LTC4300A-2, ACC = 0.7 • VCC2, VCC2 = 2.7V
LTC4300A-2
1
2
0.3 • VCC2
0.5 • VCC2
mA
V
VACCEN
Accelerator Enable Threshold
LTC4300A-2
0.5 • VCC2
0.7 • VCC2
V
IVACC
ACC Input Current
LTC4300A-2
± 0.1
±1
μA
tPDOFF
ACC Delay, On/Off
LTC4300A-2
5
ns
Input-Output Connection
VOS
Input-Output Offset Voltage
10k to VCC on SDA, SCL, VCC = 3.3V (Note 3),
LTC4300A-2, VCC2 = 3.3V, VIN = 0.2V
fSCL, SDA
Operating Frequency
Guaranteed by Design, Not Subject to Test
CIN
Digital Input Capacitance
Guaranteed by Design, Not Subject to Test
VOL
Output Low Voltage, Input = 0V
SDA, SCL Pins, ISINK = 3mA, VCC = 2.7V,
VCC2 = 2.7V, LTC4300A-2
ILEAK
Input Leakage Current
SDA, SCL Pins = VCC = 5.5V,
LTC4300A-2, VCC2 = 5.5V
l
0
100
0
l
0
175
mV
400
kHz
10
pF
0.4
V
±5
μA
400
kHz
Timing Characteristics
fI2C
I2C Operating Frequency
(Note 4)
0
tBUF
Bus Free Time Between Stop
and Start Condition
(Note 4)
1.3
μs
thD,STA
Hold Time After (Repeated)
Start Condition
(Note 4)
0.6
μs
tsu,STA
Repeated Start Condition Setup Time
(Note 4)
0.6
μs
tsu,STO
Stop Condition Setup Time
(Note 4)
0.6
μs
thD, DAT
Data Hold Time
(Note 4)
300
ns
tsu, DAT
Data Setup Time
(Note 4)
100
ns
tLOW
Clock Low Period
(Note 4)
1.3
μs
tHIGH
Clock High Period
(Note 4)
0.6
μs
tf
Clock, Data Fall Time
(Notes 4, 5)
tr
Clock, Data Rise Time
tPHL,SKEW High-to-Low Propagation Delay
Skew, SCL-SDA
20 + 0.1 • CB
(Notes 4, 5)
20 + 0.1 • CB
300
ns
300
ns
LTC4300A-1: VCC = 2.7V; VCC = 5.5V (Note 6)
l
0
±75
ns
LTC4300A-2: VCC = 2.7V, VCC2 = 5.5V;
VCC = 5.5V; VCC2 = 2.7V (Note 6)
l
0
±75
ns
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LTC4300A-1/LTC4300A-2
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: IPULLUPAC varies with temperature and VCC voltage, as shown in
the Typical Performance Characteristics section.
Note 3: The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and VCC voltage is shown in the Typical Performance
Characteristics section.
Note 4: Guaranteed by design, not subject to test.
Note 5: CB = total capacitance of one bus line in pF.
Note 6: These tests measure the difference in high-to-low propagation
delay tPHL between the clock and data channels. The delay on each
channel is measured from the 50% point of the falling driven input signal
to the 50% point of the output driven by the LTC4300A-1/LTC4300A-2.
The skew is defined as (tPHL(SCL) – tPHL(SDA)). Testing is performed in
both directions—from input bus to output bus and vice versa. Tests are
performed with approximately 500pF of distributed equivalent capacitance
on each SDA and SCL pin.
TYPICAL PERFORMANCE CHARACTERISTICS
Input – Output tPHL vs
Temperature (LTC4300A-1)
ICC vs Temperature (LTC4300A-1)
5.3
100
5.2
VCC = 2.7V
VCC = 5.5V
5.1
80
VCC = 3.3V
4.9
t PHL (ns)
ICC (mA)
5.0
4.8
4.7
VCC = 2.7V
4.6
4.5
60
40
VCC = 5.5V
20
CIN = COUT = 100pF
RPULLUPIN = RPULLUPOUT = 10k
4.4
4.3
–40
25
TEMPERATURE (°C)
0
–50
85
–25
0
25
50
TEMPERATURE (°C)
75
4300a12 G02
4300a12 G01
IPULLUPAC vs Temperature
Connection Circuitry VOUT – VIN
300
12
VCC = 5V
8
6
VCC = 3V
4
TA = 25°C
VIN = 0V
250
VOUT – VIN (mV)
IPULLUPAC (mA)
10
100
200
150
VCC = 5V
100
VCC = 3.3V
50
2
VCC = 2.7V
0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
4300a12 G03
0
0
10,000
20,000
30,000
RPULLUP (Ω)
40,000
4300a12 G04
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LTC4300A-1/LTC4300A-2
PIN FUNCTIONS
ENABLE/VCC2 (Pin 1): Chip Enable Pin/Card Supply Voltage. For the LTC4300A-1, this is a digital CMOS threshold
input pin. Grounding this pin puts the part in a low current
(<1μA) mode. It also disables the rise-time accelerators,
disables the bus precharge circuitry, drives READY low,
isolates SDAIN from SDAOUT and isolates SCLIN from
SCLOUT. Drive ENABLE all the way to VCC for normal
operation. Connect ENABLE to VCC if this feature is not
being used. For the LTC4300A-2, this is the supply voltage
for the devices on the card I2C busses. Connect pull-up
resistors from SDAOUT and SCLOUT to this pin. Place a
bypass capacitor of at least 0.01μF close to this pin for
best results.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the SCL bus on the card.
SCLIN (Pin 3): Serial Clock Input. Connect this pin to the
SCL bus on the backplane.
GND (Pin 4): Ground. Connect this pin to a ground plane
for best results.
READY/ACC (Pin 5): Connection Flag/Rise-Time Accelerator Control. For the LTC4300A-1, this is an open-drain
NMOS output which pulls low when either ENABLE is
low or the start-up sequence described in the Operation
section has not been completed. READY goes high when
ENABLE is high and start-up is complete. Connect a 10k
resistor from this pin to VCC to provide the pull up. For
the LTC4300A-2, this is a CMOS threshold digital input
pin that enables and disables the rise-time accelerators
on all four SDA and SCL pins. Drive ACC all the way to the
VCC2 supply voltage to enable all four accelerators; drive
ACC to ground to turn them off.
SDAIN (Pin 6): Serial Data Input. Connect this pin to the
SDA bus on the backplane.
SDAOUT (Pin 7): Serial Data Output. Connect this pin to
the SDA bus on the card.
VCC (Pin 8): Main Input Power Supply from Backplane.
This is the supply voltage for the devices on the backplane I2C busses. Connect pull-up resistors from SDAIN
and SCLIN (and also from SDAOUT and SCLOUT for the
LTC4300A-1) to this pin. Place a bypass capacitor of at
least 0.01μF close to this pin for best results.
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LTC4300A-1/LTC4300A-2
BLOCK DIAGRAM
(LTC4300A-1)
2-Wire Bus Buffer and Hot Swap™ Controller
2mA
2mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
8 VCC
BACKPLANE-TO-CARD
CONNECTION
SDAIN 6
CONNECT
74 SDAOUT
CONNECT
CONNECT
ENABLE
100k
RCH1
100k
RCH3
1V
PRECHARGE
100k
RCH2
100k
RCH4
2mA
2mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
SCLIN 3
CONNECT
2 SCLOUT
+
CONNECT
–
VCC – 1V
+
+
–
–
STOP BIT AND BUS IDLE
0.5μA
+
0.55VCC/
0.45VCC
UVLO
ENABLE 1
–
5 READY
20pF
CONNECT
95μs
DELAY,
RISING
ONLY
RD
QB
4 GND
S
0.5pF
CONNECT
4300A1 BD
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LTC4300A-1/LTC4300A-2
BLOCK DIAGRAM
(LTC4300A-2)
2-Wire Bus Buffer and Hot Swap Controller
VCC 8
2mA
2mA
SLEW RATE
DETECTOR
ACC
1 VCC2
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
SDAIN 6
74 SDAOUT
CONNECT
CONNECT
100k
RCH1
CONNECT
100k
RCH3
1V
PRECHARGE
100k
RCH2
100k
RCH4
2mA
2mA
SLEW RATE
DETECTOR
ACC
SLEW RATE
DETECTOR
5 ACC
BACKPLANE-TO-CARD
CONNECTION
SCLIN 3
CONNECT
2 SCLOUT
+
CONNECT
–
+
+
–
–
VCC2 – 1V
STOP BIT AND BUS IDLE
0.5μA
+
0.55VCC/
0.45VCC
UVLO
–
20pF
CONNECT CONNECT
95μs
DELAY,
RISING
ONLY
RD
QB
S
4 GND
0.5pF
4300A2 BD
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LTC4300A-1/LTC4300A-2
OPERATION
Start-Up
When the LTC4300A first receives power on its VCC pin,
either during power-up or during live insertion, it starts
in an undervoltage lockout (UVLO) state, ignoring any
activity on the SDA and SCL pins until VCC rises above
2.5V. For the LTC4300A-2, the part also waits for VCC2 to
rise above 2V. This ensures that the part does not try to
function until it has enough voltage to do so.
During this time, the 1V precharge circuitry is also active and forces 1V through 100k nominal resistors to the
SDA and SCL pins. Because the I/O card is being plugged
into a live backplane, the voltage on the backplane SDA
and SCL busses may be anywhere between 0V and VCC.
Precharging the SCL and SDA pins to 1V minimizes the
worst-case voltage differential these pins will see at the
moment of connection, therefore minimizing the amount
of disturbance caused by the I/O card.
Once the LTC4300A comes out of UVLO, it assumes that
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at the
same time as itself. Therefore, it looks for either a stop bit
or bus idle condition on the backplane side to indicate the
completion of a data transaction. When either one occurs,
the part also verifies that both the SDAOUT and SCLOUT
voltages are high. When all of these conditions are met,
the input-to-output connection circuitry is activated, joining
the SDA and SCL busses on the I/O card with those on
the backplane, and the rise time accelerators are enabled.
Connection Circuitry
Once the connection circuitry is activated, the functionality
of the SDAIN and SDAOUT pins is identical. A low forced on
either pin at any time results in both pin voltages being low.
For proper operation, logic low input voltages should be
no higher than 0.4V with respect to the ground pin voltage
of the LTC4300A. SDAIN and SDAOUT enter a logic high
state only when all devices on both SDAIN and SDAOUT
release high. The same is true for SCLIN and SCLOUT.
This important feature ensures that clock stretching, clock
synchronization, arbitration and the acknowledge protocol
always work, regardless of how the devices in the system
are tied to the LTC4300A.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms, as
described here.
Input to Output Offset Voltage
When a logic low voltage, VLOW1, is driven on any of the
LTC4300A’s data or clock pins, the LTC4300A regulates
the voltage on the other side of the chip (call it VLOW2)
to a slightly higher voltage, as directed by the following
equation:
VLOW2 = VLOW1 + 75mV + (VCC/R) • 100
where R is the bus pull-up resistance in ohms. For example, if a device is forcing SDAOUT to 10mV where
VCC = 3.3V and the pull-up resistor R on SDAIN is 10k,
then the voltage on SDAIN = 10mV + 75mV + (3.3/10000)
• 100 = 118mV. See the Typical Performance Characteristics section for curves showing the offset voltage as a
function of VCC and R.
Propagation Delays
During a rising edge, the rise-time on each side is determined by the combined pull-up current of the LTC4300A
boost current and the bus resistor and the equivalent
capacitance on the line. If the pull-up currents are the
same, a difference in rise-time occurs which is directly
proportional to the difference in capacitance between the
two sides. This effect is displayed in Figure 1 for VCC =
3.3V and a 10k pull-up resistor on each side (50pF on
one side and 150pF on the other). Since the output side
has less capacitance than the input, it rises faster and the
effective tPLH is negative.
There is a finite propagation delay, tPHL, through the connection circuitry for falling waveforms. Figure 2 shows
the falling edge waveforms for the same VCC, pull-up
resistors and equivalent capacitance conditions as used
in Figure 1. An external NMOS device pulls down the voltage on the side with 150pF capacitance; the LTC4300A
pulls down the voltage on the opposite side, with a delay
of 55ns. This delay is always positive and is a function of
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LTC4300A-1/LTC4300A-2
OPERATION
OUTPUT
SIDE
50pF
INPUT
SIDE
150pF
INPUT
SIDE
150pF
4300a12 F01
OUTPUT
SIDE
50pF
4300a12 F02
Figure 1. Input–Output Connection t PLH
Figure 2. Input–Output Connection t PHL
supply voltage, temperature and the pull-up resistors and
equivalent bus capacitances on both sides of the bus. The
Typical Performance Characteristics section shows tPHL
as a function of temperature and voltage for 10k pull-up
resistors and 100pF equivalent capacitance on both sides
of the part. By comparison with Figure 2, the VCC = 3.3V
curve shows that increasing the capacitance from 50pF
to 100pF results in a tPHL increase from 55ns to 75ns.
Larger output capacitances translate to longer delays (up
to 150ns). Users must quantify the difference in propagation times for a rising edge versus a falling edge in their
systems and adjust setup and hold times accordingly.
using the rise-time accelerators, which are activated at a
DC threshold of below 0.65V, the worst-case rise-time is:
(2.25V – 0.65V) • 200pF/1mA = 320ns, which meets the
1μs rise-time requirement.
Rise-Time Accelerators
Once connection has been established, rise-time accelerator circuits on all four SDA and SCL pins are activated.
These allow the user to choose weaker DC pull-up currents on the bus, reducing power consumption while still
meeting system rise-time requirements. During positive
bus transitions, the LTC4300A switches in 2mA (typical)
of current to quickly slew the SDA and SCL lines once
their DC voltages exceed 0.6V. Using a general rule of
20pF of capacitance for every device on the bus (10pF for
the device and 10pF for interconnect), choose a pull-up
current so that the bus will rise on its own at a rate of at
least 1.25V/μs to guarantee activation of the accelerators.
For example, assume an SMBus system with VCC = 3V,
a 10k pull-up resistor and equivalent bus capacitance of
200pF. The rise-time of an SMBus system is calculated
from (VIL(MAX) – 0.15V) to (VIH(MIN) + 0.15V), or 0.65V
to 2.25V. It takes an RC circuit 0.92 time constants to
traverse this voltage for a 3V supply; in this case, 0.92
• (10k • 200pF) = 1.84μs. Thus, the system exceeds the
maximum allowed rise-time of 1μs by 84%. However,
READY Digital Output (LTC4300A-1)
This pin provides a digital flag which is low when either
ENABLE is low or the start-up sequence described earlier
in this section has not been completed. READY goes high
when ENABLE is high and start-up is complete. The pin
is driven by an open drain pull-down capable of sinking
3mA while holding 0.4V on the pin. Connect a resistor of
10k to VCC to provide the pull-up. This feature is available
for the LTC4300A-1 only.
ENABLE Low Current Disable (LTC4300A-1)
Grounding the ENABLE pin disconnects the backplane side
from the card side, disables the rise-time accelerators,
drives READY low, disables the bus precharge circuitry
and puts the part in a near-zero current state. When the
pin voltage is driven all the way to VCC, the part waits for
data transactions on both the backplane and card sides to
be complete (as described in the Start-Up section) before
reconnecting the two sides. This feature is available for
the LTC4300A-1 only.
ACC Boost Current Enable (LTC4300A-2)
Users having lightly loaded systems may wish to disable
the rise-time accelerators. Driving this pin to ground turns
off the rise-time accelerators on all four SDA and SCL
pins. Driving this pin to the VCC2 voltage enables normal
operation of the rise-time accelerators, as described in
the Rise-Time Accelerators section above. This feature is
available for the LTC4300A-2 only.
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LTC4300A-1/LTC4300A-2
APPLICATIONS INFORMATION
Resistor Pull-Up Value Selection
The system pull-up resistors must be strong enough to
provide a positive slew rate of 1.25V/μs on the SDA and
SCL pins, in order to activate the boost pull-up currents
during rising edges. Choose maximum resistor value R
using the formula:
R ≤ (VCC(MIN) – 0.6) (800,000) / C
Live Insertion and Capacitance Buffering Application
where R is the pull-up resistor value in ohms, VCC(MIN)
is the minimum VCC voltage and C is the equivalent bus
capacitance in picofarads (pF).
BACKPLANE
SDA
SCL
STAGGERED CONNECTOR
BD_SEL
R2
10k
Figures 3 through 6 illustrate the usage of the LTC4300A
in applications that take advantage of both its hot swap
controlling and capacitance buffering features. In all of
BACKPLANE
CONNECTOR
VCC
R1
10k
In addition, regardless of the bus capacitance, always
choose R ≤ 16k for VCC = 5.5V maximum, R ≤ 24k for
VCC = 3.6V maximum. The start-up circuitry requires
logic high voltages on SDAOUT and SCLOUT to connect
the backplane to the card, and these pull-up values are
needed to overcome the precharge voltage.
POWER SUPPLY
HOT SWAP
I/O PERIPHERAL CARD 1
R3
10k
CARD
ENABLE/DISABLE
ENABLE
SDAIN
SCLIN
STAGGERED CONNECTOR
POWER SUPPLY
HOT SWAP
C1
0.01μF
R4
10k
R5
10k
R6
10k
VCC
SDAOUT
CARD_SDA
U1
LTC4300A-1
SCLOUT
CARD_SCL
GND
READY
I/O PERIPHERAL CARD 2
R7
10k
CARD
ENABLE/DISABLE
ENABLE
SDAIN
SCLIN
C3
0.01μF
R8
10k
R9
10k
R10
10k
VCC
SDAOUT
CARD2_SDA
U2
LTC4300A-1
SCLOUT
CARD2_SCL
GND
READY
STAGGERED CONNECTOR
ttt
POWER SUPPLY
HOT SWAP
I/O PERIPHERAL CARD N
R11
10k
CARD
ENABLE/DISABLE
ENABLE
SDAIN
SCLIN
C5
0.01μF
R12
10k
R13
10k
R14
10k
VCC
SDAOUT
CARDN_SDA
U3
LTC4300A-1
SCLOUT
CARDN_SCL
GND
READY
4300a12 F03
Figure 3. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4300A-1 in a CompactPCI System
4300a12fa
10
LTC4300A-1/LTC4300A-2
APPLICATIONS INFORMATION
these applications, note that if the I/O cards were plugged
directly into the backplane, all of the backplane and card
capacitances would add directly together, making riseand fall-time requirements difficult to meet. Placing a
LTC4300A on the edge of each card, however, isolates the
card capacitance from the backplane. For a given I/O card,
the LTC4300A drives the capacitance of everything on the
card and the backplane must drive only the capacitance
of the LTC4300A, which is less than 10pF.
VCC is monitored by a filtered UVLO circuit. With the VCC
voltage powering up after all other pins have established
connection, the UVLO circuit ensures that the backplane
and card data and clock busses are not connected until
the transients associated with live insertion have settled.
Owing to their small capacitance, the SDAIN and SCLIN
pins cause minimal disturbance on the backplane busses
when they make contact with the connector.
Figure 4 shows the LTC4300A-2 in a CompactPCI configuration. The LTC4300A-2 receives its VCC voltage from
one of the long “early power” pins. Because this power is
not switched, add a 5Ω to 10Ω resistor between the VCC
pins of the connector and the LTC4300A-2, as shown in
Figure 3 shows the LTC4300A-1 in a CompactPCI configuration. Connect VCC and ENABLE to the output of one of
the CompactPCI power supply Hot Swap circuits. Use a
pull-up resistor to ENABLE for a card side enable/disable.
VCC2
BD_SEL
VCC
SDA
R2
10k
STAGGERED CONNECTOR
R1
10k
I/O PERIPHERAL CARD 1
POWER SUPPLY
HOT SWAP
C1
0.01μF
5.1Ω
VCC
SDAIN
SCLIN
C2 0.01μF
R4
10k
R5
10k
R6
10k
VCC2
SDAOUT
CARD_SDA
U1
LTC4300A-2
SCLOUT
CARD_SCL
ACC
GND
I/O PERIPHERAL CARD 2
POWER SUPPLY
HOT SWAP
C3
0.01μF
5.1Ω
VCC
SDAIN
SCLIN
C4 0.01μF
R8
10k
R9
10k
R10
10k
VCC2
SDAOUT
CARD2_SDA
U2
LTC4300A-2
SCLOUT
CARD2_SCL
ACC
GND
ttt
STAGGERED CONNECTOR
SCL
BACKPLANE
CONNECTOR
STAGGERED CONNECTOR
BACKPLANE
I/O PERIPHERAL CARD N
POWER SUPPLY
HOT SWAP
C5
0.01μF
5.1Ω
VCC
SDAIN
SCLIN
C6 0.01μF
R12
10k
R13
10k
R14
10k
VCC2
SDAOUT
CARDN_SDA
U3
LTC4300A-2
SCLOUT
CARDN_SCL
GND
ACC
4300a12 F04
Figure 4. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4300A-2 in a CompactPCI System
4300a12fa
11
LTC4300A-1/LTC4300A-2
APPLICATIONS INFORMATION
the figure. In addition, make sure that the VCC bypassing
on the backplane is large compared to the 0.01μF bypass
capacitor on the card. Establishing early power VCC
ensures that the 1V precharge voltage is present at the
SDAIN and SCLIN pins before they make contact. Connect VCC2 to the output of one of the CompactPCI power
supply Hot Swap circuits. VCC2 is monitored by a filtered
UVLO circuit. With the VCC2 voltage powering up after all
other pins have established connection, the UVLO circuit
ensures that the backplane and card data and clock busses
are not connected until the transients associated with live
insertion have settled.
Figure 5 shows the LTC4300A-1 in a PCI application,
where all of the pins have the same length. In this case,
connect an RC series circuit on the I/O card between VCC
and ENABLE. An RC product of 10ms provides a filter to
prevent the LTC4300A-1 from becoming activated until
the transients associated with live insertion have settled.
BACKPLANE
Figure 6 shows the LTC4300A-2 in an application where the
user has a custom connector with pins of three different
lengths available. Making VCC2 the shortest pin ensures
that all other pins are firmly connected before VCC2 receives
any voltage. A filtered UVLO circuit on VCC2 ensures that
the VCC2 pin is firmly connected before the LTC4300A-2
connects the backplane to the card.
Repeater/Bus Extender Application
Users who wish to connect two 2-wire systems separated
by a distance can do so by connecting two LTC4300A-1s
back-to-back, as shown in Figure 7. The I2C specification
allows for 400pF maximum bus capacitance, severely
limiting the length of the bus. The SMBus specification
places no restriction on bus capacitance, but the limited
impedances of devices connected to the bus require
systems to remain small if rise- and fall-time specifications are to be met. The strong pull-up and pull-down
impedances of the LTC4300A-1 are capable of meeting
BACKPLANE
CONNECTOR
I/O PERIPHERAL CARD 1
VCC
R1
10k
R2
10k
C1
0.01μF
R3
100k
ENABLE
SDAIN
SDA
SCLIN
SCL
R5
10k
R6
10k
VCC
SDAOUT
CARD_SDA
U1
LTC4300A-1
SCLOUT
CARD_SCL
GND
C2 0.1μF
R4
10k
READY
I/O PERIPHERAL CARD 2
C3
0.01μF
R7
100k
ENABLE
SDAIN
SCLIN
C4 0.1μF
R8
10k
R9
10k
R10
10k
VCC
SDAOUT
CARD2_SDA
U2
LTC4300A-1
SCLOUT
CARD2_SCL
GND
READY
t
t
t
4300a12 F05
Figure 5. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4300A-1 in a PCI System
4300a12fa
12
LTC4300A-1/LTC4300A-2
APPLICATIONS INFORMATION
BACKPLANE
CONNECTOR
BACKPLANE
I/O PERIPHERAL CARD 1
R1
10k
STAGGERED CONNECTOR
VCC2
R2
10k
VCC
SDA
SCL
C1
0.01μF
VCC
SDAIN
SCLIN
R5
10k
R6
10k
VCC2
SDAOUT
CARD_SDA
U1
LTC4300A-2
SCLOUT
CARD_SCL
ACC
GND
C2 0.01μF
R4
10k
STAGGERED CONNECTOR
I/O PERIPHERAL CARD 2
C3
0.01μF
VCC
SDAIN
SCLIN
C4 0.01μF
R8
10k
R9
10k
R10
10k
VCC2
SDAOUT
CARD2_SDA
U2
LTC4300A-2
SCLOUT
CARD2_SCL
ACC
GND
t
t
t
4300a12 F06
Figure 6. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4300A-2 with a Custom Connector
2-WIRE SYSTEM 2
2-WIRE SYSTEM 1
VCC = 5V
VCC
C1
0.01μF
R1
10k
R4
10k
C2
0.01μF
R5
10k
LTC4300A-1
R2
R3
5.1k 5.1k
R6
10k
R7
10k
LTC4300A-1
R8
10k
VCC
VCC
ENABLE
SDAOUT
SDAOUT
ENABLE
SDA1
SDAIN
SCLOUT
SCLOUT
SDAIN
SDA1
SCL1
TO OTHER
SYSTEM 1
DEVICES
SCLIN
READY
READY
SCLIN
SCL1
TO OTHER
SYSTEM 2
DEVICES
GND
LONG
DISTANCE
BUS
GND
4300a12 F07
Figure 7. Repeater/Bus Extender Application
4300a12fa
13
LTC4300A-1/LTC4300A-2
APPLICATIONS INFORMATION
rise- and fall-time specifications for 1nF of capacitance,
thus allowing much more interconnect distance. In this
situation, the differential ground voltage between the two
systems may limit the allowed distance, because a valid
logic low voltage with respect to the ground at one end
of the system may violate the allowed VOL specification
with respect to the ground at the other end. In addition,
the connection circuitry offset voltages of the back-toback LTC4300A-1s add together, directly contributing
to the same problem.
5V to 3.3V Level Translator and Power Supply
Redundancy (LTC4300A-2)
Systems requiring different supply voltages for the backplane side and the card side can use the LTC4300A-2, as
shown in Figure 9. The pull-up resistors on the card side
connect from SDAOUT to SCLOUT to VCC2, and those on
the backplane side connect from SDAIN and SCLIN to VCC.
The LTC4300A-2 functions for voltages ranging from 2.7V
to 5.5V on both VCC and VCC2. There is no constraint on
the voltage magnitudes of VCC and VCC2 with respect to
each other.
Systems with Disparate Supply Voltages
(LTC4300A-1)
This application also provides power supply redundancy.
If the VCC2 voltage falls below its UVLO threshold, the
LTC4300A-2 disconnects the backplane from the card,
so that the backplane can continue to function. If the VCC
voltage falls below its UVLO threshold and the VCC2 voltage remains active, ground the ACC pin to ensure proper
operation.
In large 2-wire systems, the VCC voltages seen by devices
at various points in the system can differ by a few hundred millivolts or more. This situation is well modelled
by a series resistor in the VCC line, as shown in Figure 8.
For proper operation of the LTC4300A-1, make sure that
VCC(BUS) ≥ VCC(LTC4300A) – 0.5V.
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
0.889 ±0.127
(.035 ±.005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.254
(.010)
8
7 6 5
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
DETAIL “A”
0.52
(.0205)
REF
0° – 6° TYP
GAUGE PLANE
0.42 ± 0.038
(.0165 ±.0015)
TYP
0.65
(.0256)
BSC
1
0.53 ±0.152
(.021 ±.006)
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
1.10
(.043)
MAX
2 3
4
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS8) 0307 REV F
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
4300a12fa
14
LTC4300A-1/LTC4300A-2
REVISION HISTORY
REV
DATE
DESCRIPTION
A
7/12
Added TPHL,SKEW parameter to Electrical Characteristics
PAGE NUMBER
3
4300a12fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC4300A-1/LTC4300A-2
TYPICAL APPLICATIONS
RDROP
VCC (LTC4300A)
VCC (BUS)
R1
10k
C2
0.01μF
R2
10k
R3
10k
SDAIN
SCL
SCLIN
R5
10k
VCC
SDAOUT
SDA2
U1
LTC4300A-1
SCLOUT
SCL2
ENABLE
SDA
R4
10k
READY
GND
4300a12 F08
Figure 8. System with Disparate VCC Voltages
VCC
5V
R1
10k
C2
0.01μF
R4
10k
SDA
SCL
C1
0.01μF
SDAIN
VCC
VCC2
SDAOUT
SCLIN
U1
LTC4300A-2
SCLOUT
GND
CARD_VCC, 3.3V
R3
10k
R2
10k
CARD_SDA
CARD_SCL
ACC
4300a12 F09
Figure 9. 5V to 3.3V Level Translator
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PART NUMBER
DESCRIPTION
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4300a12fa
16 Linear Technology Corporation
LT 0712 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2001