TI1 LMH6702WG-QMLV 1.7 ghz, ultra low distortion, wideband op amp Datasheet

LMH6702QML
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SNOSAQ2E – JULY 2005 – REVISED MARCH 2013
1.7 GHz, Ultra Low Distortion, Wideband Op Amp
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FEATURES
DESCRIPTION
•
The LMH6702 is a very wideband, DC coupled
monolithic operational amplifier designed specifically
for wide dynamic range systems requiring exceptional
signal fidelity. Benefitting from TI's current feedback
architecture, the LMH6702 offers unity gain stability at
exceptional speed without need for external
compensation.
1
2
•
•
•
•
•
•
•
•
•
VS = ±5V, TA = 25°C, AV = +2V/V, RL = 100Ω,
VOUT = 2VPP, Typical Unless Noted:
Available with Radiation Ensurance
– High Dose Rate 300 krad(Si)
– ELDRS Free 300 krad(Si)
−3dB Bandwidth (VOUT = 0.2 VPP) 720 MHz
Low Noise 1.83nV/√Hz
Fast Settling to 0.1% 13.4ns
Fast Slew Rate 3100V/μs
Supply Current 12.5mA
Output Current 80mA
Low Intermodulation Distortion (75MHz)
−67dBc
Improved Replacement for CLC409 and
CLC449
Wide dynamic range systems such as radar and
communication receivers, requiring a wideband
amplifier offering exceptional signal purity, will find the
LMH6702's low input referred noise and low harmonic
and intermodulation distortion make it an attractive
high speed solution.
The LMH6702 is constructed using TI's VIP10
complimentary bipolar process and TI's proven
current feedback architecture.
APPLICATIONS
•
•
•
•
•
•
With its 720MHz bandwidth (AV = 2V/V, VO = 2VPP),
10-bit distortion levels through 60MHz (RL = 100Ω),
1.83nV/√Hz input referred noise and 12.5mA supply
current, the LMH6702 is the ideal driver or buffer for
high-speed flash A/D and D/A converters.
Flash A/D Driver
D/A transimpedance Buffer
Wide Dynamic Range IF Amp
Radar/Communication Receivers
Line Driver
High Resolution Video
Connection Diagrams
N/C
1
8
N/C
VINV
2
7
VNON-INV
3
-VCC
4
N/C
1
10
+VCC
VINV
2
9
+VCC
6
VOUT
VNON-INV
3
8
VOUT
5
N/C
-VCC
4
7
N/C
N/C
5
6
N/C
Figure 1. 8-Lead CDIP (NAB)
Top View
N/C
Figure 2. 10-Lead CLGA (NAC)
Top View
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LMH6702QML
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Absolute Maximum Ratings (1)
Supply Voltage (VCC)
±6.75VDC
V-to V+
Common Mode Input Voltage (VCM)
Power Dissipation (PD)
(2)
1W
Junction Temperature (TJ)
+175°C
Lead Temperature (soldering, 10 seconds)
+300°C
-65°C ≤ TA ≤ +150°C
Storage Temperature Range
Thermal Resistance
θJA
CDIP (Still Air)
170°C/W
CDIP (500LF/Min Air Flow)
100°C/W
CLGA (Still Air)
220°C/W
CLGA (500LF/Min Air Flow)
150°C/W
θJC
CDIP
35°C/W
CLGA
37°C/W
Package Weight (Typical)
CDIP
1078mg
CLGA
ESD Tolerance
(1)
(2)
(3)
227mg
(3)
1000V
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions see the Electrical
Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade
when the device is not operated under the listed test conditions.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
Human body model, 1.5kΩ in series with 100pF.
Recommended Operating Conditions
Supply Voltage (VCC)
±5VDC to ±6VDC
Gain Range
±1 to ±10
Ambient Operating Temperature Range (TA)
-55°C to +125°C
Quality Conformance Inspection
MIL-STD-883, Method 5005, Group A
2
Subgroup
Description
Temp ( C)
1
Static tests at
+25
2
Static tests at
+125
3
Static tests at
-55
4
Dynamic tests at
+25
5
Dynamic tests at
+125
6
Dynamic tests at
-55
7
Functional tests at
+25
8A
Functional tests at
+125
8B
Functional tests at
-55
9
Switching tests at
+25
10
Switching tests at
+125
11
Switching tests at
-55
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LMH6702 Electrical Characteristics DC Parameters (1) (2)
The following conditions apply, unless otherwise specified.
RL = 100Ω, VCC = ±5VDC, AV = +2 feedback resistor (RF) = 250Ω, gain resistor (RG) = 250Ω
Symbol
Parameter
IBN
Input Bias Current, Noninverting
IBI
Conditions
Input Bias Current, Iverting
VIO
Input Offset Voltage
ICC
Supply Current, no load
RL = ∞
PSSR
Power Supply Rejection Ratio
-VCC = -4.5V to -5.0V,
+VCC = +4.5V to +5.0V
(1)
(2)
Notes
Min
Max
Unit
Subgroups
-15
+15
μA
1, 2
-21
+21
μA
3
-30
+30
μA
1, 2
-34
+34
μA
3
-4.5
+4.5
mV
1, 3
-6.0
+6.0
mV
2
15
mA
1, 2, 3
dB
1, 2, 3
45
The algebraic convention, whereby the most negative value is a minimum and most positive is a maximum, is used in this table.
Negative cur rent shall be defined as convential current flow out of a device terminal.
Pre and Post irradiation limits are identical to those listed under the DC parameter tables above. Post irradiation testing is conducted at
room temperature, +25°C, only. Testing is performed as specified in MIL-STD-883 Test Method 1019 Condition A. The ELDRS-Free part
is also tested per Test Method 1019 Conditions D.
LMH6702 Electrical Characteristics AC Parameters
(1) (2)
The following conditions apply, unless otherwise specified.
RL = 100Ω, VCC = ±5VDC, AV = +2 feedback resistor (RF) = 250Ω, gain resistor (RG) = 250Ω
Max
Unit
Subgroups
2VPP at 20MHz
-62
dBc
4
0.1MHz to 75MHz, VO < 0.5VPP
0.4
dB
4
Gain Flatness Peaking
> 75MHz, VO < 0.5VPP
2.0
dB
4
Gain Flatness Rolloff
75MHz to 125MHz, VO<0.5VPP
0.2
dB
4
2nd Harmonic Distortion
2VPP at 20MHz
-52
dBc
4
Symbol
Parameter
Conditions
HD3
3rd Harmonic Distortion
GFPL
Gain Flatness Peaking
GFPH
GFRH
HD2
(1)
(2)
Notes
Min
The algebraic convention, whereby the most negative value is a minimum and most positive is a maximum, is used in this table.
Negative cur rent shall be defined as convential current flow out of a device terminal.
These parameters are not post irradiation tested.
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LMH6702 Electrical Characteristics Drift Values Parameters (1)
The following conditions apply, unless otherwise specified.
RL = 100Ω, VCC = ±5VDC, AV = +2 feedback resistor (RF) = 250Ω, gain resistor (RG) = 250Ω
"Delta not required on B level product. Delta required for S-level product at Group B5 only, or as specified on the Internal
Processing Instruction (IPI)."
Min
Max
Unit
Subgroups
Input Bias Current Noninverting
-0.3
+0.3
μA
1
Input Bias Current Inverting
-3.0
+3.0
μA
1
Input Offset Voltage
-0.3
+0.3
mV
1
Symbol
Parameter
IBN
IBI
VIO
Notes
The algebraic convention, whereby the most negative value is a minimum and most positive is a maximum, is used in this table.
Negative cur rent shall be defined as convential current flow out of a device terminal.
1
-30
AV = -1
GAIN
AV = -2 -80
0
-130
GAIN (dB)
-1
-2
PHASE
-180
-230
-3
AV = -4
-4
-5
-6
VOUT = 2VPP
-280
PHASE (°)
(1)
Conditions
-330
AV = -10
RF = 237:
-380
RL = 100:
-7
1M
10M
100M
-430
1G
FREQUENCY (Hz)
Figure 3. Inverting Frequency Response
4
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Typical Performance Characteristics
(TA = 25°C, VS = ±5V, RL = 100Ω, RF = 237Ω; Unless Specified).
Non-Inverting Frequency Response
AV = +1
GAIN
AV = +2
0
50
-1
-3
-50
AV = +4
-4
-100
GAIN (dB)
0
PHASE (°)
-2
AV = -2 -80
-130
AV = +4
PHASE
GAIN (dB)
100
-30
AV = -1
GAIN
0
-1
Inverting Frequency Response
1
150
PHASE
-2
-180
-230
-3
AV = -4
-4
-280
PHASE (°)
1
AV = +2
-5
-6
-200
AV = -10
RF = 237:
-6
AV = +10
-380
RL = 100:
-7
1M
-250
1G
10M
100M
FREQUENCY (Hz)
-330
VOUT = 2VPP
AV = +1
RF = 237:
-7
1M
-5
-150
VO = 2VPP
RL = 100:
10M
FREQUENCY (Hz)
Figure 4.
Figure 5.
Small Signal Bandwidth
Frequency Response for Various RL’s, AV = +2
1
1
150
GAIN
0
-1
AV = +2
VO = 2VPP
100
-1
RF = 237:
50
-4
0
-5
-54
-6
-108
100M
-50
-4
-150
-6
-7
-270
10G
1G
0
200M
-1
VO = 2VPP
100
RF = 237:
VO = 2VPP
50
-50
-4
-100
50:
0.5
VOUT (V)
50:
0
PHASE (°)
-2
RL = 100:
1
PHASE
1k:
-250
1G
Step Response, 2VPP
1.5
AV = +4
GAIN
AV = +2
0
-0.5
AV = -2
-150
-6
-200
100:
-7
100M
800M
Figure 7.
150
0
600M
FREQUENCY (Hz)
Frequency Response for Various RL’s, AV = +4
-5
400M
Figure 6.
1
-3
-200
50:
FREQUENCY (Hz)
0
-100
1k:
1k:
100:
-216
RF = 232:
-9
10M
-3
-162
AV = 2
-8
0
50:
-5
VOUT = 0.5 VPP
-7
-2
PHASE (°)
-3
GAIN (dB)
PHASE
PHASE (°)
GAIN (dB)
100:
0
-2
GAIN (dB)
-430
1G
100M
200M
300M
400M
-250
500M
-1
-1.5
FREQUENCY (Hz)
0
2
4
6
8
10
12
14
TIME (ns)
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
(TA = 25°C, VS = ±5V, RL = 100Ω, RF = 237Ω; Unless Specified).
Step Response, 6VPP
Percent Settling vs. Time
1
4
AV = +2
3
RL = 100:
VOUT = 6VPP
RL = 100:
SETTLING ERROR (%)
2
VOUT (V)
1
0
-1
-2
0.1
0.01
-3
0.001
-4
0
10
20
30
40
50
1
60
10
Figure 10.
RS and Settling Time vs. CL
Input Offset for 3 Representative Units
25
20
15
50
10
RS
30
20
-2
UNIT 2
UNIT 3
-3
-3.5
RL = 1k:
0
1
-1.5
-2.5
5
AV = -1
10
-1
VOS (mV)
60
-0.5
SETTLING TIME (ns)
70
0.1% SETTLING
UNIT 1
0
80
RS (:)
0.5
0.05% SETTLING
40
1k
Figure 11.
100
90
100
TIME (ns)
TIME (ns)
10
100
0
10k
1k
-4
-40
-15
10
35
60
85
110
135
TEMPERATURE (°C)
CL (pF)
Figure 12.
Figure 13.
Inverting Input Bias for 3 Representative Units
Non-Inverting Input Bias for 3 Representative Units
10
-4
UNIT 3
8
-5
6
-7
2
0
IBN (µA)
IBI (µA)
UNIT 3
-6
4
UNIT 2
-2
UNIT 2
-8
-9
UNIT 1
-4
-10
-6
UNIT 1
-11
-8
-10
-40
6
-15
10
35
60
85
110
135
-12
-40
TEMPERATURE (°C)
10
35
60
85
TEMPERATURE (°C)
Figure 14.
Figure 15.
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-15
110
135
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Typical Performance Characteristics (continued)
(TA = 25°C, VS = ±5V, RL = 100Ω, RF = 237Ω; Unless Specified).
Noise
CMRR, PSRR, ROUT
1000
15
70
60
INVERTING CURRENT
NON-INVERTING
CURRENT
10
5
50
-5
- PSRR
40
-25
30
20
-35
RO
10
VOLTAGE
-45
1k
10k
100k
0
1k
10M
1M
10k
FREQUENCY (Hz)
100k
1M
10M
FREQUENCY (Hz)
Figure 16.
Figure 17.
Transimpedance
DG/DP (NTSC)
120
VS = ±5V
RL = 100:
200
0.02
180
160
MAG
80
140
70
120
60
100
PHASE
50
80
40
60
30
40
20
1M
10M
100M
0.004
DP
0.002
0.01
0
0
-0.002
-0.01
DG
-0.004
-0.02
20
100k
RF = 237:
RL = 150:
DG (%)
GAIN (dB)
90
NTSC
PHASE (°)
100
0.006
0.03
220
110
-55
100M
DP (°)
100
VS = ±5V
RL = 100:
1
10k
-15
CMRR
20 LOG (RO)
100
CMRR/PSRR (dB)
Hz)
NOISE CURRENT (pA/
NOISE VOLTAGE (nV/
Hz)
+ PSRR
-0.03
-1.5 -1.2 -0.9 -0.6 -0.3 0
1G
-0.006
0.3 0.6 0.9 1.2 1.5
VOUT (V)
FREQUENCY (Hz)
Figure 18.
Figure 19.
DG/DP (PAL)
0.009
0.03
PAL
RF = 237:
RL = 150:
0.006
DP
DG (%)
0.01
0.003
0
0
-0.003
-0.01
-0.02
DP (°)
0.02
DG
-0.006
-0.03
-1.5 -1.2 -0.9 -0.6 -0.3 0
-0.009
0.3 0.6 0.9 1.2 1.5
VOUT (V)
Figure 20.
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APPLICATION SECTION
FEEDBACK RESISTOR
+5V
6.8µF
AV = 1 +RF/RG = VOUT/VIN
.01µF
VIN
3
VOUT
6
CSS
0.1µF
RIN
7 CPOS
+
LMH6702
2
4 CNEG
RF
.01µF
RG
6.8µF
-5V
Figure 21. Recommended Non-Inverting Gain Circuit
+5V
6.8µF
RF
.01µF
3
25:
AV =
=
VOUT
VIN
7 CPOS
+
VOUT
6
CSS
0.1µF
RG
LMH6702
2
VIN
RG
4 CNEG
.01µF
RT
6.8µF
-5V
RF
SELECT RT TO
YIELD DESIRED
RIN = RT||RG
Figure 22. Recommended Inverting Gain Circuit
The LMH6702 achieves its excellent pulse and distortion performance by using the current feedback topology.
The loop gain for a current feedback op amp, and hence the frequency response, is predominantly set by the
feedback resistor value. The LMH6702 is optimized for use with a 237Ω feedback resistor. Using lower values
can lead to excessive ringing in the pulse response while a higher value will limit the bandwidth. Application Note
OA-13 SNOA366 discusses this in detail along with the occasions where a different RF might be advantageous.
HARMONIC DISTORTION
The LMH6702 has been optimized for exceptionally low harmonic distortion while driving very demanding
resistive or capacitive loads. Generally, when used as the input amplifier to very high speed flash ADCs, the
distortions introduced by the converter will dominate over the low LMH6702 distortions. The capacitor CSS,
shown across the supplies in Figure 21 and Figure 22, is critical to achieving the lowest 2nd harmonic distortion.
For absolute minimum distortion levels, it is also advisable to keep the supply decoupling currents (ground
connections to CPOS, and CNEG in Figure 21 and Figure 22) separate from the ground connections to sensitive
input circuitry (such as RG, RT, and RIN ground connections). Splitting the ground plane in this fashion and
separately routing the high frequency current spikes on the decoupling caps back to the power supply (similar to
"Star Connection" layout technique) ensures minimum coupling back to the input circuitry and results in best
harmonic distortion response (especially 2nd order distortion).
8
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If this lay out technique has not been observed on a particular application board, designer may actually find that
supply decoupling caps could adversely affect HD2 performance by increasing the coupling phenomenon already
mentioned. Figure 23 below shows actual HD2 data on a board where the ground plane is "shared" between the
supply decoupling capacitors and the rest of the circuit. Once these capacitors are removed, the HD2 distortion
levels reduce significantly, especially between 10MHz-20MHz, as shown in Figure 23 below:
-30
AV = +2
RL = 100:
-40
VO = 2VPP
CPOS & CNEG
INCLUDED
HD2 (dBc)
-50
-60
CPOS & CNEG
REMOVED
-70
-80
-90
1
10
FREQUENCY (MHz)
100
Figure 23. Decoupling Current Adverse Effect on a Board with Shared Ground Plane
At these extremely low distortion levels, the high frequency behavior of decoupling capacitors themselves could
be significant. In general, lower value decoupling caps tend to have higher resonance frequencies making them
more effective for higher frequency regions. A particular application board which has been laid out correctly with
ground returns "split" to minimize coupling, would benefit the most by having low value and higher value
capacitors paralleled to take advantage of the effective bandwidth of each and extend low distortion frequency
range.
CAPACITIVE LOAD DRIVE
Figure 24 shows a typical application using the LMH6702 to drive an ADC.
ADC
+
RS
LMH6702
-
CIN
Figure 24. Input Amplifier to ADC
The series resistor, RS, between the amplifier output and the ADC input is critical to achieving best system
performance. This load capacitance, if applied directly to the output pin, can quickly lead to unacceptable levels
of ringing in the pulse response. The plot of "RS and Settling Time vs. CL" in the Typical Performance
Characteristics section is an excellent starting point for selecting RS. The value derived in that plot minimizes the
step settling time into a fixed discrete capacitive load with the output driving a very light resistive load (1kΩ).
Sensitivity to capacitive loading is greatly reduced once the output is loaded more heavily. Therefore, for cases
where the output is heavily loaded, RS value may be reduced. The exact value may best be determined
experimentally for these cases.
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In applications where the LMH6702 is replacing the CLC409, care must be taken when the device is lightly
loaded and some capacitance is present at the output. Due to the much higher frequency response of the
LMH6702 compared to the CLC409, there could be increased susceptibility to low value output capacitance
(parasitic or inherent to the board layout or otherwise being part of the output load). As already mentioned, this
susceptibility is most noticeable when the LMH6702's resistive load is light. Parasitic capacitance can be
minimized by careful lay out. Addition of an output snubber R-C network will also help by increasing the high
frequency resistive loading.
Referring back to Figure 24, it must be noted that several additional constraints should be considered in driving
the capacitive input of an ADC. There is an option to increase RS, band-limiting at the ADC input for either noise
or Nyquist band-limiting purposes. Increasing RS too much, however, can induce an unacceptably large input
glitch due to switching transients coupling through from the "convert" signal. Also, CIN is oftentimes a voltage
dependent capacitance. This input impedance non-linearity will induce distortion terms that will increase as RS is
increased. Only slight adjustments up or down from the recommended RS value should therefore be attempted in
optimizing system performance.
DC ACCURACY AND NOISE
Example below shows the output offset computation equation for the non-inverting configuration using the typical
bias current and offset specifications for AV = + 2:
Output Offset : VO = (±IBN · RIN ± VIO) (1 + RF/RG) ± IBI · RF
Where RIN is the equivalent input impedance on the non-inverting input.
Example computation for AV = +2, RF = 237Ω, RIN = 25Ω:
VO = (±6μA · 25Ω ± 1mV) (1 + 237/237) ± 8μA · 237 = ±4.20mV
A good design, however, should include a worst case calculation using Min/Max numbers in the data sheet
tables, in order to ensure "worst case" operation.
Further improvement in the output offset voltage and drift is possible using the composite amplifiers described in
Application Note OA-7 SNOA365. The two input bias currents are physically unrelated in both magnitude and
polarity for the current feedback topology. It is not possible, therefore, to cancel their effects by matching the
source impedance for the two inputs (as is commonly done for matched input bias current devices).
The total output noise is computed in a similar fashion to the output offset voltage. Using the input noise voltage
and the two input noise currents, the output noise is developed through the same gain equations for each term
but combined as the square root of the sum of squared contributing elements. See Application Note OA-12
SNOA375 for a full discussion of noise calculations for current feedback amplifiers.
PRINTED CIRCUIT LAYOUT
Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations (see Application Note OA-15 SNOA367 for more information). Texas Instruments
suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and
characterization:
Device
Package
Evaluation Board Part Number
LMH6702QMLMF
SOT-23-5
CLC730216
LMH6702QMLMA
Plastic SOIC
CLC730227
10
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Table 1. Revision History
Date
Released
Revision
Section
Originator
Changes
07/12/05
A
New Corporate format Release
R. Malone
1 MDS data sheet converted in corporate data
sheet format. Added reference to QMLV
products and Drift Table. MDS MNLMH6702–X,
Rev. 1A0 will be archived.
09/28/05
B
Features, Ordering Information Table
and Notes
R. Malone
Added radiation reference to Features, Rad
NSID & SMD to Ordering Table and Note 5 to
AC & DC Electrical tables. Note to note section.
11/07/05
C
Update AC electrical's and Notes
R. Malone
Added note to AC electrical's and note section.
LMH6702QML Revision B data sheet will be
archived.
07/26/2011
D
Update Features, Ordering Information
and Footnotes
Larry M.
Added 'High Dose Rate' 300 krad(Si) and
ELDRS Free 300 krad(Si). Deleted NS Part
numbers LMH6702J-QML and LMH6702WGQML. Added NS Part number
LMH6702WGFLQMLV.Modified note.
LMH6702QML Revision C data sheet will be
archived.
10/05/2011
E
Update Ordering Information, and
Footnotes
Kirby K..
Added NS Part number LMH6702JFLQMLV
300 krad(Si) .Modified note and note. Revision
D data sheet will be archived.
03/18/2013
E
All
-
Changed layout of National Data Sheet to TI
format
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LMH6702QML
11
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-0254601VPA
ACTIVE
CDIP
NAB
8
40
TBD
Call TI
Call TI
-55 to 125
LMH6702J-QV
5962-02546
01VPA Q ACO
01VPA Q >T
5962-0254601VZA
ACTIVE
CFP
NAC
10
54
TBD
Call TI
Call TI
-55 to 125
LMH6702
WGQMLV Q
5962-02546
01VZA ACO
01VZA >T
5962F0254601VPA
ACTIVE
CDIP
NAB
8
40
TBD
Call TI
Call TI
-55 to 125
LMH6702JFQV
5962F02546
01VPA Q ACO
01VPA Q >T
5962F0254601VZA
ACTIVE
CFP
NAC
10
54
TBD
Call TI
Call TI
-55 to 125
LMH6702
WGFQMLV Q
5962F02546
01VZA ACO
01VZA >T
5962F0254602VPA
PREVIEW
CDIP
NAB
8
40
TBD
Call TI
Call TI
-55 to 125
LMH6702JFLQV
5962F02546
02VPA Q ACO
02VPA Q >T
LMH6702J-QMLV
ACTIVE
CDIP
NAB
8
40
TBD
Call TI
Call TI
-55 to 125
LMH6702J-QV
5962-02546
01VPA Q ACO
01VPA Q >T
LMH6702JFLQMLV
PREVIEW
CDIP
NAB
8
40
TBD
Call TI
Call TI
-55 to 125
LMH6702JFLQV
5962F02546
02VPA Q ACO
02VPA Q >T
LMH6702JFQMLV
ACTIVE
CDIP
NAB
8
40
TBD
Call TI
Call TI
-55 to 125
LMH6702JFQV
5962F02546
01VPA Q ACO
01VPA Q >T
LMH6702WG-QMLV
ACTIVE
CFP
NAC
10
54
TBD
Call TI
Call TI
-55 to 125
LMH6702
WGQMLV Q
5962-02546
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
15-Apr-2017
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
01VZA ACO
01VZA >T
LMH6702WGFQMLV
ACTIVE
CFP
NAC
10
54
TBD
Call TI
Call TI
-55 to 125
LMH6702
WGFQMLV Q
5962F02546
01VZA ACO
01VZA >T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
MECHANICAL DATA
NAB0008A
J08A (Rev M)
www.ti.com
MECHANICAL DATA
NAC0010A
WG10A (Rev H)
www.ti.com
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