Rohm BD9888F Silicon monolithic integrated circuit Datasheet

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STRUCTURE
Silicon Monolithic Integrated Circuit
NAME OF PRODUCT
DC-AC Inverter Control IC
TYPE
BD9888F、BD9888FV
FUNCTION
・2ch control with Push-Pull
・Lamp current and voltage sense feed back control
・Sequencing easily achieved with Soft Start Control
・Short circuit protection with Timer Latch
・Under Voltage Lock Out
・Short circuit protection with over voltage
・Mode-selectable the operating or stand-by mode by stand-by pin
・Synchronous operating the other BD9888F or BD9888FV IC’s
・BURST mode controlled by PWM and DC input
・Short circuit protection with voltage difference detection
○Absolute Maximum Ratings(Ta = 25℃)
Parameter
Supply Voltage
Operating Temperature Range
Storage Temperature Range
Symbol
VCC
Topr
Tstg
Power Dissipation
Pd
Maximum Junction Temperature
Tjmax
Limits
15
-40~+90
-55~+125
600*1(BD9888F)
850*2(BD9888FV)
+125
Unit
V
℃
℃
mW
℃
*1
Pd derate at 6.0mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
*2
Pd derate at 8.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
〇Recommended operating condition
Parameter
Supply voltage
CT oscillation frequency
BCT oscillation frequency
Symbol
VCC
fCT
fBCT
Limits
5.0~14.0
20~150
0.05~0.50
Unit
V
kHz
kHz
Status of this document
The Japanese version of this document is the official specification.
Please use the translation version of this document as a reference to expedite understanding of the official version.
If these are any uncertainty in translation version of this document, official version takes priority.
REV. A
2/4
○Electric Characteristics(Ta=25℃,VCC=7V)
Parameter
((WHOLE DEVICE)
)
Operating current
Stand-by current
((OVER VOLTAGE DETECT))
FB over voltage detect voltage
((STAND BY CONTROL))
MIN.
Limits
TYP.
MAX.
Icc1
Icc2
-
-
11.0
2
17.0
10
mA
μA
Vovf
2.20
2.40
2.60
V
Symbol
Unit
Conditions
CT=0.5V
Stand-by voltage H
VstH
1.6
-
VCC
V
System ON
Stand-by voltage L
Stand-by hysteresis
((TIMER LATCH))
Timer Latch voltage
Timer Latch current
((BURST MODE))
BOSC Max voltage
BOSC Min Voltage
BOSC constant current
BOSC frequency
((OSC BLOCK))
OSC constant current
VstL
⊿Vst
-0.3
0.08
-
0.18
0.8
0.28
V
V
System OFF
Vcp
Icp
1.9
0.5
2.0
1.0
2.1
1.5
V
μA
VburH
VburL
IBCT
fBCT
1.94
0.4
1.35/BRT
266
2.0
0.5
1.5/BRT
280
2.06
0.6
1.65/BRT
294
V
V
A
Hz
fBCT=0.2kHz
fBCT=0.2kHz
BRT=33kΩ、BCT=0.050μF
ICT
1.35/RT
1.5/RT
1.65/RT
A
OSC Max voltage
VoscH
1.8
2.0
2.2
V
OSC Min voltage
VoscL
0.3
0.5
0.7
V
fCT=60kHz
MAXDUTY
44
46.5
49
%
fCT=60kHz
MAX DUTY
Iss
1.0
2.0
3.0
μA
Visc
Vss
RSRT
0.45
2.0
-
0.50
2.2
200
0.55
2.4
400
V
V
Ω
VuvloH
VuvloL
4.100
3.900
4.300
4.100
4.500
4.300
V
V
VREG
IREG
VREF
3.038
5.0
1.225
3.100
-
1.250
3.162
-
1.275
V
mA
V
IS threshold voltage
Vis
1.225
1.250
1.275
V
VS threshold voltage
IS source current 1
IS source current 2
VS source current
((OUTPUT BLOCK)
)
NAch output voltage H
NBch output voltage H
NAch output voltage L
NBch output voltage L
NAch output sink resistance
NAch output source resistance
NBch output sink resistance
NBch output source resistance
Drive output frequency
((COMP BLOCK))
Under voltage detect
Voltage difference detect
Vvs
1.220
1.250
1.280
V
Iis1
Iis2
Ivs
-
13.0
-
-
20.0
-
1.5
27.0
1.0
μA
μA
μA
VoutNAH
VoutNBH
VoutNAL
VoutNBL
RsinkNA
RsourceNA
RsinkNB
RsourceNB
fOUT
VCC-0.3
VCC-0.3
-
-
-
-
-
-
58.5
VCC-0.1
VCC-0.1
0.1
0.1
5
8
5
8
60.0
-
-
0.3
0.3
10
16
10
16
61.5
V
V
V
V
Ω
Ω
Ω
Ω
KHz
VCOMPL
⊿VCOMP
0.620
0.40
0.640
0.45
0.660
0.5
V
V
Soft start current
IS COMP detect Voltage
SS COMP detect voltage
SRT ON resistance
((UVLO BLOCK))
Operating voltage
Shut down voltage
((REG BLOCK))
REG output voltage
REG source current
VREF voltage
((FEED BACK BLOCK))
(This product is not designed to be radiation-resistant.)
REV. A
fCT=60kHz
VREF=Open
DUTY=2.0V
DUTY=0V、IS=0.5V
Isink = 10mA
Isource = 10mA
Isink = 10mA
Isource = 10mA
RT=18kΩ、CT=395pF
|VCOMPA-VCOMPB|
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〇Package Dimensions
Device Mark
(Include BURR 10.35)
(Include BURR 18.85)
BD9888F
BD9888FV
Lot No.
SOP28 (unit:mm)
SSOP-B28 (unit:mm)
〇Block Diagram
〇Pin Description
1
Pin
Name
DUTY
2
BRT
3
BCT
4
RT
5
SRT
6
CT
Pin No.
CT
REG VREF
VCC
REG
BLOCK
STB
RT
BRT BCT
OSC
DUTY
BLOCK
UVLO
BLOCK
VCC
FB1
VS1
VCC
F/B
BLOCK①
SS
PWM
BLOCK①
CT
LOGIC
BLOCK
①
FB2
IS2
VS2
NA1
OUTPUT
BLOCK①
NB1
VCC
F/B
BLOCK②
SS
CT
PWM
BLOCK②
LOGIC
BLOCK
②
NA2
OUTPUT
BLOCK②
NB2
PGND
GND
GND
8
FB1
Error amplifier output①
9
10
11
12
13
14
IS1
VS1
FB2
IS2
VS2
VREF
15
COMPA1
16
STB
17
COMPB1
18
COMPA2
19
COMPB2
20
REG
21
SS
22
SCP
23
24
25
26
27
28
NA2
NB2
PGND
NB1
NA1
Vcc
Error amplifier input①
Error amplifier input②
Error amplifier output②
Error amplifier input③
Error amplifier input④
Reference voltage
Voltage difference or under
detect for 1ch
Stand-by switch
Voltage difference or under
detect for 1ch
Voltage difference or under
detect for 2ch
Voltage difference or under
detect for 2ch.
Internal regulator output
External capacitor from SS to
Soft Start Control
External capacitor from SCP to
Timer Latch
FET driver for 2ch
FET driver for 2ch
Ground for FET drivers
FET driver for 1ch
FET driver for 1ch
Supply voltage input
SYSTEM ON/OFF
STB
BLOCK
SS
IS1
7
Control PWM mode and BURST mode
External resistor from BRT to GND for
adjusting the BURST triangle oscillator
External capacitor from BCT to GND for
adjusting the BURST triangle oscillator
External resistor from SRT to RT for
adjusting the triangle oscillator
External resistor from SRT to RT for
adjusting the triangle oscillator
External capacitor from CT to GND for
adjusting the triangle oscillator
GROUND
DUTY
BOSC
PROTECT
BLOCK
SCP
SRT
COMP BLOCK
VOLTAGE
VOLTAGE
DIFFERENCE
DIFFERENCE
DETECT BLOCK DETECT BLOCK
②
①
COMPA1
COMPA2
COMPB1
COMPB2
REV. A
Function
voltage
voltage
voltage
voltage
GND for
GND for
4/4
〇NOTE FOR USE
1. When designing the external circuit, including adequate margins for variation between external devices
and IC. Use adequate margins for steady state and transient characteristics.
2. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is
within recommended operating range. The standard electrical characteristic values cannot be guaranteed
at other voltages in the operating ranges, however the variation will be small.
3. Mounting failures, such as misdirection or miscounts, may harm the device.
4. A strong electromagnetic field may cause the IC to malfunction.
5. The GND pin should be the location within ±0.3V compared with the PGND pin.
6. BD9888F and BD9888FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown
circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not
designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed.
7. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become
significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical
countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings.
8. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage
is switching. Make sure to leave adequate margin for this IC variation.
9. On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch.
10. By STB voltage, BD9888F and BD9888FV are changed to 2 states. Therefore, do not input STB pin voltage
between one state and the other state (0.8~1.6).
11. The pin connected a connector need to connect to the resistor for electrical surge destruction.
This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins.
A P-N junction is formed from this P layer of each pin. For example, the relation between each potential
is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can
result in mutual interference among circuits as well as operation faults and physical damage. Accordingly
you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than
the GND (P substrate) voltage to an input pin.
12.This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A
P-N junction is formed from this P layer of each pin. For example, the relation between each potential
is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can
result in mutual interference among circuits as well as operation faults and physical damage. Accordingly
you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than
the GND (P substrate) voltage to an input pin.
Transistor (NPN)
Resistance
(PinA)
(PinB)
B
E
C
C
GND
P
P+
N
P+
N
N
N
N
P substrate
GND
Parasitic diode
N
P substrate
GND
Parasitic diode
(PinB)
(PinA)
B
CC
B
EE
Parasitic diode
GND
GND
Other adjacent components
Parasitic diode
Fig-1 Simplified structure of a Bipolar IC
REV. A
Notice
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