AD AD9637BCPZ-40 1.8 v analog-to-digital converter Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
Low power: 60 mW per channel at 80 MSPS with scalable
power options
SNR = 71.5 dBFS (to Nyquist)
SFDR = 92 dBc (to Nyquist)
DNL = ±0.4 LSB (typical), INL = ±0.5 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
650 MHz full power analog bandwidth
2 V p-p differential input voltage range
1.8 V supply operation
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
PDWN
AD9637
DRVDD
12
VIN+ A
VIN– A
ADC
VIN+ B
VIN– B
ADC
VIN+ C
VIN– C
ADC
VIN+ D
VIN– D
ADC
VIN+ E
VIN– E
ADC
VIN+ F
VIN– F
ADC
VIN+ G
VIN– G
ADC
VIN+ H
VIN– H
ADC
D+ A
D– A
SERIAL
LVDS
12
D+ B
D– B
SERIAL
LVDS
12
D+ C
D– C
SERIAL
LVDS
12
D+ D
D– D
SERIAL
LVDS
12
D+ E
D– E
SERIAL
LVDS
12
D+ F
D– F
SERIAL
LVDS
12
D+ G
D– G
SERIAL
LVDS
12
APPLICATIONS
D+ H
D– H
SERIAL
LVDS
VREF
SENSE
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Optical networking
Test equipment
VCM
1.0V
REF
SELECT
SERIAL PORT
INTERFACE
DATA
RATE
MULTIPLIER
SYNC
RBIAS
AGND
CSB
SDIO/ SCLK/
DFS
DTP
CLK+ CLK–
FCO+
FCO–
DCO+
DCO–
10215-001
Data Sheet
Octal, 12-Bit, 40/80 MSPS, Serial LVDS,
1.8 V Analog-to-Digital Converter
AD9637
Figure 1.
GENERAL DESCRIPTION
The AD9637 is an octal, 12-bit, 40/80 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 80 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
Rev. A
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI).
The AD9637 is available in a RoHS-compliant, 64-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Small Footprint. Eight ADCs are contained in a small,
space-saving package.
Low Power of 60 mW/Channel at 80 MSPS with Scalable
Power Options.
Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 480 MHz and supports
double data rate (DDR) operation.
User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
Pin Compatible with the AD9257 (14-Bit Octal ADC).
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AD9637* PRODUCT PAGE QUICK LINKS
Last Content Update: 06/09/2017
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EVALUATION KITS
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REFERENCE MATERIALS
Technical Articles
DOCUMENTATION
• MS-2210: Designing Power Supplies for High Speed ADC
Application Notes
• AN-501: Aperture Uncertainty and ADC System
Performance
DESIGN RESOURCES
• AN-737: How ADIsimADC Models an ADC
• PCN-PDN Information
• AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
• Quality And Reliability
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-878: High Speed ADC SPI Control Software
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
• AD9637 Material Declaration
• Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
Visit the product page to see pricing options.
Data Sheet
• AD9637: Octal, 12-Bit, 40/80 MSPS, Serial LVDS,1.8 V
Analog-to-Digital Converter Data Sheet
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AD9637
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Power Dissipation and Power-Down Mode ........................... 22
Applications ....................................................................................... 1
Digital Outputs and Timing ..................................................... 23
General Description ......................................................................... 1
Built-In Output Test Modes .......................................................... 27
Functional Block Diagram .............................................................. 1
Output Test Modes ..................................................................... 27
Product Highlights ........................................................................... 1
Serial Port Interface (SPI) .............................................................. 28
Revision History ............................................................................... 2
Configuration Using the SPI ..................................................... 28
Specifications..................................................................................... 3
Hardware Interface..................................................................... 29
DC Specifications ......................................................................... 3
Configuration Without the SPI ................................................ 29
AC Specifications.......................................................................... 4
SPI Accessible Features .............................................................. 29
Digital Specifications ................................................................... 5
Memory Map .................................................................................. 30
Switching Specifications .............................................................. 6
Reading the Memory Map Register Table............................... 30
Timing Specifications .................................................................. 6
Memory Map Register Table ..................................................... 31
Absolute Maximum Ratings............................................................ 8
Memory Map Register Descriptions ........................................ 34
Thermal Characteristics .............................................................. 8
Applications Information .............................................................. 36
ESD Caution .................................................................................. 8
Design Guidelines ...................................................................... 36
Pin Configuration and Function Descriptions ............................. 9
Power and Ground Recommendations ................................... 36
Typical Performance Characteristics ........................................... 11
Clock Stability Considerations ................................................. 36
AD9637-80 .................................................................................. 11
Exposed Pad Thermal Heat Slug Recommendations ............ 36
AD9637-40 .................................................................................. 14
VCM ............................................................................................. 36
Equivalent Circuits ......................................................................... 17
Reference Decoupling ................................................................ 36
Theory of Operation ...................................................................... 18
SPI Port ........................................................................................ 36
Analog Input Considerations.................................................... 18
Outline Dimensions ....................................................................... 37
Voltage Reference ....................................................................... 19
Ordering Guide .......................................................................... 37
Clock Input Considerations ...................................................... 20
REVISION HISTORY
4/13—Rev. 0 to Rev. A
Added Common-Mode Range ....................................................... 3
Changes to AC Specifications Section ........................................... 4
Added Propagation Delay of 1.5 ns Min and 3.1 ns Max; Table 4 .. 6
Added CLK Divider = 8 to Figure 7, Figure 9, Figure 10, and
Figure 11 Captions.......................................................................... 11
Added CLK Divider = 8 to Figure 22, Figure 24, and Figure 25
Captions ........................................................................................... 14
Changes to Figure 36 and Figure 37 ............................................. 17
Changes to Figure 44 ...................................................................... 18
Changes to Figure 56 ...................................................................... 22
Changes to Digital Outputs and Timing Section ....................... 23
Changes to Channel Specific Registers Section .......................... 30
Changes to Register 0x21, Bit 3; Table 17 .................................... 33
Changes to Bits[6:4]—Input Clock Phase Adjust Section......... 35
Added Clock Stability Considerations Section ........................... 36
Updated Outline Dimensions ....................................................... 37
10/11—Revision 0: Initial Version
Rev. A | Page 2 of 40
Data Sheet
AD9637
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 1.
Parameter 1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation at 1.0 mA (VREF = 1 V)
Input Resistance
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUTS
Differential Input Voltage (VREF = 1 V)
Common-Mode Voltage
Common-Mode Range
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
AVDD
DRVDD
IAVDD (Eight Channels)
IDRVDD (Eight Channels, ANSI-644 Mode)
IDRVDD (Eight Channels, Reduced Range Mode)
TOTAL POWER CONSUMPTION
Total Power Dissipation (Eight Channels, ANSI-644 Mode)
Total Power Dissipation (Eight Channels, Reduced Range Mode)
Power-Down Dissipation
Standby Dissipation 2
1
2
Temp
Full
Full
Full
Full
Full
Full
Full
Min
12
−0.6
0.0
−8.0
−1.0
−0.8
−1.0
Full
Full
Full
Full
AD9637-40
Typ
Max
Guaranteed
−0.3 +0.1
0.2
0.6
−2.1 +2.0
+1.7 +5.0
±0.3 +0.8
±0.4 +1.0
Min
12
−0.7
0.0
−7.0
−1.0
−0.8
−1.2
±2
0.98
0.99
2
7.5
AD9637-80
Typ
Max
Guaranteed
−0.3 +0.1
0.2
0.6
−3.2 +1.0
+2.3 +6.0
±0.4 +0.8
±0.5 +1.2
±2
1.01
0.98
0.99
2
7.5
Unit
Bits
% FSR
% FSR
% FSR
% FSR
LSB
LSB
ppm/°C
1.01
V
mV
kΩ
25°C
0.36
0.49
LSB rms
Full
Full
Full
2
0.9
2
0.9
V p-p
V
V
kΩ
pF
0.5
Full
Full
Full
Full
Full
25°C
Full
25°C
25°C
25°C
1.3
0.5
5.2
3.5
1.7
1.7
1.3
5.2
3.5
1.8
1.8
142
51
36
1.9
1.9
151
79
347
320
1
72
414
1.7
1.7
1.8
1.8
221
58
43
1.9
1.9
234
85
V
V
mA
mA
mA
502
475
1
98
574
mW
mW
mW
mW
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Can be controlled via the SPI.
Rev. A | Page 3 of 40
AD9637
Data Sheet
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. CLK
divider = 8 used for typical characteristics at input frequency ≥ 19.7 MHz.
Table 2.
Parameter 1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 30.5 MHz
fIN = 63.5 MHz
fIN = 69.5 MHz
fIN = 123.5 MHz
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 30.5 MHz
fIN = 63.5 MHz
fIN = 69.5 MHz
fIN = 123.5 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 30.5 MHz
fIN = 63.5 MHz
fIN = 69.5 MHz
fIN = 123.5 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 30.5 MHz
fIN = 63.5 MHz
fIN = 69.5 MHz
fIN = 123.5 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 30.5 MHz
fIN = 63.5 MHz
fIN = 69.5 MHz
fIN = 123.5 MHz
WORST OTHER (EXCLUDING SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 30.5 MHz
fIN = 63.5 MHz
fIN = 69.5 MHz
fIN = 123.5 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—
AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 8 MHz, fIN2 = 10 MHz
fIN1 = 30 MHz, fIN2 = 32 MHz
Temp
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Min
70.0
AD9637-40
Typ
Max
72.0
72.0
71.9
Min
71.0
AD9637-80
Typ
Max
71.5
71.5
71.5
71.4
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
71.5
70.5
69.0
71.9
71.9
71.9
70.0
71.5
71.5
71.5
71.3
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
71.4
70.4
11.2
11.7
11.7
11.7
11.3
11.6
11.6
11.6
11.6
Bits
Bits
Bits
Bits
Bits
Bits
11.6
11.4
78
25°C
Full
25°C
25°C
25°C
25°C
96
96
96
93
92
92
92
dBc
dBc
dBc
dBc
dBc
dBc
89
88
−99
−96
−98
−78
−93
−92
−92
−92
−78
−89
−88
25°C
Full
25°C
25°C
25°C
25°C
−96
−98
−96
25°C
25°C
93
Rev. A | Page 4 of 40
78
−86
−97
−97
−97
−96
Unit
dBc
dBc
dBc
dBc
dBc
dBc
−92
dBc
dBc
dBc
dBc
dBc
dBc
85
dBc
dBc
−97
−86
Data Sheet
Parameter 1
CROSSTALK 2
Crosstalk (Overrange Condition) 3
ANALOG INPUT BANDWIDTH, FULL POWER
1
2
3
AD9637
Temp
25°C
25°C
25°C
AD9637-40
−98
−89
650
AD9637-80
−96
−89
650
Unit
dB
dB
MHz
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Crosstalk is measured at 10 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel.
Overrange condition is 3 dB above the full-scale input range.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3.
Parameter 1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage 2
Input Voltage Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SYNC, SCLK)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO) 3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D± x), ANSI-644
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D± x), LOW POWER,
REDUCED SIGNAL OPTION
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temp
Min
Full
Full
Full
25°C
25°C
0.2
AGND − 0.2
Full
Full
25°C
25°C
1.2
0
Full
Full
25°C
25°C
1.2
0
Full
Full
25°C
25°C
1.2
0
Typ
Max
Unit
3.6
AVDD + 0.2
V p-p
V
V
kΩ
pF
AVDD + 0.2
0.8
V
V
kΩ
pF
AVDD + 0.2
0.8
V
V
kΩ
pF
AVDD + 0.2
0.8
V
V
kΩ
pF
CMOS/LVDS/LVPECL
0.9
15
4
30
2
26
2
26
5
Full
Full
1.79
0.05
Full
Full
247
1.13
LVDS
350
454
1.21
1.38
Twos complement
Full
Full
150
1.13
LVDS
200
250
1.21
1.38
Twos complement
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO/DFS pins sharing the same connection.
1
2
Rev. A | Page 5 of 40
V
V
mV
V
mV
V
AD9637
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter 1, 2
CLOCK 3
Input Clock Rate
Conversion Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD) 4
DCO to Data Delay (tDATA)4
DCO to FCO Delay (tFRAME)4
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down) 5
Pipeline Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
Temp
Min
Full
Full
Full
Full
10
10
Full
Full
Full
Full
Full
Full
Full
Full
1.5
Typ
Max
Unit
640
40/80
MHz
MSPS
ns
ns
3.1
ns
ps
ps
ns
ns
ps
ps
ps
12.5/6.25
12.5/6.25
1.5
(tSAMPLE/24) − 300
(tSAMPLE/24) − 300
2.3
300
300
2.3
tFCO + (tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24)
±50
3.1
(tSAMPLE/24) + 300
(tSAMPLE/24) + 300
±200
25°C
25°C
Full
35
375
16
μs
μs
Clock
cycles
25°C
25°C
25°C
1
0.1
1
ns
ps rms
Clock
cycles
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Measured on standard FR-4 material.
3
Can be adjusted via the SPI.
4
tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. tSAMPLE = 1/fS.
5
Wake-up time is defined as the time required to return to normal operation from power-down mode.
1
2
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Description
Limit
Unit
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
See Figure 61
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to
the SCLK falling edge (not shown in Figure 61)
Time required for the SDIO pin to switch from an output to an input relative to
the SCLK rising edge (not shown in Figure 61)
0.24
0.40
ns typ
ns typ
2
2
40
2
2
10
10
10
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
10
ns min
Rev. A | Page 6 of 40
Data Sheet
AD9637
Timing Diagrams
N–1
tA
VIN± x
N
tEH
tEL
CLK–
CLK+
tCPD
DCO–
DCO+
tFRAME
tFCO
FCO–
FCO+
tPD
tDATA
MSB
N – 17
D10
N – 17
D9
N – 17
D8
N – 17
D7
N – 17
D6
N – 17
D5
N – 17
D4
N – 17
D3
N – 17
D2
N – 17
D1
N – 17
D0
N – 17
MSB
N – 16
D10
N – 16
D+ x
05967-002
D– x
Figure 2. Word-Wise DDR, 1× Frame, 12-Bit Output Mode (Default)
N–1
VIN± x
tA
N
tEL
tEH
CLK–
CLK+
tCPD
DCO–
DCO+
tFRAME
tFCO
FCO–
FCO+
tPD
tDATA
D– x
D8
N – 17
D6
D7
N – 17 N – 17
D4
D3
D2
D5
N – 17 N – 17 N – 17 N – 17
D1
D0
MSB
D8
N – 17 N – 17 N – 16 N – 16
D7
D6
N – 16 N – 16
D5
N – 16
10215-003
MSB
N – 17
D+ x
Figure 3. Word-Wise DDR, 1× Frame, 10-Bit Output Mode
CLK+
tHSYNC
10215-004
tSSYNC
SYNC
Figure 4. SYNC Input Timing Requirements
Rev. A | Page 7 of 40
AD9637
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
Electrical
AVDD to AGND
DRVDD to AGND
Digital Outputs
(D± x, DCO+, DCO−, FCO+, FCO−) to
AGND
CLK+, CLK− to AGND
VIN+ x, VIN− x to AGND
SCLK/DTP, SDIO/DFS, CSB to AGND
SYNC, PDWN to AGND
RBIAS to AGND
VREF, SENSE to AGND
Environmental
Operating Temperature Range (Ambient)
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient)
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the printed
circuit board (PCB) increases the reliability of the solder joints
and maximizes the thermal capability of the package.
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
Table 7. Thermal Resistance
Package
Type
64-Lead
LFCSP
9 mm × 9 mm
(CP-64-4)
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
Airflow
Velocity
(m/sec)
0
1.0
2.5
θJA1, 2
22.3
19.5
17.5
θJC1, 3
1.4
N/A
N/A
θJB1, 4
N/A
11.8
N/A
ΨJT1, 2
0.1
0.2
0.2
Unit
°C/W
°C/W
°C/W
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
1
2
3
−40°C to +85°C
150°C
300°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown Table 7, airflow improves heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes reduces θJA.
ESD CAUTION
Rev. A | Page 8 of 40
Data Sheet
AD9637
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VIN+ F
VIN– F
AVDD
VIN– E
VIN+ E
AVDD
SYNC
VCM
VREF
SENSE
RBIAS
VIN+ D
VIN– D
AVDD
VIN– C
VIN+ C
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AD9637
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AVDD
VIN+ B
VIN– B
AVDD
VIN– A
VIN+ A
AVDD
PDWN
CSB
SDIO/DFS
SCLK/DTP
AVDD
DNC
DRVDD
D+ A
D– A
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
10215-005
D– G
D+ G
D– F
D+ F
D– E
D+ E
DCO–
DCO+
FCO–
FCO+
D– D
D+ D
D– C
D+ C
D– B
D+ B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVDD
VIN+ G
VIN– G
AVDD
VIN– H
VIN+ H
AVDD
AVDD
CLK–
CLK+
AVDD
AVDD
DNC
DRVDD
D– H
D+ H
Figure 5. Pin Configuration, Top View
Table 8. Pin Function Descriptions
Pin No.
0, EP
1, 4, 7, 8, 11,
12, 37, 42, 45,
48, 51, 59, 62
13, 36
14, 35
2, 3
5, 6
9, 10
15, 16
17, 18
19, 20
21, 22
23, 24
25, 26
27, 28
29, 30
31, 32
33, 34
38
39
40
41
43, 44
46, 47
49, 50
Mnemonic
AGND,
Exposed Pad
AVDD
Description
Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the
analog ground for the part. This exposed pad must be connected to analog ground for proper operation.
1.8 V Analog Supply.
DNC
DRVDD
VIN+ G, VIN− G
VIN− H, VIN+ H
CLK−, CLK+
D− H, D+ H
D− G, D+ G
D− F, D+ F
D− E, D+ E
DCO−, DCO+
FCO−, FCO+
D− D, D+ D
D− C, D+ C
D− B, D+ B
D− A, D+ A
SCLK/DTP
SDIO/DFS
CSB
PDWN
VIN+ A, VIN− A
VIN− B, VIN+ B
VIN+ C, VIN− C
Do Not Connect. Do not connect to this pin.
1.8 V Digital Output Driver Supply.
ADC G Analog Input True, ADC G Analog Input Complement.
ADC H Analog Input Complement, ADC H Analog Input True.
Input Clock Complement, Input Clock True.
ADC H Digital Output Complement, ADC H Digital Output True.
ADC G Digital Output Complement, ADC G Digital Output True.
ADC F Digital Output Complement, ADC F Digital Output True.
ADC E Digital Output Complement, ADC E Digital Output True.
Data Clock Digital Output Complement, Data Clock Digital Output True.
Frame Clock Digital Output Complement, Frame Clock Digital Output True.
ADC D Digital Output Complement, ADC D Digital Output True.
ADC C Digital Output Complement, ADC C Digital Output True.
ADC B Digital Output Complement, ADC B Digital Output True.
ADC A Digital Output Complement, ADC A Digital Output True.
Serial Clock (SCLK)/Digital Test Pattern (DTP).
Serial Data Input/Output (SDIO)/Data Format Select (DFS).
Chip Select Bar.
Power-Down.
ADC A Analog Input True, ADC A Analog Input Complement.
ADC B Analog Input Complement, ADC B Analog Input True.
ADC C Analog Input True, ADC C Analog Input Complement.
Rev. A | Page 9 of 40
AD9637
Pin No.
52, 53
54
55
56
57
58
60, 61
63, 64
Data Sheet
Mnemonic
VIN− D, VIN+ D
RBIAS
SENSE
VREF
VCM
SYNC
VIN+ E, VIN− E
VIN− F, VIN+ F
Description
ADC D Analog Input Complement, ADC D Analog Input True.
Sets analog current bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
Reference Mode Selection.
Voltage Reference Input/Output.
Analog Output Voltage at Midsupply. Sets common mode of the analog inputs.
Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
ADC E Analog Input True, ADC E Analog Input Complement.
ADC F Analog Input Complement, ADC F Analog Input True.
Rev. A | Page 10 of 40
Data Sheet
AD9637
TYPICAL PERFORMANCE CHARACTERISTICS
AD9637-80
0
80MSPS
9.7MHz AT –1dBFS
SNR = 70.8dB (71.8dBFS)
SFDR = 92.7dBc
–15
AMPLITUDE (dBFS)
–30
–45
–60
–75
–90
–90
–120
8
12
16
20
24
28
32
36
FREQUENCY (MHz)
Figure 6. Single-Tone 16k FFT with fIN = 9.7 MHz, fSAMPLE = 80 MSPS
–135
4
8
12
16
20
24
28
32
36
FREQUENCY (MHz)
Figure 9. Single-Tone 16k FFT with fIN = 19.7 MHz, fSAMPLE = 80 MSPS, CLK
Divider = 8
0
0
–30
AMPLITUDE (dBFS)
–30
–15
–45
–60
–75
–90
–45
–60
–75
–90
–105
–105
–120
–120
4
8
12
16
20
24
28
32
36
FREQUENCY (MHz)
–135
10215-007
–135
Figure 7. Single-Tone 16k FFT with fIN = 63.5 MHz, fSAMPLE = 80 MSPS, CLK
Divider = 8
4
–15
–30
–30
AMPLITUDE (dBFS)
–15
–75
–90
F2 – F1
2F1 + F2
F1 + F2
20
24
28
32
36
80MSPS
123.5MHz AT –1dBFS
SNR = 69.6dB (70.6dBFS)
SFDR = 90.3dBc
–45
–60
–75
–90
2F2 – F1
2F1 – F2
2F2 + F1
–105
16
–105
–120
–120
4
8
12
16
20
24
28
32
36
FREQUENCY (MHz)
Figure 8. Two-Tone 16k FFT with fIN1 = 30 MHz and fIN2 = 32 MHz,
fSAMPLE = 80 MSPS
–135
10215-008
–135
4
8
12
16
20
24
FREQUENCY (MHz)
28
32
36
10215-010
+
12
Figure 10. Single-Tone 16k FFT with fIN = 30.5 MHz, fSAMPLE = 80 MSPS, CLK
Divider = 8
0
–60
8
FREQUENCY (MHz)
0
–45
80MSPS
30.5MHz AT –1dBFS
SNR = 70.7dB (71.7dBFS)
SFDR = 90.7dBc
10215-109
80MSPS
63.5MHz AT –1dBFS
SNR = 70.5dB (71.5dBFS)
SFDR = 93.2dBc
–15
AMPLITUDE (dBFS)
–75
–120
4
AMPLITUDE (dBFS)
–60
–105
–135
80MSPS
19.7MHz AT –1dBFS
SNR = 70.7dB (71.7dBFS)
SFDR = 90.1dBc
–45
–105
10215-006
AMPLITUDE (dBFS)
–30
–15
10215-009
0
Figure 11. Single-Tone 16k FFT with fIN = 123.5 MHz, fSAMPLE = 80 MSPS, CLK
Divider = 8
Rev. A | Page 11 of 40
AD9637
Data Sheet
0
105
100
–20
SFDR (dBc)
SNR/SFDR (dBFS/dBc)
–40
IMD3 (dBc)
–60
–80
SFDR (dBFS)
–100
95
90
85
80
75
SNR (dBFS)
IMD3 (dBFS)
–78
–66
–54
–42
–30
–18
–6
INPUT AMPLITUDE (dBFS)
70
–40
10215-011
–120
–90
Figure 12. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 30 MHz and fIN2 = 32 MHz, fSAMPLE = 80 MSPS
–15
35
60
85
Figure 15. SNR/SFDR vs. Temperature, fIN = 9.7 MHz, fSAMPLE = 80 MSPS
110
120
100
100
SFDRFS
80
SNRFS
60
SFDR
40
SFDR (dBc)
90
SNR/SFDR (dBFS/dBc)
SNR/SFDR (dBFS/dBc)
10
TEMPERATURE (°C)
10215-014
SFDR/IMD3 (dBc/dBFS)
SFDR (dBc)
SNR
80
SNR (dBFS)
70
60
50
40
30
20
20
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
0
10215-012
–60
0
200
150
INPUT FREQUENCY (MHz)
Figure 13. SNR/SFDR vs. Analog Input Level, fIN = 9.7 MHz, fSAMPLE = 80 MSPS
Figure 16. SNR/SFDR vs. fIN, fSAMPLE = 80 MSPS
105
105
100
100
SFDR
SFDR
95
SNR/SFDR (dBFS/dBc)
95
90
85
80
90
85
80
75
SNRFS
75
SNRFS
70
20
30
40
50
60
70
SAMPLE FREQUENCY (MSPS)
80
Figure 14. SNR/SFDR vs. Encode, fIN = 19.7 MHz
65
20
30
40
50
60
70
SAMPLE FREQUENCY (MSPS)
Figure 17. SNR/SFDR vs. Encode, fIN = 30.5 MHz
Rev. A | Page 12 of 40
80
10215-016
70
10215-013
SNR/SFDR (dBFS/dBc)
100
50
10215-015
10
0
–70
Data Sheet
AD9637
1.0
700,000
0.491 LSB RMS
0.8
600,000
0.6
DNL (LSB)
0.4
400,000
300,000
0.2
0
–0.2
–0.4
200,000
–0.6
100,000
–0.8
Figure 18. Input Referred Noise Histogram, fSAMPLE = 80 MSPS
2.0
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
4000
10215-018
3600
3200
2800
2400
2000
1600
1200
800
400
–2.0
0
Figure 19. INL, fIN = 9.7 MHz, fSAMPLE = 80 MSPS
Rev. A | Page 13 of 40
4000
10215-019
3500
3000
2500
2000
1500
OUTPUT CODE
Figure 20. DNL, fIN = 9.7 MHz, fSAMPLE = 80 MSPS
1.6
OUTPUT CODE
1000
0
10215-017
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
OUTPUT CODE
500
–1.0
0
INL (LSB)
NUMBER OF HITS
500,000
AD9637
Data Sheet
AD9637-40
0
–30
–45
–60
–75
–90
–60
–75
–90
–105
–105
–120
–120
4
6
8
10
14
12
18
16
FREQUENCY (MHz)
–135
2
4
6
8
10
12
14
16
10215-023
2
10215-020
–135
18
FREQUENCY (MHz)
Figure 21. Single-Tone 16k FFT with fIN = 9.7 MHz, fSAMPLE = 40 MSPS
Figure 24. Single-Tone 16k FFT with fIN = 19.7 MHz, fSAMPLE = 40 MSPS, CLK
Divider = 8
0
0
40MSPS
30.5MHz AT –1dBFS
SNR = 70.9dB (7.19dBFS)
SFDR = 95.87dBc
–15
–15
–30
AMPLITUDE (dBFS)
–30
AMPLITUDE (dBFS)
–45
–45
–60
–75
–90
–45
–60
–75
–90
–105
–105
–120
–120
2
4
6
8
10
12
14
16
18
FREQUENCY (MHz)
–135
10215-021
–135
Figure 22. Single-Tone 16k FFT with fIN = 30.5 MHz, fSAMPLE = 40 MSPS , CLK
Divider = 8
40MSPS
69.5MHz AT –1dBFS
SNR = 70.5dB (71.5dBFS)
SFDR = 88.6dBc
4
2
6
8
10
12
14
16
10215-024
AMPLITUDE (dBFS)
–30
40MSPS
19.7MHz AT –1dBFS
SNR = 70.9dB (71.9dBFS)
SFDR = 91.0dBc
–15
AMPLITUDE (dBFS)
–15
0
40MSPS
9.7MHz AT –1dBFS
SNR = 71.0dB (72.0dBFS)
SFDR = 96.9dBc
18
FREQUENCY (MHz)
Figure 25. Single-Tone 16k FFT with fIN = 69.5 MHz, fSAMPLE = 40 MSPS, CLK
Divider = 8
0
0
–15
–20
SFDR (dBc)
SFDR/IMD3 (dBc/dBFS)
AMPLITUDE (dBFS)
–30
–45
–60
–75
–90
2F1 + F2
2F2 – F1
F2 – F1
2F1 – F2
–105
+
2F2 + F1
F1 + F2
–40
IMD3 (dBc)
–60
–80
SFDR (dBFS)
–100
–120
4
6
8
10
12
14
16
18
FREQUENCY (MHz)
10215-022
2
–120
–90
–78
–66
–54
–42
–30
–18
–6
INPUT AMPLITUDE (dBFS)
Figure 23. Two-Tone 16k FFT with fIN1 = 8 MHz and fIN2 = 10 MHz,
fSAMPLE = 40 MSPS
Figure 26. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 30 MHz and fIN2 = 32 MHz, fSAMPLE = 40 MSPS
Rev. A | Page 14 of 40
10215-025
IMD3 (dBFS)
–135
Data Sheet
AD9637
110
120
100
80
SFDR (dBc)
90
SFDRFS
SNR/SFDR (dBFS/dBc)
SNR/SFDR (dBFS/dBc)
100
SNRFS
60
SFDR
40
SNR
80
SNR (dBFS)
70
60
50
40
30
20
20
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
0
10215-026
–60
0
20
40
60
Figure 27. SNR/SFDR vs. Analog Input Level, fIN = 9.7 MHz, fSAMPLE = 40 MSPS
100
120
140
160
180
200
Figure 30. SNR/SFDR vs. fIN, fSAMPLE = 40 MSPS
105
105
100
100
SFDR
SFDR
95
SNR/SFDR (dBFS/dBc)
95
90
85
80
90
85
80
75
75
SNRFS
SNRFS
70
70
25
30
35
40
SAMPLE FREQUENCY (MSPS)
65
20
10215-027
65
20
25
30
35
40
SAMPLE FREQUENCY (MSPS)
10215-030
SNR/SFDR (dBFS/dBc)
80
INPUT FREQUENCY (MHz)
10215-029
10
0
–70
Figure 31. SNR/SFDR vs. Encode, fIN = 30.5 MHz
Figure 28. SNR/SFDR vs. Encode, fIN = 19.7 MHz
1,000,000
105
0.356 LSB RMS
100
900,000
SFDR (dBc)
NUMBER OF HITS
SNR/SFDR (dBFS/dBc)
800,000
95
90
85
700,000
600,000
500,000
400,000
300,000
80
200,000
SNR (dBFS)
10
35
TEMPERATURE (°C)
60
85
0
OUTPUT CODE
Figure 29. SNR/SFDR vs. Temperature, fIN = 9.7 MHz, fSAMPLE = 40 MSPS
Rev. A | Page 15 of 40
Figure 32. Input-Referred Noise Histogram, fSAMPLE = 40 MSPS
10215-031
–15
100,000
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
70
–40
10215-028
75
Data Sheet
1.0
1.6
0.8
1.2
0.6
0.8
0.4
0.4
0.2
0
OUTPUT CODE
Figure 33. INL, fIN = 9.7 MHz, fSAMPLE = 40 MSPS
Figure 34. DNL, fIN = 9.7 MHz, fSAMPLE = 40 MSPS
Rev. A | Page 16 of 40
4000
10215-033
3600
3200
2800
2400
2000
1600
0
4000
10215-032
OUTPUT CODE
3600
3200
2800
2400
–1.0
2000
–2.0
1600
–0.8
1200
–0.6
–1.6
800
–0.4
–1.2
400
–0.8
1200
–0.2
800
0
–0.4
400
DNL (LSB)
2.0
0
INL (LSB)
AD9637
Data Sheet
AD9637
EQUIVALENT CIRCUITS
AVDD
AVDD
350Ω
SCLK/DTP, SYNC,
AND PDWN
30kΩ
10215-034
10215-038
VIN± x
Figure 39. Equivalent SCLK/DTP, SYNC, and PDWN Input Circuit
Figure 35. Equivalent Analog Input Circuit
AVDD
10Ω
CLK+
AVDD
15kΩ
0.9V
AVDD
15kΩ
10215-039
10215-035
CLK–
375Ω
RBIAS
AND VCM
10Ω
Figure 36. Equivalent Clock Input Circuit
Figure 40. Equivalent RBIAS, VCM Circuit
AVDD
AVDD
30kΩ
400Ω
SDIO/DFS
10215-036
10215-040
CSB
31kΩ
350Ω
Figure 37. Equivalent SDIO/DFS Input Circuit
Figure 41. Equivalent CSB Input Circuit
DRVDD
AVDD
V
V
D– x
D+ x
V
V
375Ω
VREF
10215-037
DRGND
10215-041
7.5kΩ
Figure 42. Equivalent VREF Circuit
Figure 38. Equivalent Digital Output Circuit
Rev. A | Page 17 of 40
AD9637
Data Sheet
THEORY OF OPERATION
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and data clocks.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9637 is a differential, switched
capacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
H
input can help reduce the peak transient current injected from
the output stage of the driving source. In addition, low Q inductors
or ferrite beads can be placed on each leg of the input to reduce
high differential capacitance at the analog inputs and, therefore,
achieve the maximum bandwidth of the ADC. Such use of low
Q inductors or ferrite beads is required when driving the converter
front end at high IF frequencies. Either a differential capacitor or
two single-ended capacitors can be placed on the inputs to provide
a matching passive network. This ultimately creates a low-pass
filter at the input to limit unwanted broadband noise. See the
AN-742 Application Note, the AN-827 Application Note, and the
Analog Dialogue article “Transformer-Coupled Front-End for
Wideband A/D Converters” (Volume 39, April 2005) for more
information. In general, the precise values depend on the
application.
Input Common Mode
The analog inputs of the AD9637 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
this bias externally. Setting the device so that VCM = AVDD/2 is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 44.
100
SFDR
90
80
SNR/SFDR (dBFS/dBc)
The AD9637 is a multistage, pipelined ADC. Each stage
provides sufficient overlap to correct for flash errors in the
preceding stage. The quantized outputs from each stage are
combined into a final 12-bit result in the digital correction
logic. The serializer transmits this converted data in a 12-bit
output. The pipelined architecture permits the first stage to
operate with a new input sample, while the remaining stages
operate with preceding samples. Sampling occurs on the rising
edge of the clock.
SNRFS
70
60
50
40
CPAR
H
VIN+ x
S
S
S
20
0.5
CSAMPLE
VIN– x
0.7
0.8
0.9
1.0
1.1
1.2
VCM (V)
H
H
1.3
Figure 44. SNR/SFDR vs. Common-Mode Voltage,
fIN = 9.7 MHz, fSAMPLE = 80 MSPS
10215-042
CPAR
0.6
10215-043
30
CSAMPLE
S
Figure 43. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 43). When the input
circuit is switched to sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle. A small resistor in series with each
An on-board, common-mode voltage reference is included in
the design and is available from the VCM pin. The VCM pin
must be decoupled to ground by a 0.1 µF capacitor, as described
in the Applications Information section.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9637, the largest input span available is 2 V p-p.
Rev. A | Page 18 of 40
Data Sheet
AD9637
Differential Input Configurations
Internal Reference Connection
There are several ways to drive the AD9637 either actively or
passively. However, optimum performance is achieved by driving
the analog input differentially. Using a differential double balun
configuration to drive the AD9637 provides excellent performance
and a flexible interface to the ADC (see Figure 46) for baseband
applications.
A comparator within the AD9637 detects the potential at the
SENSE pin and configures the reference into two possible modes,
which are summarized in Table 9. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 45), setting VREF to 1.0 V.
Table 9. Reference Configuration Summary
For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see
Figure 47), because the noise performance of most amplifiers is
not adequate to achieve the true performance of the AD9637.
Selected Mode
Fixed Internal
Reference
Fixed External
Reference
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
SENSE
Voltage (V)
AGND to 0.2
Resulting
VREF (V)
1.0 internal
AVDD
1.0 applied
to external
VREF pin
Resulting
Differential
Span (V p-p)
2.0
2.0
It is not recommended to drive the AD9637 input single-ended.
VOLTAGE REFERENCE
VIN+ x
VIN– x
A stable and accurate 1.0 V voltage reference is built into the
AD9637. VREF can be configured using either the internal 1.0 V
reference or an externally applied 1.0 V reference voltage. The
various reference modes are summarized in the sections that
follow. The VREF pin should be externally decoupled to ground
with a low ESR, 1.0 μF capacitor in parallel with a low ESR,
0.1 μF ceramic capacitor.
ADC
CORE
VREF
0.1µF
1.0µF
SELECT
LOGIC
SENSE
ADC
Figure 45. Internal Reference Configuration
0.1µF
*C1
0.1µF
R
C
33Ω
33Ω
2V p-p
C
VIN+ x
ADC
5pF
33Ω
0.1µF
R
VCM
VIN– x
ET1-1-I3
33Ω
C
*C1
200Ω
0.1µF
C
0.1µF
*C1 IS OPTIONAL
Figure 46. Differential Double Balun Input Configuration for Baseband Applications
ADT1-1WT
1:1 Z RATIO
R
*C1
VIN+ x
33Ω
2V p-p
49.9Ω
C
ADC
5pF
R
33Ω
VIN– x
VCM
*C1
0.1µF
0.1μF
*C1 IS OPTIONAL
10215-046
200Ω
Figure 47. Differential Transformer-Coupled Configuration for Baseband Applications
Rev. A | Page 19 of 40
10215-045
R
10215-044
0.5V
AD9637
Data Sheet
If the internal reference of the AD9637 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 48 shows
how the internal reference voltage is affected by loading.
0
–0.5
INTERNAL VREF = 1V
VREF ERROR (%)
The AD9637 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the utmost concern, as described in the Jitter Considerations
section.
–2.0
–2.5
–3.0
–3.5
–4.0
–5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (mA)
10215-047
–4.5
Figure 48. VREF Error vs. Load Current
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. Figure 49 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
Figure 50 and Figure 51 show two preferred methods for clocking
the AD9637 (at clock rates of up to 640 MHz prior to the internal
CLK divider). A low jitter clock source is converted from a singleended signal to a differential signal using either an RF transformer
or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 80 MHz and 640 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary winding limit clock excursions into the AD9637 to
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9637 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance. However, the diode capacitance comes
into play at frequencies above 500 MHz. Care must be taken in
choosing the appropriate signal limiting diode.
4
2
VREF ERROR (mV)
For optimum performance, clock the AD9637 sample clock inputs,
CLK+ and CLK−, with a differential signal. The signal is typically
ac-coupled into the CLK+ and CLK− pins via a transformer or
capacitors. These pins are biased internally (see Figure 36) and
require no external bias.
Clock Input Options
–1.0
–1.5
CLOCK INPUT CONSIDERATIONS
0
–2
Mini-Circuits®
ADT1-1WT, 1:1 Z
–4
0.1µF
CLOCK
INPUT
–6
XFMR
0.1µF
CLK+
100Ω
50Ω
ADC
0.1µF
CLK–
35
TEMPERATURE (°C)
60
85
SCHOTTKY
DIODES:
HSMS2822
0.1µF
10215-049
10
Figure 50. Transformer Coupled Differential Clock (Up to 200 MHz)
Figure 49. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 42). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V. It is not recommended to leave the SENSE pin floating.
0.1µF
CLOCK
INPUT
0.1µF
CLK+
50Ω
ADC
0.1µF
0.1µF
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 51. Balun Coupled Differential Clock (80 MHz to 640 MHz)
Rev. A | Page 20 of 40
10215-050
–15
10215-048
–8
–40
Data Sheet
AD9637
causes the clock divider to reset to its initial state. This
synchronization feature allows multiple parts to have their clock
dividers aligned to guarantee simultaneous input sampling.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 52. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer
excellent jitter performance.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a variety
of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 53. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.
The AD9637 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide
a wide range of clock input duty cycles without affecting the
performance of the AD9637. Noise and distortion performance
are nearly flat for a wide range of duty cycles with the DCS
turned on.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 54).
Input Clock Divider
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 µs to 5 µs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
The AD9637 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
The AD9637 clock divider can be synchronized using the external
SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
0.1µF
0.1µF
CLOCK
INPUT
CLK+
0.1µF
100Ω
ADC
0.1µF
CLK–
50kΩ
240Ω
50kΩ
10215-051
CLOCK
INPUT
AD951x
PECL DRIVER
240Ω
Figure 52. Differential PECL Sample Clock (Up to 640 MHz)
0.1µF
0.1µF
CLOCK
INPUT
CLK+
0.1µF
100Ω
ADC
0.1µF
CLK–
50kΩ
10215-052
CLOCK
INPUT
AD951x
LVDS DRIVER
50kΩ
Figure 53. Differential LVDS Sample Clock (Up to 640 MHz)
VCC
0.1µF
50Ω1
1kΩ
AD951x
CMOS DRIVER
OPTIONAL
0.1µF
100Ω
1kΩ
CLK+
ADC
CLK–
0.1µF
150Ω
RESISTOR IS OPTIONAL.
Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Rev. A | Page 21 of 40
10215-053
CLOCK
INPUT
AD9637
Data Sheet
Jitter Considerations
POWER DISSIPATION AND POWER-DOWN MODE
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(fA) due only to aperture jitter (tJ) can be calculated by
As shown in Figure 56, the power dissipated by the AD9637 is
proportional to its sample rate. The digital power dissipation
does not vary significantly because it is determined primarily by
the DRVDD supply and bias current of the LVDS output drivers.



400
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 55).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9637.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
RMS CLOCK JITTER REQUIREMENT
90
14 BITS
80
12 BITS
70
10 BITS
60
8 BITS
50
40
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
30
1
10
100
ANALOG INPUT FREQUENCY (MHz)
Figure 55. Ideal SNR vs. Input Frequency and Jitter
1000
10215-054
SNR (dB)
110
16 BITS
65MSPS
300
50MSPS
250
40MSPS
200
20MSPS
150
10
20
30
40
50
60
70
SAMPLE RATE (MSPS)
80
The AD9637 is placed in power-down mode either by the SPI
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates 1 mW. During power-down, the output drivers
are placed in a high impedance state. Asserting the PDWN pin
low returns the AD9637 to its normal operating mode. Note
that PDWN is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
120
100
350
Figure 56. Analog Core Power vs. fSAMPLE for fIN = 9.7 MHz
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
130
80MSPS
10215-055
1
 2π × f × t
J
A

ANALOG POWER (mW)
SNR Degradation = 20 log10 
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times. When
using the SPI port interface, the user can place the ADC in
power-down mode or standby mode. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details on using these features.
Rev. A | Page 22 of 40
Data Sheet
AD9637
DIGITAL OUTPUTS AND TIMING
The AD9637 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is
recommended that the trace length be less than 24 inches and
that the differential output traces be close together and at equal
lengths. An example of the FCO and data stream with proper
trace length and position is shown in Figure 57. An example of
LVDS output timing in reduced range mode is shown in Figure 58.
FCO 500mV/DIV
DCO 500mV/DIV
DATA 500mV/DIV
5ns/DIV
Figure 57. LVDS Output Timing Example in ANSI-644 Mode (Default)
FCO 500mV/DIV
DCO 500mV/DIV
DATA 500mV/DIV
5ns/DIV
10215-057
When operating in reduced range mode, the output current is
reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p
differential) across a 100 Ω termination at the receiver.
10215-056
The AD9637 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SPI. The LVDS driver current is derived on chip and sets the
output current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing (or 700 mV p-p
differential) at the receiver.
Figure 58. LVDS Output Timing Example in Reduced Range Mode
Rev. A | Page 23 of 40
AD9637
Data Sheet
Figure 59 shows an example of the LVDS output using the
ANSI-644 standard (default) data eye and a time interval error
(TIE) jitter histogram with trace lengths of less than 24 inches
on standard FR-4 material.
EYE: ALL BITS
300
ULS: 8000:448000
EYE DIAGRAM VOLTAGE (mV)
200
100
0
–100
–200
–300
ULS: 7000:448000
200
100
0
–100
–200
0.2ns
0.4ns
0.6ns
0.8ns
20ps
40ps
60ps
80ps
0ns
–0.2ns
–0.4ns
–0.8ns
0.8ns
0.6ns
0.4ns
0.2ns
0ns
–0.2ns
–0.4ns
–0.6ns
–0.8ns
–300
3.0k
1.0k
1.5k
1.0k
–60ps
10215-058
80ps
60ps
40ps
20ps
0ps
0
–20ps
0
–40ps
0.5k
–60ps
0.5k
Figure 59. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
of Less Than 24 Inches on Standard FR-4, External 100 Ω Far-End
Termination Only
Figure 60 shows an example of trace lengths exceeding 24 inches
on standard FR-4 material. Note that the TIE jitter histogram
reflects the decrease of the data eye opening as the edge deviates
from the ideal position.
It is the responsibility of the user to determine if the waveforms
meet the timing budget of the design when the trace lengths exceed
24 inches. Additional SPI options allow the user to further increase
the internal termination (increasing the current) of all eight outputs
Figure 60. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater Than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
The default format of the output data is twos complement. Table 10
shows an example of the output coding format. To change the
output data format to offset binary, see the Memory Map section.
Data from each ADC is serialized and provided on a separate
channel in DDR mode. The data rate for each serial stream is equal
to 12 bits times the sample clock rate, with a maximum of
960 Mbps (12 bits × 80 MSPS) = 960 Mbps. The lowest typical
conversion rate is 10 MSPS. See the Memory Map section for
details on enabling this feature.
Table 10. Digital Output Coding
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< −VREF − 0.5 LSB
= −VREF
=0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
10215-059
1.5k
2.0k
0ps
2.0k
2.5k
–20ps
2.5k
–40ps
TIE JITTER HISTOGRAM (Hits)
3.0k
TIE JITTER HISTOGRAM (Hits)
EYE: ALL BITS
–0.6ns
EYE DIAGRAM VOLTAGE (mV)
300
to drive longer trace lengths, which can be achieved by programming Register 0x15. Even though this option produces sharper
rise and fall times on the data edges and is less prone to bit errors,
it also increases the power dissipation of the DRVDD supply.
Offset Binary Output Mode
0000 0000 0000
0000 0000 0000
1000 0000 0000
1111 1111 1111
1111 1111 1111
Rev. A | Page 24 of 40
Twos Complement Mode
1000 0000 0000
1000 0000 0000
0000 0000 0000
0111 1111 1111
0111 1111 1111
Data Sheet
AD9637
resolution systems. When changing the resolution to a 10-bit
serial stream, the data stream is shortened. See Figure 3 for the
10-bit example.
Two output clocks are provided to assist in capturing data from
the AD9637. The DCO is used to clock the output data and is
equal to 6× the sample clock (CLK) rate for the default mode of
opera-tion. Data is clocked out of the AD9637 and must be
captured on the rising and falling edges of the DCO that supports
double data rate (DDR) capturing. The FCO is used to signal the
start of a new output byte and is equal to the sample clock rate
(see the Timing Diagrams section).
In default mode, as shown in Figure 2, the MSB is first in the data
output serial stream. This can be inverted so that the LSB is first
in the data output serial stream by using the SPI.
There are 12 digital output test pattern options available that can
be initiated through the SPI. This is a useful feature when validating
receiver capture and timing (see Table 11 for the output bit
sequencing options that are available). Some test patterns have
two serial sequential words and can be alternated in various ways,
depending on the test pattern chosen. Note that some patterns
do not adhere to the data format select option. In addition,
custom user-defined test patterns can be assigned in the 0x19,
0x1A, 0x1B, and 0x1C register addresses.
When the SPI is used, the DCO phase can be adjusted in 60°
increments relative to the data edge. This enables the user to
refine system timing margins, if required. The default DCO+
and DCO− timing, as shown in Figure 2, is 180° relative to the
output data edge.
A 10-bit serial stream can also be initiated from the SPI. This
allows the user to implement and test compatibility to lower
Table 11. Flexible Output Test Modes
PN sequence long 1
Digital Output Word 1
N/A
1000 0000 0000 (12-bit)
10 0000 0000 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 (10-bit)
N/A
Digital Output Word 2
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0101 0101 0101 (12-bit)
01 0101 0101 (10-bit)
N/A
Subject
to Data
Format
Select
N/A
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
0110
PN sequence short1
N/A
N/A
Yes
0111
One-/zero-word toggle
1000
1001
User input
1-/0-bit toggle
1010
1× sync
1011
One bit high
1111 1111 1111 (12-bit)
11 1111 1111 (10-bit)
Reg. 0x19 to Reg. 0x1A
1010 1010 1010 (12-bit)
10 1010 1010 (10-bit)
0000 0011 1111 (12-bit)
00 0001 1111 (10-bit)
1000 0000 0000 (12-bit)
0000 0000 0000 (12-bit)
00 0000 0000 (10-bit)
Reg. 0x1B to Reg. 0x1C
N/A
N/A
N/A
N/A
N/A
No
No
No
No
No
No
No
No
10 0000 0000 (10-bit)
N/A
No
1010 0011 0011 (12-bit)
10 0110 0011 (10-bit)
N/A
N/A
No
No
Output Test
Mode Bit
Sequence
0000
0001
Pattern Name
Off (default)
Midscale short
0010
+Full-scale short
0011
−Full-scale short
0100
Checkerboard
0101
1100
1
Mixed frequency
Notes
Offset binary code shown
Offset binary code shown
Offset binary code shown
Offset binary code shown
Offset binary code shown
Offset binary code shown
PN23
ITU 0.150
X23 + X18 + 1
PN9
ITU O.150
X9 + X5 + 1
Pattern associated with
the external pin
Pattern associated with
the external pin
All test mode options except PN sequence short and PN sequence long can support 10-bit to 12-bit word lengths to verify data capture to the receiver.
Rev. A | Page 25 of 40
AD9637
Data Sheet
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 − 1 or 511 bits. A description
of the PN sequence and how it is generated can be found in
Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value
is all 1s (see Table 12 for the initial values). The output is a parallel
representation of the serial PN9 sequence in MSB first format.
The first output word is the first 12 bits of the PN9 sequence in
MSB aligned format.
Table 12. PN Sequence
Sequence
PN Sequence Short
PN Sequence Long
Initial
Value
0x1FE0
0x1FFF
First Three Output Samples
(MSB First) Twos Complement
0x1DF1, 0x3CC8, 0x294E
0x1FE0, 0x2001, 0x1C00
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 − 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
seed value is all 1s (see Table 12 for the initial values) and the
AD9637 inverts the bit stream with relation to the ITU standard.
The output is a parallel representation of the serial PN23 sequence
in MSB first format. The first output word is the first 12 bits of the
PN23 sequence in MSB aligned format.
See the Memory Map section for information on how to change
these additional digital output timing features through the SPI.
SDIO/DFS Pin
For applications that do not require SPI mode operation, the
CSB pin is tied to AVDD, and the SDIO/DFS pin controls the
output data format select operation according to Table 13.
SCLK/DTP Pin
The SCLK/DTP pin is for use in applications that do not require
SPI mode operation. This pin can enable a single digital test
pattern if it and the CSB pin are both held high during device
power-up. When SCLK/DTP is tied to AVDD, the ADC channel
outputs shift out the following pattern: 1000 0000 0000. The
FCO and DCO function normally while all channels shift out the
repeatable test pattern. This pattern allows the user to perform
timing alignment adjustments among the FCO, DCO, and output
data. This pin has an internal 30 kΩ resistor to GND. It can be
left unconnected for normal operation.
Table 14. Digital Test Pattern Pin Settings
Selected DTP
Normal Operation
DTP
Resulting D± x
Normal operation
1000 0000 0000
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map section
for information about the options available.
CSB Pin
The CSB pin should be tied to AVDD for applications that do
not require SPI mode operation. Tying CSB high causes all
SCLK and SDIO information to be ignored.
RBIAS Pin
To set the internal core bias current of the ADC, place
a 10.0 kΩ, 1% tolerance resistor to ground at the RBIAS pin.
Table 13. Output Data Format Select Pin Settings
DFS Pin Voltage
AVDD
GND (Default)
DTP Voltage
No connect
AVDD
Output Mode
Twos complement
Offset binary
Rev. A | Page 26 of 40
Data Sheet
AD9637
BUILT-IN OUTPUT TEST MODES
The AD9637 includes a built-in test feature designed to enable
verification of the integrity of each data output channel, as well
as to facilitate board level debugging. Various output test options
are provided to place predictable values on the outputs of the
AD9637.
OUTPUT TEST MODES
The output test options are described in Table 17 at Address 0x0D.
When an output test mode is enabled, the analog section of the
ADC is disconnected from the digital back-end blocks and the
test pattern is run through the output formatting block. Some of
the test patterns are subject to output formatting, and some are
not. The PN generators from the PN sequence tests can be reset
by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be
performed with or without an analog signal (if present, the
analog signal is ignored), but they do require an encode clock.
For more information, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Rev. A | Page 27 of 40
AD9637
Data Sheet
SERIAL PORT INTERFACE (SPI)
The AD9637 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
gives the user added flexibility and customization, depending on
the application. Addresses are accessed via the serial port and
can be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 61
and Table 5.
CONFIGURATION USING THE SPI
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in high impedance mode. This mode turns
on any SPI pin secondary functions.
Three pins define the SPI of this ADC: the SCLK/DTP pin, the
SDIO/DFS pin, and the CSB pin (see Table 15). The SCLK
(a serial clock) is used to synchronize the read and write data
presented from and to the ADC. The SDIO (serial data input/
output) is a dual-purpose pin that allows data to be sent to and
read from the internal ADC memory map registers. The CSB
(chip select bar) is an active low control that enables or disables
the read and write cycles.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. The first bit of the first byte in
a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. If the instruction is a
readback operation, performing a readback causes the serial
data input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.
Table 15. Serial Port Interface Pins
SDIO
CSB
Function
Serial clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip select bar. An active low control that gates the read
and write cycles.
tHIGH
tDS
tS
tDH
CSB
All data is composed of 8-bit words. Data can be sent in MSB
first mode or in LSB first mode. MSB first is the default on
power-up and can be changed via the SPI port configuration
register. For more information about this and other features,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
tCLK
tH
tLOW
SCLK DON’T CARE
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
Figure 61. Serial Port Interface Timing Diagram
Rev. A | Page 28 of 40
D4
D3
D2
D1
D0
DON’T CARE
10215-060
Pin
SCLK
Data Sheet
AD9637
HARDWARE INTERFACE
The pins described in Table 15 comprise the physical interface
between the user programming device and the serial port of the
AD9637. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9637 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to DRVDD or ground
during device power-on, they are associated with a specific
function. Table 13 and Table 14 describe the strappable
functions supported on the AD9637.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DFS pin, the SCLK/DTP pin, and the PDWN pin
serve as standalone CMOS-compatible control pins. When the
device is powered up, it is assumed that the user intends to use the
pins as static control lines for the output data format, output
digital test pattern, and power-down feature control. In this
mode, CSB should be connected to AVDD, which disables the
serial port interface.
When the device is in SPI mode, the PDWN pin (if enabled)
remains active. For SPI control of power-down, the PDWN pin
should be set to its default state.
SPI ACCESSIBLE FEATURES
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9637 part-specific features are described in detail
in the Memory Map Register Descriptions section following
Table 17, the external memory map register table.
Table 16. Features Accessible Using the SPI
Feature Name
Mode
Clock
Offset
Test I/O
Output Mode
Output Phase
ADC Resolution
and Speed Grade
Rev. A | Page 29 of 40
Description
Allows the user to set either power-down
mode or standby mode
Allows the user to access the DCS, set the
clock divider, set the clock divider phase,
and enable the sync
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have
known data on output bits
Allows the user to set the output mode
Allows the user to set the output clock polarity
Scalable power consumption options based
on resolution and speed grade selection
AD9637
Data Sheet
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Default Values
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into three sections: the chip
configuration registers (Address 0x00 to Address 0x02); the
device index and transfer registers (Address 0x05 and Address
0xFF) and the global ADC functions registers, including setup,
control, and test (Address 0x08 to Address 0x109).
After the AD9637 is reset, critical registers are loaded with
default values. The default values for the registers are given in
Table 17, the memory map register table.
The memory map register table (see Table 17) lists the default
hexadecimal value for each hexadecimal address shown. The
column with the heading Bit 7 (MSB) is the start of the default
hexadecimal value given. For example, Address 0x05, the device
index register, has a hexadecimal default value of 0x3F. This
means that in Address 0x05, Bits[7:6] = 0, and the remaining
Bits[5:0] = 1. This setting is the default channel index setting.
The default value results in both ADC channels receiving the
next write command. For more information on this function
and others, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI. This application note details the
functions controlled by Register 0x00 to Register 0xFF. The
remaining registers are documented in the Memory Map
Register Descriptions section.
Open Locations
All address and bit locations that are not included in Table 17
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x05). If the entire address location
is open or not listed in Table 17 (for example, Address 0x13) this
address location should not be written.
Logic Levels
An explanation of logic level terminology follows:
•
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Channel-Specific Registers
Some channel setup functions can be programmed differently
for each channel. In these cases, channel address locations are
internally duplicated for each channel. These registers and bits
are designated in Table 17 as local. These local registers and bits
can be accessed by setting the appropriate data channel bits (A
through H) and the clock channel DCO/FCO bits (Bits[5:4]) in
Register 0x04 and Register 0x05. If all the bits are set, the subsequent write affects the registers of all channels and the DCO/
FCO clock channels. In a read cycle, only one of the channels
should be set to read one of the four local registers. If all the bits
are set during a SPI read cycle, the part returns the value for
Channel A. Registers and bits designated as global in Table 17
affect the entire part or the channel features for which independent settings are not allowed between channels. The settings
in Register 0x04 and Register 0x05 do not affect the global
registers and bits.
Rev. A | Page 30 of 40
Data Sheet
AD9637
MEMORY MAP REGISTER TABLE
The AD9637 uses a 3-wire interface and 16-bit addressing and,
therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3
and Bit 4 are set to 1. When Register 0x00, Bit 5 is set high, the
SPI enters a soft reset, where all of the user registers revert to
their default values and Bit 2 is automatically cleared.
Table 17. Memory Map Register Table
Reg.
Addr. Parameter
(Hex)
Name
Bit 7 (MSB)
Chip Configuration Registers
0x00
SPI port
0 = SDO
configuration
active
0x01
Chip ID (global)
0x02
Chip grade
(global)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
LSB first
Soft reset
1=
16-bit
address
1=
16-bit
address
Soft reset
LSB first
0 = SDO
active
8-bit chip ID, Bits[7:0]
AD9637 0x93 = octal 12-bit 40 MSPS/80 MSPS serial LVDS
Open
Speed grade ID, Bits[6:4]
001 = 40 MSPS
100 = 80 MSPS
Default
Value
(Hex)
0x18
Read
only
0x93
Open
Open
Open
Open
Read
only
Device Index and Transfer Registers
0x04
Device Index 2
Open
Open
Open
Open
Data
Channel H
Data
Channel G
Data
Channel F
Data
Channel E
0xF
0x05
Device Index 1
Open
Open
Clock
Channel
DCO
Clock
Channel
FCO
Data
Channel D
Data
Channel C
Data
Channel B
Data
Channel A
0x3F
0xFF
Transfer
Open
Open
Open
Open
Open
Open
Open
Initiate
override
0x00
Global ADC Functions
0x08
Power modes
(global)
Open
Open
Open
Open
0x09
Open
Open
External
powerdown
pin
function
0 = full
powerdown
1=
standby
Open
Open
Open
Clock (global)
Rev. A | Page 31 of 40
Open
Open
Internal power-down
mode
00 = chip run
01 = full power-down
10 = standby
11 = reset
Open
Duty cycle
stabilizer
0 = off
1 = on
Comments
The nibbles
are mirrored
so that LSB or
MSB first
mode registers
correctly. The
default for
the ADCs is
16-bit mode.
Unique chip ID
that is used to
differentiate
devices; read
only.
Unique speed
grade ID that
is used to
differentiate
graded
devices; read
only.
Bits are set to
determine
which device
on chip
receives the
next write
command.
The default is
all devices on
chip.
Bits are set
to determine
which device
on chip
receives the
next write
command.
The default is
all devices on
chip.
Set
resolution/
sample rate
override.
0x00
Determines
various
generic
modes of chip
operation.
0x01
Turns duty
cycle
stabilizer on
or off.
AD9637
Reg.
Addr.
(Hex)
0x0B
Parameter
Name
Clock divide
(global)
0x0C
Enhancement
control
0x0D
Test mode (local
except for PN
sequence resets)
0x10
0x14
Offset adjust
(local)
Output mode
0x15
Output adjust
Data Sheet
Bit 7 (MSB)
Open
Bit 1
Bit 0 (LSB)
Clock divide ratio, Bits[2:0]
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Open
Open
Open
Open
Open
Chop
Open
Open
mode
0 = off
1 = on
User input test mode
Reset PN Reset
Output test mode, Bits[3:0] (local)
long gen PN
00 = single
0000 = off (default)
short
01 = alternate
0001 = midscale short
gen
10 = single once
0010 = positive FS
11 = alternate once
0011 = negative FS
(affects user input test
0100 = alternating checkerboard
mode only,
0101 = PN 23 sequence
Bits[3:0] = 1000)
0110 = PN 9 sequence
0111 = one/zero word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
8-bit device offset adjustment, Bits[7:0] (local)
Offset adjust in LSBs from +127 to −128 (twos complement format)
Open
LVDS-ANSI/
Open
Open
Open
Output
Open
Output
LVDS-IEEE
format
invert
option
0 = offset
(local)
0 = LVDSbinary
ANSI
1 = twos
1 = LVDScomplement
IEEE reduced
range link
(global)
(global)
see Table 18
Open
Open
Output driver
Open
Open
Open
Output
drive
termination, Bits[1:0]
0 = 1× drive
00 = none
1 = 2× drive
01 = 200 Ω
0x16
Output phase
Open
0x18
VREF
Open
Bit 6
Open
Bit 5
Open
Bit 4
Open
Bit 3
Open
10 = 100 Ω
11 = 100 Ω
Input clock phase adjust, Bits[6:4]
(value is number of input clock
cycles of phase delay)
(see Table 19)
Open
Open
Open
Bit 2
Output clock phase adjust, Bits[3:0]
(setting = 0000 through 1011)
(see Table 20)
Open
Rev. A | Page 32 of 40
Internal VREF adjustment
digital scheme, Bits[2:0]
000 = 1.0 V p-p
001 = 1.14 V p-p
010 = 1.33 V p-p
011 = 1.6 V p-p
100 = 2.0 V p-p
Default
Value
(Hex)
0x00
Comments
The divide
ratio is the
value plus 1.
0x00
Enables/
disables chop
mode.
0x00
When set,
the test data
is placed on
the output
pins in place
of normal
data.
0x00
Device offset
trim.
Configures
the outputs
and the
format of the
data.
0x01
0x00
Determines
LVDS or other
output
properties.
0x03
On devices
that use
global clock
divide,
determines
which phase
of the divider
output is
used to
supply the
output clock.
Internal
latching is
unaffected.
Selects
and/or
adjusts the
VREF.
0x04
Data Sheet
Reg.
Addr.
(Hex)
0x19
0x1A
0x1B
0x1C
Parameter
Name
USER_PATT1_LSB
(global)
USER_PATT1_MS
B (global)
USER_PATT2_LSB
(global)
USER_PATT2_MS
B (global)
AD9637
Bit 7 (MSB)
B7
Bit 6
B6
Bit 5
B5
Bit 4
B4
Bit 3
B3
Bit 2
B2
Bit 1
B1
Bit 0 (LSB)
B0
Default
Value
(Hex)
0x00
B15
B14
B13
B12
B11
B10
B9
B8
0x00
B7
B6
B5
B4
B3
B2
B1
B0
0x00
B15
B14
B13
B12
B11
B10
B9
B8
0x00
PLL low
encode
rate
mode
Open
Open
Open
0x21
Serial control
(global)
LVDS
output LSB
first
Word-wise DDR 1-lane, Bits[6:4]
100 = DDR 1-lane
0x22
Serial channel
status (local)
Open
Open
0x100
Resolution/
sample rate
override
Open
Resolution/
sample rate
override
enable
0x101
User I/O Control 2
Open
Open
Open
Open
Open
Open
Open
0x102
User I/O Control 3
Open
Open
Open
Open
Open
Open
0x109
Sync
Open
Open
Open
Open
VCM
powerdown
Open
SDIO
pull-down
Open
Open
Sync next
only
Enable
sync
Open
Open
Resolution
10 = 12 bits
11 = 10 bits
Open
Rev. A | Page 33 of 40
Serial output number
of bits
10 = 12 bits
11 = 10 bits
Channel
output
reset
Channel
powerdown
Sample rate
000 = 20 MSPS
001 = 40 MSPS
010 = 50 MSPS
011 = 65 MSPS
100 = 80 MSPS
0x42
0x00
0x00
0x00
0x00
0x00
Comments
User Defined
Pattern 1 LSB.
User Defined
Pattern 1
MSB.
User Defined
Pattern 2 LSB.
User Defined
Pattern 2
MSB.
Serial stream
control.
Default
causes MSB
first and the
native bit
stream.
Used to
power down
individual
sections of
a converter.
Resolution/
sample rate
override
(requires
transfer bit,
0xFF).
Disables SDIO
pull-down.
VCM control.
AD9637
Data Sheet
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Device Index (Register 0x04 and Register 0x05)
There are certain features in the map that can be set independently
for each channel, whereas other features apply globally to all
channels (depending on context), regardless of which are selected.
The first four bits in Register 0x04 and Register 0x05 can be
used to select which individual data channels are affected. The
output clock channels can be selected in Register 0x05, as well.
A smaller subset of the independent feature list can be applied
to those devices.
Transfer (Register 0xFF)
All registers except Register 0x100 are updated the moment
they are written. Setting Bit 0 of this transfer register high
initializes the settings in the ADC sample rate override register
(Address 0x100).
Output Mode (Register 0x14)
Bit 7—Open
Bit 6—LVDS-ANSI/LVDS-IEEE Option
Setting this bit chooses the LVDS-IEEE (reduced range) option.
The default setting is LVDS-ANSI. As described in Table 18,
when LVDS-ANSI or LVDS-IEEE reduced range link is selected,
the user can select the driver termination. The driver current
is automatically selected to give the proper output swing.
Table 18. LVDS-ANSI/LVDS-IEEE Options
Output
Mode,
Bit[6]
0
1
Output
Mode
LVDS-ANSI
Output Driver
Termination
User selectable
LVDS-IEEE
reduced
range link
User selectable
Output Driver
Current
Automatically
selected to give
proper swing
Automatically
selected to give
proper swing
Power Modes (Register 0x08)
Bits[7:6]—Open
Bits[5:3]—Open
Bit 5—External Power-Down Pin Function
Setting this bit inverts the output bit stream.
If set, the external PDWN pin initiates standby mode. If cleared,
the external PDWN pin initiates power-down mode.
Bit 1—Open
Bits[4:2]—Open
By default, this bit is set to send the data output in twos
complement format. Resetting this bit changes the output mode
to offset binary.
Bit 2—Output Invert
Bits[1:0]—Internal Power-Down Mode
In normal operation (Bits[1:0] = 00), all ADC channels are active.
In power-down mode (Bits[1:0] = 01), the digital data path clocks
are disabled while the digital data path is reset. Outputs are
disabled.
Bit 0—Output Format
Output Adjust (Register 0x15)
Bits[7:6]—Open
Bits[5:4]—Output Driver Termination
In standby mode (Bits[1:0] = 10), the digital data path clocks
and the outputs are disabled.
These bits allow the user to select the internal termination
resistor.
During a digital reset (Bits[1:0] = 11), all the digital data path
clocks and the outputs (where applicable) on the chip are reset,
except the SPI port. Note that the SPI is always left under
control of the user, that is, it is never automatically disabled or
in reset (except by power-on reset).
Bits[3:1]—Open
Enhancement Control (Register 0x0C)
Bits[7:3]—Open
Bit 2—Chop Mode
For applications that are sensitive to offset voltages and other
low frequency noise, such as homodyne or direct conversion
receivers, chopping in the first stage of the AD9637 is a feature
that can be enabled by setting Bit 2. In the frequency domain,
chopping translates offsets and other low frequency noise to
fCLK/2, where they can be filtered.
Bit 0—Output Drive
Bit 0 of the output adjust register controls the drive strength on
the LVDS driver of the FCO and DCO outputs only. The default
values set the drive to 1×. The drive can be increased to 2× by
setting the appropriate channel bit in Register 0x05 and then
setting Bit 0. These features cannot be used with the output driver
termination select. The termination selection takes precedence
over the 2× driver strength on FCO and DCO when both the
output driver termination and output drive are selected.
Bits[1:0]—Open
Rev. A | Page 34 of 40
Data Sheet
AD9637
Output Phase (Register 0x16)
Bit 7—Open
Resolution/Sample Rate Override (Register 0x100)
Bits[6:4]—Input Clock Phase Adjust
When the clock divider (Register 0x0B) is used, the applied
clock is at a higher frequency than the internal sampling
clock. Bits[6:4] determine at which phase of the external
clock sampling occurs. This is only applicable when the
clock divider is used. Selecting Bits[6:4] greater than
Register 0x0B Bits[2:0] is prohibited.
Table 19. Input Clock Phase Adjust Options
Input Clock Phase
Adjust, Bits[6:4]
000 (Default)
001
010
011
100
101
110
111
Number of Input Clock Cycles of
Phase Delay
0
1
2
3
4
5
6
7
This register is designed to allow the user to downgrade the device.
Any attempt to upgrade the default speed grade results in a chip
power-down. Settings in this register are not initialized until Bit 0
of the transfer register (Register 0xFF) is written high.
User I/O Control 2 (Register 0x101)
Bits[7:1]—Open
Bit 0—SDIO Pull-Down
Bit 0 can be set to disable the internal 30 kΩ pull-down on the
SDIO pin, which can be used to limit loading when many
devices are connected to the SPI bus.
User I/O Control 3 (Register 0x102)
Bits[7:4]—Open
Bit 3—VCM Power-Down
Bit 3 can be set high to power down the internal VCM generator.
This feature is used when applying an external reference.
Bits[2:0]—Open
Bits[3:0]—Output Clock Phase Adjust
Table 20. Output Clock Phase Adjust Options
Output Clock (DCO),
Phase Adjust, Bits[3:0]
0000
0001
0010
0011 (Default)
0100
0101
0110
0111
1000
1001
1010
1011
DCO Phase Adjustment
(Degrees Relative to D± x Edge)
0
60
120
180
240
300
360
420
480
540
600
660
Rev. A | Page 35 of 40
AD9637
Data Sheet
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting the design and layout of the AD9637 as a system,
it is recommended that the designer become familiar with these
guidelines, which describes the special circuit connections and
layout requirements that are needed for certain pins.
POWER AND GROUND RECOMMENDATIONS
When connecting power to the AD9637, it is recommended
that two separate 1.8 V supplies be used. Use one supply for
analog (AVDD); use a separate supply for the digital outputs
(DRVDD). For both AVDD and DRVDD, several different
decoupling capacitors should be used to cover both high and
low frequencies. Place these capacitors close to the point of
entry at the PCB level and close to the pins of the part, with
minimal trace length.
A single PCB ground plane should be sufficient when using the
AD9637. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
CLOCK STABILITY CONSIDERATIONS
When powered on, the AD9637 goes into an initialization phase
where an internal state machine sets up the biases and the
registers for proper operation. During the initialization process,
the AD9637 needs a stable clock. If the ADC clock source is not
present or not stable during ADC power-up, it will disrupt the
state machine and cause the ADC to start up in an unknown
state. To correct this, an initialization sequence needs to be
re-invoked after the ADC clock is stable. This is done by issuing
a digital reset via Register 0x08. In the default configuration
(internal VREF, ac-coupled input) where VREF and VCM are
supplied by the ADC itself, a stable clock during power-up is
sufficient. In the case where VREF and/or VCM are supplied by
an external source, these too should be stable at power up;
otherwise, a subsequent digital reset via Register 0x08 will
be needed. The pseudo-code sequence for a digital reset is
as follows:
SPI_Write (0x08, 0x03); # Digital Reset
EXPOSED PAD THERMAL HEAT SLUG
RECOMMENDATIONS
It is required that the exposed pad on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9637. An
exposed continuous copper plane on the PCB should mate to
the AD9637 exposed pad, Pin 0. The copper plane should have
several vias to achieve the lowest possible resistive thermal path
for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
guarantees only one tie point. For detailed information on
packaging and the PCB layout of chip scale packages, see the
AN-772 Application Note, A Design and Manufacturing Guide
for the Lead Frame Chip Scale Package (LFCSP), at
www.analog.com.
VCM
The VCM pin should be decoupled to ground with a 0.1 μF
capacitor.
REFERENCE DECOUPLING
The VREF pin should be externally decoupled to ground with
a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF
ceramic capacitor.
SPI PORT
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9637 to keep these signals from transitioning at the converter inputs during critical sampling periods.
SPI_Write (0x08, 0x00); # Normal Operation
Rev. A | Page 36 of 40
Data Sheet
AD9637
OUTLINE DIMENSIONS
9.10
9.00 SQ
8.90
0.30
0.25
0.18
0.60 MAX
0.60
MAX
64 1
49
48
PIN 1
INDICATOR
PIN 1
INDICATOR
8.85
8.75 SQ
8.65
0.50
BSC
0.50
0.40
0.30
33
32
0.25 MIN
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
06-12-2012-C
0.05 MAX
0.02 NOM
SEATING
PLANE
16
7.50 REF
0.80 MAX
0.65 TYP
12° MAX
17
BOTTOM VIEW
TOP VIEW
1.00
0.85
0.80
6.35
6.20 SQ
6.05
EXPOSED
PAD
Figure 62. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9637BCPZ-40
AD9637BCPZRL7-40
AD9637BCPZ-80
AD9637BCPZRL7-80
AD9637-80EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 37 of 40
Package Option
CP-64-4
CP-64-4
CP-64-4
CP-64-4
AD9637
Data Sheet
NOTES
Rev. A | Page 38 of 40
Data Sheet
AD9637
NOTES
Rev. A | Page 39 of 40
AD9637
Data Sheet
NOTES
©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10215-0-4/13(A)
Rev. A | Page 40 of 40
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