GMT G2995P1U Ddr termination regulator Datasheet

G2995
Global Mixed-mode Technology Inc.
DDR Termination Regulator
Features
General Description
„
The G2995 is a linear regulator designed to meet the
JEDEC SSTL-2 and SSTL-3 (Series Stub Termination
Logic) specifications for termination of DDR-SDRAM.
It contains a high-speed operational amplifier that provides excellent response to the load transients. This
device can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for
DDR-SDRAM termination. With an independent VSENSE
pin, the G2995 can provide superior load regulation.
The G2995 provides a VREF output as the reference for
the applications of the chipset and DIMMs.
„
„
„
„
„
„
„
„
Operation Supply Voltage: 1.6V to 5.5V
Low Supply Current: 280µA @ 2.5V
Low Output Offset
Source and Sink Current
Low External Component Count
No Inductor Required
No external Resistors Required
Thermal Shutdown Protection
SOP-8L with Power-Pad package
Applications
„
DDR-SDRAM Termination Voltage
DDR-I / DDR-II Termination Voltage
„ SSTL-2
„ SSTL-3
The G2995 can easily provide the accurate VTT and
VREF voltages without external resistors that PCB areas can be reduced. The quiescent current is as low
as 280µA @ 2.5V. So the power consumption can
meet the low power consumption applications.
„
Ordering Information
ORDER
NUMBER
ORDER NUMBER
(Pb free)
MARKING
TEMP.
RANGE
PACKAGE
G2995P1U
G2995F1U
G2995P1Uf
G2995F1Uf
G2995
G2995
-40°C to 85°C
-40°C to 85°C
SOP-8
SOP-8 (FD)
Note: P1:SOP-8
U: Tape & Reel
F1:SOP-8(FD)
(FD): Thermal Pad
Pin Configuration
Typical Application Circuit
G2995
NC
8
1
GND
2
7
VSENSE
3
6
VREF
4
5
VTT
PVIN
VDDQ
VDDQ=2.5V
Thermal
Pad
VDD=2.5V
AVIN
AVIN
VREF
47µF
VDDQ
VREF=1.25V
0.01µF
VSENSE
PVIN
+
+
VTT
GND
VTT=1.25V
+
220µF
SOP-8
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Absolute Maximum Ratings
Recommend Operation Range
(1)
Supply Voltage
PVIN, AVIN, VDDQ to GND……………-0.3V to +6V
Operating Ambient Temperature Range
TA…….…………………………….……...-40°C to +125°C
Maximum Junction Temperature, TJ…..……….….150°C
Storage Temperature Range, TSTG….….-65°C to+150°C
Reflow Temperature (Soldering, 10 sec)…………260°C
Electrostatic Discharge, VESD
Human body mode..………………………………2000V(2)
SOP-8L Thermal Resistance (θJA)…….………130°C/W
SOP-8L (FD) Thermal Resistance (θJA)……...50°C/W(3)
SOP-8L (FD) Thermal Resistance (θJA)………41°C/W(4)
SOP-8L (FD) Thermal Resistance (θJc)……….12°C/W
Operating Ambient Temperature Range
TA…….…………………………….……….-40°C to +85°C
AVIN to GND………………………..………1.6V to +5.5V
PVIN, VDDQ to GND.………………………1.6V to AVIN
Note:
(1)
:Absolute maximum rating indicates limits beyond which damage to the device may occurs.
(2)
: Human body model : C = 100pF, R = 1500Ω, 3 positive pulses plus 3 negative pulses
(3)
: The package is placed on a 2-layer PCB (2oz/2oz) with 6 vias.
(4)
: The package is placed on a 2-layer PCB (2oz/2oz) with 6 vias. The airflow is used.
Electrical Characteristics
Specifications with standard typeface are for TA=25°C. Unless otherwise specified, AVIN=PVIN=2.5V, VDDQ=2.5V
PARAMETER
SYMBOL
VREF Voltage
VREF
VREF Output impendence
ZREF
VTT Output voltage
VTT Output Voltage Offset (VREF- VTT)
Quiescent Current
VDDQ input Impedence
VSENSE input current
Thermal Shutdown
Thermal Shutdown Hystersis
VTT
VosVtt
IQ
CONDITION
VDDQ=2.3V
VDDQ=2.5V
VDDQ=2.7V
IREF =-30µA to + 30µA
IOUT=0A
VDDQ=2.3V
VDDQ=2.5V
VDDQ=2.7V
IOUT=±1.5A
VDDQ=2.3V
VDDQ=2.5V
VDDQ=2.7V
IOUT=0A
IOUT=-1.5A
IOUT=+1.5A
IOUT=0A
ZVDDQ
ISENSE
TSD
THsy
MIN
TYP
MAX
UNIT
1.11
1.21
1.31
---
1.145
1.245
1.345
1.15
1.19
1.29
1.39
---
V
V
V
kΩ
1.11
1.21
1.31
1.152
1.252
1.352
1.19
1.29
1.39
V
V
V
1.11
1.21
1.31
-40
-40
-40
-----------
1.152
1.252
1.352
0
0
0
280
100
20
150
25
1.19
1.29
1.39
40
40
40
500
---------
V
V
V
mV
mV
mV
µA
KΩ
nA
°C
°C
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Typical Performance Characteristics
AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1µF, CPVIN=47µF, CVREF=0.01µF, CVTT=220µF, TA=25°C, unless otherwise noted.
VREF vs IREF
1.3
250
1.28
230
1.26
VREF(V)
IQ(µA)
IQ vs AVIN
270
210
1.24
190
1.22
170
1.2
150
1.18
2
2.5
3
3.5
4
4.5
5
5.5
-30
-20
-10
0
10
20
30
IREF(µA)
AVIN(V)
VTT vs IOUT Temperature
VREF vs VDDQ
3
1.252
2.5
1.248
VTT(V)
VREF(V)
2
1.5
1.244
1.24
0°C
1
25°C
1.236
0.5
85°C
1.232
-100
0
2
2.5
3
3.5
4
4.5
5
5.5
VDDQ(V)
-75
-50
-25
0
25
50
75
100
IOUT(mA)
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G2995
Global Mixed-mode Technology Inc.
Typical Performance Characteristics
AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1µF, CPVIN=47µF, CVREF=0.01µF, CVTT=220µF, TA=25°C, unless otherwise noted.
IQ vs AVIN Temperature
VTT vs VDDQ
3
270
2.5
250
2
230
25°C
IQ(µA)
VTT(V)
85°C
1.5
1
190
0.5
170
0
0°C
210
150
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
VDDQ(V)
4
4.5
5
5.5
AVIN(V)
Maximum Sourcing Current vs AVIN
(VDDQ=2.5V, PVIN=1.8V)
Maximum Sourcing Current vs AVIN
(VDDQ=2.5V, PVIN=2.5V)
1.4
1.8
1.2
1.7
OUTPUT CURRENT(A)
OUTPUT CURRENT(A)
3.5
1
0.8
0.6
0.4
0.2
1.6
1.5
1.4
1.3
1.2
0
1.1
2
2.5
3
3.5
4
4.5
5
5.5
2
AVIN(V)
2.5
3
3.5
4
4.5
5
5.5
AVIN(V)
Maximum Sourcing Current vs AVIN
(VDDQ=2.5V, PVIN=3.3V)
OUTPUT CURRENT(A)
3
2.8
2.6
2.4
2.2
2
2
2.5
3
3.5
4
4.5
5
5.5
AVIN(V)
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Typical Performance Characteristics
AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1µF, CPVIN=47µF, CVREF=0.01µF, CVTT=220µF, TA=25°C, unless otherwise noted.
Maximum Sourcing Current vs AVIN
(VDDQ=1.8V, PVIN=1.8V)
3
1.4
2.8
1.2
OUTPUT CURRENT(A)
OUTPUT CURRENT(A)
Maximum Sinking Current vs AVIN
(VDDQ=2.5V)
2.6
2.4
2.2
2
1.8
1
0.8
0.6
0.4
0.2
1.6
0
1.4
2
2.5
3
3.5
4
4.5
5
2
5.5
2.5
3
3.5
4
4.5
5
5.5
AVIN(V)
AVIN(V)
Maximum Sourcing Current vs AVIN
(VDDQ=1.8V, PVIN=3.3V)
Maximum Sinking Current vs AVIN
(VDDQ=1.8V)
2.8
IO=200m
3
2.4
OUTPUT CURRENT(A)
OUTPUT CURRENT(A)
2.6
2.2
2
1.8
1.6
1.4
2.8
2.6
2.4
2.2
1.2
2
1
2
2.5
3
3.5
4
4.5
5
2
5.5
AVIN(V)
2.5
3
3.5
4
4.5
5
5.5
AVIN(V)
VOSVTT vs Temperature(VDDQ=2.5V)
30
Sourcing 1.5A
VOSVTT(mV)
20
10
No Load
0
-10
Sinking 1.5A
-20
-30
0
25
50
75
100
125
Temperature(℃)
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G2995
Typical Performance Characteristics (continued)
AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1µF/Ceramic X7R/0603/6.3V/TDK, CPVIN=68µF/6.3V POSCAP Series/SANYO, CVTT=330µF*2/6.3V POSCAP Series/SANYO, TA=25°C, unless otherwise noted.
ILoad=0.5A Transient (Sinking)
ILoad=0.5A Transient (Sourcing)
ILoad=1A Transient (Sinking)
ILoad=1A Transient (Sourcing)
ILoad=1.5A Transient (Sinking)
ILoad=1.5A Transient (Sourcing)
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Pin Description
NUMBER
NAME
1
2
NC
GND
FUNCTION
3
4
VSENSE
VREF
Feedback pin for regulating VTT
Buffered output that is a reference output of VDDQ/2
5
6
VDDQ
AVIN
Input for internal reference which equals to VDDQ/2
Analog input pin
7
8
PVIN
VTT
Power input pin
Output voltage for connection to termination resistors, equal to VDDQ/2
Ground
Block Diagram
VDDQ
AVIN
PVIN
50k
VREF
+
+
-
-
50k
VTT
VSENSE
GND
Description
VTT
VDD
The G2995 is a linear bus termination regulator designed to meet the JEDEC SSTL-2 and SSTL-3 (Series Stub Termination Logic) specifications for termination of DDR-SDRAM. The output, VTT, is capable of
sinking and sourcing current while regulating the output voltage equal to VDDQ/2. The G2995 is designed
to maintain the excellent load regulation and with fast
response time to minimum the transition preventing
shoot-through. The G2995 also incorporates two distinct power rails that separates the analog circuitry
(AVIN) from the power output stage (PVIN). This
power rails split can be utilized to reduce the internal
power dissipation. And this also permits G2995 to provide a termination solution for the next generation of
DDR-SDRAM (DDR II).
RT
RS
MENORY
CHIPSET
VREF
Figure 1. SSTL-Termination Scheme
AVIN, PVIN
AVIN and PVIN are two independent input supply pins
for the G2995. AVIN is used to supply all the internal
analog circuits. PVIN is only used to supply the output
stage to create the regulated VTT. To keep the regulation successfully, AVIN should be equal to or larger
than PVIN. Using a higher PVIN voltage will produce a
larger sourcing capability from VTT. But the internal
power loss will also increase and then the heat increases. If the junction temperature exceeds the
thermal shutdown threshold than the G2995 will enter
the shutdown state, where VTT is tri-state and VREF remains active.
For SSTL-2 applications, the AVIN and PVIN can be
short together at 2.5V to minimize the PCB complexity
and to reduce the bypassing capacitors for the two
supply pins separately.
Series Stub Termination Logic (SSTL) was created to
improve signal integrity of the data transmission
across the memory bus. This termination scheme is
essential to prevent data error from signal reflections
while transmitting at high frequencies encountered
with DDR-SDRAM. The most common form of termination is Class II single parallel termination. This involves one RS series resistor from the chipset to the
memory and one RT termination resistor, both 25Ω
typically. The resistors can be changed to scale the
current requirements from the G2995. This implementation can be seen below in Figure 1.
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VDDQ
A voltage divider of two 50kΩ is connected between
VDDQ and ground, to create the internal reference
voltage (VDDQ/2). This guarantees that VTT will track
VDDQ/2 precisely. The optimal implementation of
VDDQ is as a remote sensing. This can be achieved
by connecting VDDQ directly to the 2.5V rail (SSTL-2
applications) at the DIMM instead of AVIN and PVIN.
This will ensure that the reference voltage tracks the
DDR memory rails precisely without a large voltage
drop from the power lines.
G2995
mal performance. The RDS of MOS will increase when
the junction temperature increases. If the heat is not
dealt with well, the maximum output current will be
degraded. When the temperature exceeds the junction
temperature, the thermal shutdown protection is activated. That will drive the VTT output into tri-state until
the temperature returns below the hysteretic trigger
point.
Capacitors
The G2995 does not require the capacitors for input
stability, but it is recommended for improving the
performance during large load transition to prevent the
input power rail from dropping, especially for PVIN.
The input capacitor for PVIN should be as close as
possible. The typical recommended value is 50µF for
AL electrolytic capacitors, 10uF with X5R for the ceramic capacitors. To prevent the excessive noise coupling into this device, an additional 0.1µF ceramic capacitor can be placed on the AVIN power rail for the
better performance.
Vsense
The VSENSE pin is the feedback sensing pin of the operation amplifier which regulates the VTT voltage. In
most motherboard applications, the termination resistors will connect VTT in a long plane. If using the remote sensing pin – VSENSE to the middle of the bus, the
significant long-trace IR drop resulting in a termination
voltage which is lower at one end than the other can
be avoided. This will provide a better distribution
across the entire termination bus. If the remote load
regulation is not used, the VSENSE pin must still be
connected to VTT for correct regulation. Care should be
taken when a long VSENSE trace is implemented in
close proximity to the memory. Noise pickup in the
VSENSE trace can cause problems with precise regulation of VTT. A small 0.1µF ceramic capacitor placed
next to the VSENSE pin can help to filter any high frequency signals and preventing errors.
The output capacitor of the G2995 is suggested to use
the capacitors with low ESR. Using the capacitors with
low ESR (as ceramic, OS-CON, tantalum) will have
the better transition performance which is with smaller
voltage drop when the peak current occurring at the
transition. As a general recommendation the output
capacitor should be sized above 220µF with the low
ESR for SSTL applications with DDR-SDRAM.
Thermal Dissipation
When the current is sinking to or sourcing from VTT,
the G2995 will generate internal power dissipation
resulting in the heat. Care should be taken to prevent
the device from damages caused by the junction temperature exceeding the maximum rating. The maximum allowable internal temperature rise (TRMAX) can
be calculated under the given maximum ambient
temperature (TAMAX) of the application and the maximum allowable junction temperature (TJMAX).
VREF
VREF provides a buffered output of the internal reference voltage (VDDQ/2). It can support the reference
voltage of Northbridge chipset and memory. For better
performance, using an output bypass capacitor close
this pin is more helpful for the noise. A ceramic capacitor in the range of 0.1µF to 0.01µF is recommended.
VTT
VTT is the regulated output that is used to terminate the
bus resistors of DDR-SDRAM. It can precisely track
the VDDQ/2 voltage with the sinking and sourcing
current capability. The G2995 is designed to deliver
1.5A continuous current and peak current up to 3A
with a fast transient response @ 2.5V supply rail. The
maximum continuous current sourcing from VTT is a
function of PVIN. Using a higher PVIN will increase the
source current from VTT, but it also increase the internal power dissipation and reduce the efficiency. Although the G2995 can deliver the larger current, care
should be taken for the thermal dissipation when larger current is required. The G2995 is packaged with
Power-Pad to increase the power dissipation capability.
When driving larger current, the larger heat-sink in the
PCB is strongly recommended to have a better ther-
TRMAX= TJMAX - TAMAX
From this equation, the maximum power dissipation
(PDMAX) of the G2995 can be calculated:
PDMAX = TRMAX /θJA
θJA of the G2995 will be dependent on several variables: the packages used, the thickness and size of
the copper, the number of vias and the airflow. In the
package, the G2995 use the SO-8 with Power-PAD to
improve the θJA . If the layout of the PCB can put a
larger size of copper to contact the Power-PAD of this
device, the θJA will be further improved. The better θJA
is not only protecting the device well, but also increasing the maximum current capability at the same ambient temperature.
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Typical Application Circuits
ment the SSTL-2 termination scheme, it is recommended to connect all the input rails to 2.5V rail, as
seen in Figure 2. This provides an optimal trade-off
between power dissipation and component count.
There are several application circuits shown in Figure
2 through 8 to illustrate some of the possible configurations of the G2995. Figure 2~4 are the SSTL-2 applications. For the majority of applications that imple-
VREF
VDDQ
VDDQ=2.5V
VREF=1.25V
+
CREF
VDD=2.5V
CIN
AVIN
VSENSE
PVIN
VTT
+
VTT=1.25V
+
GND
COUT
Figure 2. Recommended SSTL-2 Implementation
device and improve the efficiency, but the disadvantage is the maximum continuous current sourcing from
VTT is reduced. This configuration is applied when the
power dissipation and efficiency are concerned.
In Figure 3, the power rails are split. The power rail of
the output stage (PVIN) can be as low as 1.8V, the
power rail of the analog circuit (AVIN) is operated
above 2V. The lower output stage power rail can lower
the internal power dissipation when sourcing from the
VDDQ
VDDQ=2.5V
VREF
+
VREF=1.25V
CREF
AVIN=1.8V or 5.5V
PVIN=1.8V
CIN
AVIN
VSENSE
PVIN
VTT
+
VTT=1.25V
+
GND
COUT
Figure 3. Lower Power Dissipation SSTL-2 Implementation
In Figure 4, the power rail of the output stage (PVIN) is
connected to 3.3V to increase the maximum continuous current sourcing from VTT. AVIN should be always
equal to or larger than PVIN. This configuration can
increase the source capability of this device, but the
power dissipation increases at the same time. It
should be more careful to prevent the junction temperature from exceeding the maximum rating. Because of this risk, it is not recommended to supply the
output stage power rail (PVIN) with a voltage higher
than a nominal 3.3V rail.
VDDQ
VDDQ=2.5V
VREF
+
VREF=1.25V
CREF
AVIN=3.3V or 5V
PVIN=3.3V
CIN
+
AVIN
VSENSE
PVIN
VTT
GND
VTT=1.25V
+
COUT
Figure 4. SSTL-2 Implementation with higher voltage rails
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is possible to use the G2995 in applications utilizing
DDR-II memory. Figure 6 is used to increase the driving capability. The risk is the same as figure 4.
In Figure 5 & 6, they are the application configurations
of DDR-II SDRAM bus terminations. Figure 5 is the
typical application scheme of DDR-II SDRAM. With the
separate VDDQ pin and an internal resistor divider, it
VREF
VDDQ
VDDQ=1.8V
AVIN=1.8V or 5.5V
AVIN
VSENSE
PVIN=1.8V
PVIN
VTT
CIN
+
+
VTT=0.9V
+
GND
VREF=0.9V
CREF
COUT
Figure 5. Recommended DDR-II Termination
VREF
VDDQ
VDDQ=1.8V
AVIN=3.3V or 5.5V
AVIN
VSENSE
PVIN=3.3V
PVIN
VTT
CIN
+
+
VTT=0.9V
+
GND
VREF=0.9V
CREF
COUT
Figure 6. DDR-II Termination with higher voltage rails
Figure 7 & 8 are used to scale the VTT to the wanted
value when the standard voltages of SSTL-2 do not
meet the requirements. Using R1 & R2, Figure 7 can
VDDQ
VDDQ
VDD
AVIN
shift VTT up to VDDQ/2 * (1+R1/R2) and figure 8 can
shift VTT down to VDDQ/2 * (1-R1/R2).
VSENSE
PVIN
CIN
+
VTT
VTT
R1
+
COUT
R2
GND
Figure 7. Increasing VTT by Level Shifting
R2
VDDQ
VDDQ
VDD
AVIN
VSENSE
R1
PVIN
VTT
VTT
+
CIN
+
GND
COUT
Figure 8. Decreasing VTT by Level Shifting
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Package Information
C
E
H
L
D
θ
7 ° (4X)
A2
A
A1
y
e
B
SOP-8L Package
Note:
1. Package body sizes exclude mold flash and gate burrs
2. Dimension L is measured in gage plane
3. Tolerance 0.10mm unless otherwise specified
4. Controlling dimension is millimeter converted inch dimensions are not necessarily exact.
5. Followed from JEDEC MS-012
MIN.
DIMENSION IN MM
NOM.
MAX.
MIN.
DIMENSION IN INCH
NOM.
MAX.
A
A1
1.35
0.10
1.60
-----
1.75
0.25
0.053
0.004
0.063
-----
0.069
0.010
A2
B
C
D
E
----0.33
0.19
4.80
3.80
1.45
-----------------
----0.51
0.25
5.00
4.00
----0.013
0.007
0.189
0.150
0.057
-----------------
----0.020
0.010
0.197
0.157
e
H
----5.80
1.27
-----
----6.20
----0.228
0.050
-----
----0.244
L
y
θ
0.40
-----
---------
1.27
0.10
0.016
-----
---------
0.050
0.004
0º
-----
8º
0º
-----
8º
SYMBOL
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C
E1
E
H
D1
L
D
θ
7 ° (4X)
A2
A
A1
y
e
B
SOP- 8L (FD) Package
Note:
1. Package body sizes exclude mold flash and gate burrs
2. Dimension L is measured in gage plane
3. Tolerance 0.10mm unless otherwise specified
4. Controlling dimension is millimeter converted inch dimensions are not necessarily exact.
5. Followed from JEDEC MS-012
MIN.
DIMENSION IN MM
NOM.
MAX.
MIN.
DIMENSION IN INCH
NOM.
A
1.45
1.50
1.55
0.057
0.059
0.061
A1
A2
0.00
-----
----1.45
0.10
-----
0.000
-----
----0.057
0.004
-----
B
C
0.33
0.19
---------
0.51
0.25
0.013
0.007
---------
0.020
0.010
D
E
4.80
3.80
---------
5.00
4.00
0.189
0.150
---------
0.197
0.157
e
H
----5.80
1.27
-----
----6.20
----0.228
0.050
-----
----0.244
L
0.40
-----
1.27
0.016
-----
0.050
y
θ
-----
-----
0.10
-----
-----
0.004
D1
0º
2.22
---------
8º
2.60
0º
0.087
---------
8º
0.102
E1
2.60
-----
2.98
0.102
-----
0.117
SYMBOL
MAX.
Taping Specification
PACKAGE
Q’TY/REEL
SOP-8
2,500 ea
SOP-8 (FD)
2,500 ea
Feed Direction
Typical SOP Package Orientation
GMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications.
TEL: 886-3-5788833
http://www.gmt.com.tw
Ver: 1.7
May 10, 2005
12
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