MOTOROLA MC14415FL Quad precision timer/driver Datasheet

SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
MC14415 quad timer/driver is constructed with complementary MOS
enhancement mode devices. The output pulse width of each digital timer is
a function of the input clock frequency. Once the proper input sequence is
detected the output buffer is set (turned on), and after 100 clock pulses are
counted, the output buffer is reset (turned off).
The MC14415 was designed specifically for application in high speed line
printers to provide the critical timing of the hammer drivers, but may be used
in many applications requiring precision pulse widths.
•
•
•
•
•
•
Four Precision Digital Time Delays
Schmitt Trigger Clock Conditioning
NPN Bipolar Output Drivers
Timing Disable Capability Using Inhibit Output
Positive or Negative Edge Strobing on the Inputs
Synchronous Polynomial Counters Used for Delay Counting
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MAXIMUM RATINGS* (Voltages Referenced to VSS)
Rating
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14415FP (3.0 V–18 V)
MC14415VP (3.0 V–6.0 V)
MC14415FL (3.0 V–18 V)
MC14415VL (3.0 V–6.0 V)
MC14415DW (3.0 V–18 V)
Plastic
Plastic
Ceramic
Ceramic
SOIC
Symbol
Value
Unit
DC Supply Voltage MC14415FL, FP,DW
MC14415VL, VP
VDD
– 0.5 to + 18.0
– 0.5 to + 6.0
V
Input or Output Voltage (DC or Transient)
Vin, Vout
– 0.5 to VDD + 0.5
V
Iin
± 10
mA
Output Current (DC or Transient), per Pin
Iout
± 20
mA
Power Dissipation, per Package†
PD
500
mW
CLOCK
1
16
VDD
Storage Temperature
Tstg
– 65 to + 150
_C
SET
2
15
INH
TL
260
_C
SET A
3
14
OUT A
SET B
4
13
OUT B
SET C
5
12
OUT C
SET D
6
11
OUT D
ST 1
7
10
DIS
VSS
8
9
ST2
Input Current (DC or Transient), per Pin
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
SET A 3
SET B 4
SET C 5
TA = – 55° to 125°C for all packages.
PIN ASSIGNMENT
14 OUTPUT A
INPUT
LOGIC
DIVIDE–BY–
100
COUNTERS
SET D 6
OUTPUT
BUFFERS
13 OUTPUT B
12 OUTPUT C
11 OUTPUT D
STROBE 2 9
STROBE 1 7
INPUT DISABLE 10
COMMON
LOGIC
CLOCK
CONDITIONING
CIRCUIT
VDD = PIN 16
VSS = PIN 8
OUTPUT SET 2
CLOCK 1
OUTPUT INHIBIT 15
REV 3
1/94
MC14415
Motorola, Inc. 1995
290
MOTOROLA CMOS LOGIC DATA
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v
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v
v
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v
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v
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v
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
(No Load)
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.01
0.01
—
—
—
—
0
0
—
0.01
0.01
—
—
—
—
0.05
0.05
—
Vdc
“1” Level
VOH
5.0
10
15
—
—
—
—
—
—
3.0
8.0
—
4.14
9.09
14.12
—
—
—
—
—
—
—
—
—
Vdc
5.0
10
15
1.5
3.0
—
—
—
—
1.5
3.0
—
2.25
4.50
6.75
—
—
—
1.4
2.9
—
—
—
—
5.0
10
15
1.4
2.9
—
—
—
—
1.5
3.0
—
2.25
4.50
6.75
—
—
—
1.5
3.0
—
—
—
—
5.0
—
—
—
—
—
—
—
—
3.0
2.7
2.5
2.2
4.14
3.44
3.30
3.08
—
—
—
—
—
—
—
—
—
—
—
—
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
10
—
—
—
—
—
—
—
—
8.0
7.7
7.5
7.1
9.09
8.45
8.30
8.14
—
—
—
—
—
—
—
—
—
—
—
—
Vdc
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
15
—
—
—
—
—
—
—
—
—
—
—
—
14.12
13.81
13.70
13.61
—
—
—
—
—
—
—
—
—
—
—
—
Vdc
5.0
10
15
0.23
0.60
—
—
—
—
0.2
0.5
—
0.78
2.0
7.8
—
—
—
0.16
0.40
—
—
—
—
Noise Immunity
(∆Vout
1.5 Vdc)
(∆Vout
3.0 Vdc)
(∆Vout
4.5 Vdc)
(∆Vout
(∆Vout
(∆Vout
VNL
1.5 Vdc)
3.0 Vdc)
4.5 Vdc)
VNH
Output Drive Voltage (NPN Driver)
(IOH = 0 mA)
Source
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
VOH
Output Drive Current
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
Vdc
IOL
Sink
mAdc
Input Leakage Current
Iin
15
—
± 0.3
—
± 0.00001
± 0.3
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
—
—
—
pF
Quiescent Dissipation
PQ
5.0
10
15
—
—
—
0.25
1.0
—
—
—
—
0.00005
0.00022
0.00050
0.25
1.0
—
—
—
—
3.5
14
—
mW
Power Dissipation**
(Dynamic plus Quiescent)
(CL = 15 pF)
PD
5.0
10
15
PD (56 mW/MHz) f + PQ
PD (225 mW/MHz) f + PQ
PD (510 mW/MHz) f + PQ
mW
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MOTOROLA CMOS LOGIC DATA
MC14415
291
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 15 pF, TA = 25_C)
Characteristic
Symbol
Output Rise Time
tTLH = (2.0 ns/pF) CL + 10 ns
tTLH = (1.25 ns/pF) CL + 6 ns
tTLH = (1.10 ns/pF) CL + 3 ns
tTLH
Output Fall Time
tTHL = (1.5 ns/pF) CL + 47 ns
tTHL = (0.75 ns/pF) CL + 24 ns
tTHL = (0.55 ns/pF) CL + 17 ns
tTHL
Turn–Off Delay Time
tPLH = (2.7 ns/pF) CL + 560 ns
tPLH = (1.2 ns/pF) CL + 282 ns
tPLH = (0.91 ns/pF) CL + 286 ns
tPLH
Turn–On Delay Time
tPHL = (2.4 ns/pF) CL + 564 ns
tPHL = (1.0 ns/pF) CL + 285 ns
tPHL = (0.75 ns/pF) CL + 289 ns
tPHL
Turn–On Delay Time (Inhibit to Output)
tPHL
Turn–Off Delay Time (Inhibit to Output)
VDD
Vdc
Min
Typ #
Max
5.0
10
15
—
—
—
40
25
20
85
60
—
5.0
10
15
—
—
—
70
35
25
150
80
—
5.0
10
15
—
—
—
600
300
150
1200
600
—
5.0
10
15
—
—
—
600
300
150
1200
600
—
5.0
10
15
—
—
—
300
225
110
550
425
—
5.0
10
15
—
—
—
300
225
110
550
425
—
5.0
10
15
500
450
—
450
350
—
—
—
—
5.0
10
15
500
450
—
450
350
—
—
—
—
5.0
10
15
—
—
—
0.7
1.0
1.5
—
—
—
5.0
10
15
—
—
—
—
—
—
15
5.0
4.0
ns
ns
ns
ns
ns
tPLH
Input Pulse Coincidence (Figure 3)
ns
PCmin
Input Pulse Width (Figure 1)
ns
tWH
Input Clock Frequency
ns
fcl
Clock Input Rise and Fall Times (Figure 1)
Unit
MHz
tTLH, tTHL
µs
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
90%
50%
INPUT
tPLH
OUTPUT
10%
VSS
tWH
90%
VOH
50%
10%
tTLH
CLOCK
20 ns
VDD
1
VOL
tTHL
2
100
tPHL
OUTPUT
50%
VDD
VSS
VOH
VOL
Figure 1. Switching Characteristics — Waveform Relationships
MC14415
292
MOTOROLA CMOS LOGIC DATA
INPUT DISABLE
INPUT DISABLE
STROBE 2
STROBE 2
STROBE 1
STROBE 1
SET A
MINIMUM COINCIDENCE =
500 ns @ VDD = 4.75 Vdc
50%
OUTPUT SET
SET A
MINIMUM COINCIDENCE =
500 ns @ VDD = 4.75 Vdc
50%
OUTPUT SET
50%
OUTPUT INHIBIT
OUTPUT INHIBIT
1
CLOCK
2
CLOCK
100
50%
OUTPUT A
1
OUTPUT A
tPLH
2
100
50%
tPLH
tPHL
Mode 1: OUTPUT SET Initiates Time Delay
tPHL
Mode 2: Set A Initiates Time Delay
INPUT DISABLE
STROBE 2
INPUT DISABLE
STROBE 1
STROBE 2
SET A
50%
STROBE 1
50%
OUTPUT SET
MINIMUM COINCIDENCE =
500 ns @ VDD = 4.75 Vdc
SET A
50%
OUTPUT INHIBIT
CLOCK
1
OUTPUT A
OUTPUT SET
2
CLOCK
100
OUTPUT A
50%
tPLH
tPHL
tPLH
tPHL
Mode 3: OUTPUT INHIBIT Disables Time Delay
1
100
50%
tPLH
tPHL
Mode 4: Positive–Edge Strobe (ST2)
Initiates Time Delay
Figure 2. Typical Operation Modes and Functional Timing Diagram
MOTOROLA CMOS LOGIC DATA
MC14415
293
MC14415
294
CLOCK 1
INPUT DISABLE 10
STROBE 1 7
STROBE 2 9
OUTPUT SET 2
SET D 6
SET C 5
SET B 4
SET A 3
SCHMITT CLOCK
CONDITIONING
CIRCUIT
S
S
S
S
Q
R
Q
R
Q
R
Q
R
C1
C2
15
OUTPUT INHIBIT
DIVIDE–BY–100
SYNCHRONOUS
COUNTER
ENABLE
DIVIDE–BY–100
SYNCHRONOUS
COUNTER
ENABLE
C1
C2
DIVIDE–BY–100
C1 SYNCHRONOUS
COUNTER
ENABLE
C2
DIVIDE–BY–100
C1 SYNCHRONOUS
COUNTER
ENABLE
C2
C1
C2
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
11 OUTPUT D
12 OUTPUT C
13 OUTPUT B
14 OUTPUT A
LOGIC DIAGRAM
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
J
16 PL
0.25 (0.010)
MOTOROLA CMOS LOGIC DATA
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14415
295
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
ISSUE A
–A–
16
9
–B–
8X
P
0.010 (0.25)
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
B
M
8
16X
J
D
0.010 (0.25)
M
T A
S
B
S
F
R X 45 _
C
–T–
14X
G
K
SEATING
PLANE
M
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
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MC14415
296
◊
*MC14415/D*
MOTOROLA CMOS LOGIC
DATA
MC14415/D
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