AMIC A67L16181E 2m x 18, 1m x 36 lvttl, flow-through zebl sram Datasheet

A67L16181/A67L06361 Series
Preliminary
2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM
Document Title
2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM
Revision History
History
Issue Date
Remark
0.0
Initial issue
July 26, 2004
Preliminary
0.1
Change speed grade from cycle time to access time
February 17, 2005
Rev. No.
PRELIMINARY
(February, 2005, Version 0.1)
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Preliminary
2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM
Features
Fast access time: 6.5/7.5/8.5 ns
(153, 133, 117 MHz)
Zero Bus Latency between READ and WRITE cycles
allows 100% bus utilization
Signal +3.3V ± 5% power supply
Individual Byte Write control capability
Clock enable ( CEN ) pin to enable clock and suspend
operations
Clock-controlled and registered address, data and control
signals
Registered output for pipelined applications
Three separate chip enables allow wide range of options
for CE control, address pipelining
Internally self-timed write cycle
Selectable BURST mode (Linear or Interleaved)
SLEEP mode (ZZ pin) provided
Available in 100 pin LQFP package
General Description
The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs
high-speed, low-power CMOS designs using an advanced
CMOS process.
The A67L16181, A67L06361 SRAMs integrate a 2M X 18,
1M X 36 SRAM core with advanced synchronous peripheral
circuitry and a 2-bit burst counter. These SRAMs are
optimized for 100 percent bus utilization without the insertion
of any wait cycles during Write-Read alternation. The positive
edge triggered single clock input (CLK) controls all
synchronous inputs passing through the registers. The
synchronous inputs include all address, all data inputs, active
low chip enable ( CE ), two additional chip enables for easy
depth expansion (CE2, CE2 ), cycle start input (ADV/ LD ),
synchronous clock enable ( CEN ), byte write enables
by the chip and controlled by the same input pin ADV/ LD in
High state.
Write cycles are internally self-time and synchronous with the
rising edge of the clock input and when R/ W is Low. The
feature simplified the write interface. Individual Byte enables
allow individual bytes to be written. BW1 controls I/Oa pins;
BW2 controls I/Ob pins; BW3 controls I/Oc pins; and BW4
controls I/Od pins. Cycle types can only be defined when an
address is loaded.
The SRAM operates from a +3.3V power supply, and all
inputs and outputs are LVTTL-compatible. The device is
ideally suited for high bandwidth utilization systems.
( BW1, BW2 , BW3 , BW4 ) and read/write (R/ W ).
Asynchronous inputs include the output enable ( OE ), clock
(CLK), SLEEP mode (ZZ, tied LOW if unused) and burst
mode (MODE). Burst Mode can provide either interleaved or
linear operation, burst operation can be initiated by
synchronous address Advance/Load (ADV/ LD ) pin in Low
state. Subsequent burst address can be internally generated
PRELIMINARY
(February, 2005, Version 0.1)
2
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Pin Configuration
A18
A8
A9
83
82
81
A9
A19
84
A17
OE
ADV/
LD
86
A8
CEN
87
A18
OE
ADV/
LD
R/W
88
85
CEN
CLK
89
CLK
VSS
90
R/W
VCC
91
VSS
CE2
92
VCC
BW1
93
BW1
BW2
94
CE2
NC
95
BW2
BW4
NC
96
BW3
CE2
CE2
97
A7
CE
98
2M X 18
CE
A7
99
A6
A6
100
1M X 36
I/Oc8
NC
1
80
A10
I/Oc0
NC
2
79
NC
I/Ob7
I/Oc1
NC
3
78
NC
I/Ob6
VCCQ
VCCQ
4
77
VCCQ
VCCQ
VSSQ
VSSQ
5
76
VSSQ
VSSQ
I/Oc2
NC
6
75
NC
I/Ob5
I/Oc3
NC
7
74
I/Oa0
I/Ob4
I/Oc4
I/Ob8
8
73
I/Oa1
I/Ob3
I/Oc5
I/Ob7
9
72
I/Oa2
I/Ob2
VSSQ
VSSQ
10
71
VSSQ
VSSQ
VCCQ
VCCQ
11
70
VCCQ
VCCQ
I/Ob8
I/Oc6
I/Ob6
12
69
I/Oa3
I/Ob1
I/Oc 7
I/Ob5
13
68
I/Oa4
I/Ob0
VSS
VSS
14
67
VSS
VSS
VCC
VCC
15
66
VSS
VSS
VCC
VCC
16
65
VCC
VCC
VSS
VSS
17
64
ZZ
ZZ
I/Od 0
I/Ob4
18
63
I/Oa5
I/Oa7
I/Od 1
I/Ob3
19
62
I/Oa6
I/Oa6
VCCQ
VCCQ
20
61
VCCQ
VCCQ
VSSQ
VSSQ
21
60
VSSQ
VSSQ
I/Od 2
I/Ob 2
22
59
I/Oa7
I/Oa5
I/Od 3
I/Ob 1
23
58
I/Oa8
I/Oa4
I/Od 4
I/Ob 0
24
57
NC
I/Oa3
I/Od 5
NC
25
56
NC
I/Oa2
VSSQ
VSSQ
26
55
VSSQ
VSSQ
VCCQ
VCCQ
27
54
VCCQ
VCCQ
I/Od6
NC
28
53
NC
I/Oa1
I/Od7
NC
29
52
NC
I/Oa0
I/Od8
NC
30
51
NC
I/Oa8
PRELIMINARY
43
44
45
46
47
48
49
50
A20
A11
A12
A13
A14
A15
A16
A17
A10
A11
A12
A13
A14
A15
A16
40
A19
39
NC
NC
42
38
NC
NC
NC
37
A0
A0
NC
36
A1
A1
41
35
A2
A2
VSS
34
A3
A3
VCC
33
A4
A4
VSS
32
A5
A5
(February, 2005, Version 0.1)
VCC
31
MODE MODE
A67L16181E
A67L06361E
3
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Block Diagram (1M X 36)
ZZ
MODE
LOGIC
MODE
ADV/LD
CLK
LOGIC
CEN
CLK
A0-A19
BURST
LOGIC
ADDRESS
COUNTER
CLR
WRITE
ADDRESS
REGISTER
ADDRESS
REGISTERS
9
9
ADV/LD
R/W
BW1
BW2
WRITE
REGISTRY
&
CONTROL
LOGIC
9
BYTEb
WRITE
DRIVER
9
1MX9X4
MEMORY
9
9
BW3
BW4
BYTEa
WRITE
DRIVER
BYTEc
WRITE
DRIVER
9
BYTEd
WRITE
DRIVER
9
SENSE
AMPS
OUTPUT
BUFFERS
I/O s
ARRAY
DATA-IN
REGISTERS
CE
CHIP
ENABLE
LOGIC
CE2
CE2
FLOW-THROUGH
ENABLE
LOGIC
OUTPUT
ENABLE
LOGIC
OE
PRELIMINARY
(February, 2005, Version 0.1)
4
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Block Diagram (2M X 18)
ZZ
MODE
LOGIC
MODE
ADV/LD
CLK
LOGIC
CEN
CLK
A0- A20
BURST
LOGIC
ADDRESS
COUNTER
CLR
WRITE
ADDRESS
REGISTER
ADDRESS
REGISTERS
9
ADV/LD
R/W
BW1
BW2
WRITE
REGISTRY
&
CONTROL
LOGIC
BYTEa
WRITE
DRIVER
9
2MX9X2
MEMORY
9
BYTEb
WRITE
DRIVER
9
SENSE
AMPS
OUTPUT
BUFFERS
I/O S
ARRAY
DATA-IN
REGISTERS
CE
CHIP
ENABLE
LOGIC
CE2
CE2
FLOWTHROUGH
ENABLE LOGIC
OUTPUT
ENABLE
LOGIC
OE
PRELIMINARY
(February, 2005, Version 0.1)
5
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Pin Description
Pin No.
Symbol
Description
A0
A1
A2 – A9
Synchronous Address Inputs : These inputs are registered and
must meet the setup and hold times around the rising edge of
CLK. Pins 83 and 84 are reserved as address bits for higherdensity 9Mb and 18Mb DBA SRAMs, respectively. A0 and A1 are
the two lest significant bits (LSB) of the address field and set the
internal burst counter if burst is desired.
LQFP (X18)
LQFP (X36)
37
36
35,34,33,32,
100,99,82,81
44,45,46,47,
48,49,50,83,84
43
80
37
36
35,34,33,32,
100,99,82,81
45,46,47,48,
49,50,83,84,43
93 ( BW1)
94 ( BW2 )
93 ( BW1)
94 ( BW2 )
95 ( BW3 )
96 ( BW4 )
BW1
BW2
BW3
89
89
CLK
Clock : This signal registers the address, data, chip enables, byte
write enables and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock’s rising edge.
98
98
CE
Synchronous Chip Enable : This active low input is used to enable
the device. This input is sampled only when a new external
address is loaded (ADV/ LD LOW).
92
92
CE2
Synchronous Chip Enable : This active low input is used to enable
the device and is sampled only when a new external address is
loaded (ADV/ LD LOW). This input can be used for memory depth
expansion.
97
97
CE2
Synchronous Chip Enable : This active high input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/ LD LOW). This input can be used for
memory depth expansion.
86
86
OE
Output Enable : This active low asynchronous input enables the
data I/O output drivers.
85
85
ADV/ LD
Synchronous Address Advance/Load : When HIGH, this input is
used to advance the internal burst counter, controlling burst
access after the external address is loaded. When HIGH, R/ W is
ignored. A LOW on this pin permits a new address to be loaded at
CLK rising edge.
87
87
CEN
Synchronous Clock Enable : This active low input permits CLK to
propagate throughout the device. When HIGH, the device ignores
the CLK input and effectively internally extends the previous CLK
cycle. This input must meet setup and hold times around the
rising edge of CLK.
PRELIMINARY
44
A11-A19
A20
A10
BW4
(February, 2005, Version 0.1)
Synchronous Byte Write Enables : These active low inputs allow
individual bytes to be written when a WRITE cycle is active and
must meet the setup and hold times around the rising edge of
CLK. BYTE WRITEs need to be asserted on the same cycle as
the address, BWs are associated with addresses and apply to
subsequent data. BW1 controls I/Oa pins; BW2 controls I/Ob pins;
BW3 controls I/Oc pins; BW4 controls I/Od pins.
6
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Pin Description (continued)
Pin No.
Symbol
Description
LQFP (X18)
LQFP (X36)
64
64
ZZ
Snooze Enable : This active high asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When active, all other inputs are
ignored.
88
88
R/ W
Read/Write : This active input determines the cycle type when
ADV/ LD is LOW. This is the only means for determining READs
and WRITEs. READ cycles may not be converted into WRITEs
(and vice versa) other than by loading a new address. A LOW on
this pin permits BYTE WRITE operations and must meet the setup
and hold times around the rising edge of CLK. Full bus width
WRITEs occur if all byte write enables are LOW.
52, 53, 56, 57,
58, 59, 62, 63, 51
68, 69, 72, 73, 74,
75, 78, 79, 80
2, 3, 6, 7, 8, 9, 12,
13,1
18, 19, 22, 23, 24,
25, 28, 29, 30
I/Oa
SRAM Data I/O : Byte “a” is I/Oa pins; Byte “b” is I/Ob pins; Byte
“c” is I/Oc pins; Byte “d” is I/Od pins. Input data must meet setup
and hold times around CLK rising edge.
31
31
MODE
1, 2, 3, 6, 7, 25, 28,
29, 30, 38, 39, 42,
51, 52, 53, 56, 57,
75, 78, 79, 95, 96
38,39,42
NC
15, 16, 41, 65, 91
15, 16, 41, 65, 91
VCC
4, 11, 20, 27,
54, 61, 70, 77
4, 11, 20, 27,
54, 61, 70, 77
VCCQ
14, 17, 40, 66, 90
14, 17, 40, 66, 90
VSS
5,10,21,26,
55,60,71,76
5,10,21,26,
55,60,71,76
VSSQ
74, 73, 72, 69, 68
63, 62, 59, 58
24, 23, 22, 19, 18
13, 12, 9, 8
PRELIMINARY
I/Ob
I/Oc
I/Od
(February, 2005, Version 0.1)
Mode: This input selects the burst sequence. A LOW on this pin
selects linear burst. NC or HIGH on this pin selects interleaved
burst. Do not alter input state while device is operating.
No Connect : These pins can be left floating or connected to GND
to minimize thermal impedance.
Power Supply
Isolated Output Buffer Supply
Ground : GND.
Isolated Output Buffer Ground
7
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Truth Table (Notes 5 - 7)
Operation
Address
Used
None
CE
CE2
CE2
ZZ
ADV/
LD
L
R/ W
BWx
OE
CEN
CLK
I/O
Notes
Deselected Cycle,
H
X
X
L
X
X
X
L
L→H
High-Z
Power-down
Deselected Cycle,
None
X
H
X
L
L
X
X
X
L
L→H
High-Z
Power-down
Deselected Cycle,
None
X
X
L
L
L
X
X
X
L
L→H
High-Z
Power-down
Continue Deselect
None
X
X
X
L
H
X
X
X
L
L→H
High-Z
1
Cycle
READ Cycle
External
L
L
H
L
L
H
X
L
L
L→H
Q
(Begin Burst)
READ Cycle
Next
X
X
X
L
H
X
X
L
L
L→H
Q
1,7
(Continue Burst)
NOP/Dummy READ
External
L
L
H
L
L
H
X
H
L
L→H
High-Z
2
(Begin Burst)
Dummy READ
Next
X
X
X
L
H
X
X
H
L
L→H
High-Z
1,2,7
(Continue Burst)
WRITE Cycle
External
L
L
H
L
L
L
L
X
L
L→H
D
3
(Begin Burst)
WRITE Cycle
Next
X
X
X
L
H
X
L
X
L
L→H
D
1,3,7
(Continue Burst)
NOP/WRITE Abort
None
L
L
H
L
L
L
H
X
L
L→H
High-Z
2,3
(Begin Burst)
WRITE Abort
Next
X
X
X
L
H
X
H
X
L
L→H
High-Z
1,2,3,7
(Continue Burst)
IGNORE Clock Edge
Current
X
X
X
L
X
X
X
X
H
L→ H
4
(Stall)
SLEEP Mode
None
X
X
X
H
X
X
X
X
X
X
High-Z
Notes:
1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is
executed first.
2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE
Abort means a WRITE command is given, but no operation is performed.
3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the
output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their
requirements.
4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs during
a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock Edge cycle.
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals ( BW1, BW2 , BW3
and BW4 ) are HIGH. BWx = L means one or more byte write signals are LOW.
6. BW1enables WRITEs to Byte “a” (I/Oa pins); BW2 enables WRITEs to Byte “b” (I/Ob pins); BW3 enables WRITEs to Byte
“c” (I/Oc pins); BW4 enables WRITEs to Byte “d” (I/Od pins).
7. The address counter is incremented for all Continue Burst cycles.
PRELIMINARY
(February, 2005, Version 0.1)
8
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Partial Truth Table for READ/WRITE Commands (X18)
Operation
R/ W
BW1
BW2
READ
H
X
X
WRITE Byte “a”
L
L
H
WRITE Byte “b”
L
H
L
WRITE all bytes
L
L
L
WRITE Abort/NOP
L
H
H
Note : Using R/ W and BYTE WRITE(s), any one or more bytes may be written.
Partial Truth Table for READ/WRITE Commands (X36)
Operation
R/ W
BW1
BW2
BW3
BW4
READ
H
X
X
X
X
WRITE Byte “a”
L
L
H
H
H
WRITE Byte “b”
L
H
L
H
H
WRITE Byte “c”
L
H
H
L
H
WRITE Byte “d”
L
H
H
H
L
WRITE all bytes
L
L
L
L
L
WRITE Abort/NOP
L
H
H
H
H
Note : Using R/ W and BYTE WRITE(s), any one or more bytes may be written.
Linear Burst Address Table (MODE = LOW)
First Address (External)
Second Address (Internal)
Third Address (Internal)
Fourth Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
Interleaved Burst Address Table (MODE = HIGH or NC)
First Address (External)
Second Address (Internal)
Third Address (Internal)
Fourth Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
PRELIMINARY
(February, 2005, Version 0.1)
9
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Absolute Maximum Ratings*
*Comments
Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V
Voltage Relative to GND for any Pin Except VCC (Vin,
Vout) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Operating Temperature (Topr) . . . . . . . . . . . 0°C to 70°C
Storage Temperature (Tbias) . . . . . . . . . . -10°C to 85 °C
Storage Temperature (Tstg) . . . . . . . . . . -55°C to 125°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics and Operating Conditions
(0°C ≤ TA ≤ 70°C, VCC, VCCQ = +3.3V± 5% unless otherwise noted)
Symbol
Parameter
Conditions
Min.
Max.
Unit
Note
VIH
Input High Voltage
2.0
VCC+0.3
V
1,2
VIL
Input Low Voltage
-0.3
0.8
V
1,2
ILI
Input Leakage Current
0V ≤ VIH ≤ VCC
-2.0
2.0
µA
ILO
Output Leakage Current
Output(s) disabled,
-2.0
2.0
µA
0V ≤ VIN≤ VCC
VOH
Output High Voltage
IOH = -4.0mA
VOL
Output Low Voltage
IOL = 8.0mA
VCC
Supply Voltage
Isolated Output Buffer Supply
VCCQ
2.4
V
1,3
0.4
V
1,3
3.135
3.465
V
1
3.135
VCC
V
1,4
Conditions
Typ.
Max.
Unit
Note
Capacitance
Symbol
Parameter
CI
Control Input Capacitance
TA = 25°C; f = 1MHz
3
4
pF
6
CO
Input/Output Capacitance (I/O)
VCC = 3.3V
4
5
pF
6
CA
Address Capacitance
3
3.5
pF
6
Note : 1. All voltages referenced to VSS (GND).
2. Overshoot :
VIH ≤ +4.6V for t ≤ tKHKH/2 for I ≤ 20mA
Undershoot : VIL ≥ -0.7V for t ≤ tKHKH/2 for I ≤ 20mA
Power-up :
VIH ≤ +3.465V and VCC ≤ 3.135 for t ≤ 200ms
3. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values.
AC I/O curves are available upon request.
4. VCC and VCCQ can be externally wired together to the same power supply.
5. This parameter is sampled.
PRELIMINARY
(February, 2005, Version 0.1)
10
AMIC Technology, Corp.
A67L16181/A67L06361 Series
ICC Operating Condition and Maximum Limits
Max.
Symbol
Parameter
-6.5
-7.5
-8.5
Unit
Conditions
ICC
Power Supply Current :
Operating
400
400
400
mA
Device selected; All inputs ≤ VIL or ≥
VIH; Cycle time ≥ tKC (MIN); VCC =
MAX; Output open
ISB
Standby
TBD
TBD
TBD
mA
Device deselected; VCC = MAX;
inputs ≤ VSS+0.2 or ≥ VCC-0.2;
Cycle time ≥ tKC (MIN)
All
ISB
Standby
TBD
TBD
TBD
mA
Device deselected; VCC = MAX; All
inputs ≤VSS+0.2 or ≥ VCC-0.2; All
inputs static; CLK frequency=MAX; ZZ
≥ VCC-0.2V
ISB2
Standby
TBD
TBD
TBD
mA
Device deselected; VCC = MAX; All
inputs ≤ VIL; or ≥ VIH;
All
inputs static; CLK frequency=0
ISB2Z
SLEEP Mode
TBD
TBD
TBD
mA
ZZ ≥ VIH
PRELIMINARY
(February, 2005, Version 0.1)
11
AMIC Technology, Corp.
A67L16181/A67L06361 Series
AC Characteristics (Note 4)
(0°C ≤ TA ≤ 70°C, VCC = +3.3V± 5%)
Symbol
-6.5
Parameter
-7.5
-8.5
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Note
Clock
tKHKH
Clock cycle time
7.5
-
-8.5
-
10
-
ns
tKF
Clock frequency
-
133
-
117
-
100
MHz
tKHKL
Clock HIGH time
2.5
-
2.8
-
3.0
-
ns
tKLKH
Clock LOW time
2.5
-
2.8
-
3.0
-
ns
-
6.5
-
7.5
-
8.5
ns
Output Times
tKHQV
Clock to output valid
tKHQX
Clock to output invalid
3.0
-
3.0
-
3.0
-
ns
tKHQX1
Clock to output in Low-Z
2.5
-
2.5
-
2.5
-
ns
1,2,3
tKHQZ
Clock to output in High-Z
1.5
3.8
1.5
4.0
1.5
5.0
ns
1,2,3
tGLQV
OE to output valid
-
3.5
-
3.5
-
4.0
ns
4
tGLQX
OE to output in Low-Z
0
-
0
-
0
-
ns
1,2,3
tGHQZ
OE to output in High-Z
-
3.5
-
3.5
-
4.0
ns
1,2,3
Setup Times
tAVKH
Address
1.5
-
2.0
-
2.0
-
ns
5
tEVKH
Clock enable ( CEN)
1.5
-
2.0
-
2.0
-
ns
5
tCVKH
Control signals
1.5
-
2.0
-
2.0
-
ns
5
tDVKH
Data-in
1.5
-
2.0
-
2.0
-
ns
5
Hold Times
tKHAX
Address
0.5
-
0.5
-
0.5
-
ns
5
tKHEX
Clock enable ( CEN)
0.5
-
0.5
-
0.5
-
ns
5
tKHCX
Control signals
0.5
-
0.5
-
0.5
-
ns
5
tKHDX
Data-in
0.5
-
0.5
-
0.5
-
ns
5
Notes: 1. This parameter is sampled.
2. Output loading is specified with C1=5pF as in Figure 2.
3. Transition is measured ±200mV from steady state voltage.
4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system for
turnaround timing.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when ADV/ LD is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with stable logic
levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of
CLK (when ADV/ LD is LOW) to remain enabled.
PRELIMINARY
(February, 2005, Version 0.1)
12
AMIC Technology, Corp.
A67L16181/A67L06361 Series
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
1.0ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures 1 and 2
+3.3V
319Ω
Q
Q
ZO=50Ω
50Ω
353Ω
5pF
VT=1.5V
Figure 1
Output Load Equivalent
PRELIMINARY
(February, 2005, Version 0.1)
Figure 2
Output Load Equivalent
13
AMIC Technology, Corp.
A67L16181/A67L06361 Series
SLEEP Mode
SLEEP Mode is a low current “Power-down” mode in which the
device is deselected and current is reduced to ISB2Z. This
duration of SLEEP Mode is dictated by the length of time the
ZZ is in a HIGH state. After entering SLEEP Mode, all inputs
except ZZ become disabled and all outputs go to High-Z.
The ZZ pin is asynchronous, active high input that causes the
device to enter SLEEP Mode. When the ZZ pin becomes
logic HIGH, ISB2Z is guaranteed after the time tZZI is met.
Any operation pending when entering SLEEP Mode is not
guaranteed to successfully complete. Therefore, SLEEP
Mode (READ or WRITE) must not be initiated until valid
pending operations are completed. Similarly, when exiting
SLEEP Mode during tRZZ, only a DESELECT or READ cycle
should be given while the SRAM is transitioning out of SLEEP
Mode.
SLEEP Mode Electrical Characteristics
(VCC, VCCQ = +3.3V±5%)
Symbol
ISB2Z
Parameter
Current during SLEEP Mode
Conditions
Min.
Max.
Unit
ZZ ≥ VIH
-
TBD
mA
Note
tZZ
ZZ active to input ignored
0
2(tKHKH)
ns
1
tRZZ
ZZ inactive to input sampled
0
2(tKHKH)
ns
1
tZZI
ZZ active to snooze current
-
2(tKHKH)
ns
1
tRZZI
ZZ inactive to exit snooze current
0
ns
1
Note : 1. This parameter is sampled.
SLEEP Mode Waveform
CLK
tZZ
tRZZ
ZZ
tZZI
I
SUPPLY
IISB2Z
tRZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Output
(Q)
High-Z
: Don't Care
PRELIMINARY
(February, 2005, Version 0.1)
14
AMIC Technology, Corp.
A67L16181/A67L06361 Series
READ/WRITE Timing
1
2
3
tKHKH
4
5
A3
A4
6
7
8
9
A5
A6
A7
10
CLK
tEVK
tKHE
H
X
tCVKH
tKHCX
tKHKL
tKLKH
CEN
CE
ADV/
LD
R/W
BWx
ADDRESS
A2
A1
tAVKH
tKHAX
tKHQV
tKHQX1
tDVKH
I/O
tKHQX
tGLQV
tKHDX
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
tKHQZ
D(A5)
Q(A4+1)
Q(A6)
D(A7)
tKHQX
tGHQZ
tGLQX
OE
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
BURST
READ
Q(A4+1)
READ
Q(A4)
WRITE
D(A5)
READ
Q(A6)
: Don't Care
WRITE
D(A7)
DESELECT
: Undefined
Note : 1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional.
3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The most
recent data may be from the input data register.
PRELIMINARY
(February, 2005, Version 0.1)
15
AMIC Technology, Corp.
A67L16181/A67L06361 Series
NOP, STALL and Deselect Cycles
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/
LD
R/W
BWx
ADDRESS
A5
tKHQZ
I/O
D(A1)
Q(A2)
Q(A3)
Q(A5)
D(A4)
tKHQX
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
: Don't Care
DESELECT
CONTINUE
DESELECT
: Undefined
Note : 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CEN being used to create a “pause.” A WRITE is not
performed during this cycle.
2. For this waveform, ZZ and OE are tied LOW.
3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
PRELIMINARY
(February, 2005, Version 0.1)
16
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Ordering Information
Part No.
Configure
Cycle Time / Access Time
A67L16181E-6.5
A67L16181E-7.5
7.5ns / 6.5ns
2M X 18
8.5ns / 7.5ns
A67L16181-8.5
10ns / 8.5ns
A67L06361E-6.5
7.5ns / 6.5ns
A67L06361E-7.5
1M X 36
8.5ns / 7.5ns
A67L06361E-8.5
PRELIMINARY
Package
(February, 2005, Version 0.1)
100L LQFP
100L LQFP
10ns / 8.5ns
17
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Package Information
LQFP 100L Outline Dimensions
unit: inches/mm
HE
A2
A1
D
E
80
51
50
100
31
1
L1
L
HD
D
81
y
30
b
e
c
θ
Symbol
A1
Dimensions in inches
Dimensions in mm
Min.
Nom.
Max.
Min.
Nom.
Max.
0.002
-
-
0.05
-
-
A2
0.053
0.055
0.057
1.35
1.40
1.45
b
0.011
0.013
0.015
0.27
0.32
0.37
c
0.005
-
0.008
0.12
-
0.20
HE
0.860
0.866
0.872
21.85
22.00
22.15
E
0.783
0.787
0.791
19.90
20.00
20.10
HD
0.624
0.630
0.636
15.85
16.00
16.15
D
0.547
0.551
0.555
13.90
14.00
14.10
e
L
0.026 BSC
0.018
L1
0.024
0.65 BSC
0.030
0.45
0.039 REF
0.60
0.75
1.00 REF
y
-
-
0.004
-
-
0.1
θ
0°
3.5°
7°
0°
3.5°
7°
Notes:
1. Dimensions D and E do not include mold protrusion.
2. Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
PRELIMINARY
(February, 2005, Version 0.1)
18
AMIC Technology, Corp.
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