STMicroelectronics L6932D2.5TR High performance 2a uldo linear regulator Datasheet

L6932
HIGH PERFORMANCE 2A ULDO LINEAR REGULATOR
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2V TO 14V INPUT VOLTAGE RANGE
200mΩ Rdson MAX.
200µA QUIESCENT CURRENT AT ANY LOAD
EXCELLENT LOAD AND LINE REGULATION
1.5V, 1.8V AND 2.5V FIXED VOLTAGE
ADJUSTABLE FROM 1.2V TO 5V (L6932D1.2)
1% VOLTAGE REGULATION ACCURACY
SHORT CIRCUIT PROTECTION
THERMAL SHUT DOWN
SO-8 (4+4) PACKAGE
APPLICATIONS
■ MOTHERBOARDS
SO-8 (4+4)
ORDERING NUMBERS:
L6932D1.2 (SO-8) L6932D1.2TR (T&R)
L6932D1.5 (SO-8) L6932D1.5TR (T&R)
L6932D1.8 (SO-8) L6932D1.8TR (T&R)
L6932D2.5 (SO-8) L6932D2.5TR (T&R)
Mosfet, can be usefull for the DC-DC conversion
between 2.5V and 1.5V at 2A in portable applications reducing the power dissipation.
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MOBILE PC
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HAND-HELD INSTRUMENTS
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PCMCIA CARDS
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PROCESSORS I/O
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CHIPSET AND RAM SUPPLY
L6932 is available in 1.5V, 1.8V, 2.5V and adj version from 1.2V and ensure a voltage regulation accuracy of 1%.
DESCRIPTION
The L6932 Ultra Low Drop Output linear regulator
operates from 2V to 14V and is able to support 2A.
Designed with an internal 50mΩ N-channel
The current limit is fixed at 2.5A to control the current in short circuit condition within ±8%. The current is sensed in the power mos in order to limit the
power dissipation.
The device is also provided of a thermal shut down
that limits the internal temperature at 150°C with
an histeresys of 20°C. L6932 provides the Enable
and the Power good functions.
TYPICAL OPERATING CIRCUIT
VIN
IN
3
2
VOUT
OUT
1.5V-1.8V-2.5V
2V to 14V
L6932D
C1
4
5,6,7,8
PGOOD
C2
1
GND
EN
VIN
IN
4
2
VOUT
OUT
1.2V to 5V
2V to 14V
R1
L6932D
C1
3
5,6,7,8
ADJ
C2
1
R2
GND
EN
December 2005
Rev. 9
1/11
L6932
PIN CONNECTIONS
EN
1
8
GND
EN
1
8
GND
IN
2
7
GND
IN
2
7
GND
ADJ
3
6
GND
OUT
3
6
GND
OUT
4
5
GND
PGOOD
4
5
GND
L6932D1.2
L6932D1.5
L6932D1.8
L6932D2.5
PIN FUNCTION
N°
L6232D
1.5/1.8/
2.5
L6232D
1.2
Description
1
EN
Enables the device if connected to Vin and disables the device if forced to gnd.
2
IN
Supply voltage. This pin is connected to the drain of the internal N-mos. Connect this
pin to a capacitor larger than 10µF.
ADJ
–
Connecting this pin to a voltage divider it is possible to programme the output voltage
between 1.2V and 5V.
–
OUT
Regulated output voltage. This pin is connected to the source of the internal N-mos.
Connect this pin to a capacitor of 10µF.
OUT
–
Regulated output voltage. This pin is connected to the source of the internal N-mos.
Connect this pin to a capacitor of 10µF.
3
4
–
5, 6, 7, 8
PGOOD Power good output. The pin is open drain and detects the output voltage. It is forced
low if the output voltage is lower than 90% of the programmed voltage.
GND
Ground pin.
ABSOLUTE MAXIMUM RATINGS
Symbol
Vin
Parameter
VIN and Pgood
EN, OUT and ADJ
Value
Unit
14.5
V
-0.3 to (Vin +0.3)
V
Value
Unit
62 (*)
°C/W
150
°C
-65 to 150
°C
THERMAL DATA
Symbol
Rth J-amb
Parameter
Thermal Resistance Junction to Ambient
Tmax
Maximum Junction Temperature
Tstg
Storage Temperature Range
(*) Measured on Demoboard with about 4 cm2 of dissipating area 2 Oz.
2/11
L6932
BLOCK DIAGRAM (Referred to the Fixed Voltage version)
IN
CHARGE
PUMP
VREF
REFERENCE
VREF=1.25V
EN
ENABLE
CURRENT
LIMIT
DRIVER
+
ERROR
AMPL.
OUT
THERMAL
SENSOR
PG
0.9 VREF
+
GND
D99IN1100
ELECTRICAL CHARACTERISTCS (Tj = 25°C, VIN = 5V unless otherwise specified)
(*) Specification referred to Tj from -25°C to 125°C.
Symbol
Parameter
Test Condition
Min.
Max.
Unit
14
V
1.2
1.212
V
1.485
1.5
1.515
V
1.782
1.8
1.818
V
2.475
2.5
2.525
V
5
mV
Vin = 3.3V ±10%; Io = 10mA
5
mV
Vin = 5V ±10%;
Vin
Operating Supply Voltage
Vo
Output voltage L6932D1.2
Io = 0.1A; Vin = 3.3V
1.188
Output voltage L6932D1.5
Io = 0.1A; Vin = 3.3V
Output voltage L6932D1.8
Io = 0.1A; Vin = 3.3V
Output voltage L6932D2.5
Io = 0.1A; Vin = 3.3V
L6932D1.2
Line Regulation
Vin = 2.5V ±10%; Io = 10mA
L6932D1.5
Line Regulation
L6932D1.8
Line Regulation
L6932D2.5
Line Regulation
Rdson
Typ.
2
Io = 10mA
5
mV
Vin = 2.5V ±10%; Io = 10mA
5
mV
Vin = 3.3V ±10%; Io = 10mA
5
mV
Vin = 5V ±10%;
Io = 10mA
5
mV
Vin = 2.5V ±10%; Io = 10mA
5
mV
Vin = 3.3V ±10%; Io = 10mA
5
mV
Vin = 5V ±10%;
Io = 10mA
5
mV
Vin = 3.3V ±10%; Io = 10mA
5
mV
Vin = 5V ±10%;
5
mV
L6932D1.2 Load Regulation
Vin = 3.3V; 0.1A < Io < 2A
15
mV
L6932D1.5 Load Regulation
Vin = 3.3V; 0.1A < Io < 2A
15
mV
L6932D1.8 Load Regulation
Vin = 3.3V; 0.1A < Io < 2A
15
mV
L6932D2.5 Load Regulation
Vin = 3.3V; 0.1A < Io < 2A
15
mV
200
mΩ
Drain Source ON resistance
Io = 10mA
3/11
L6932
ELECTRICAL CHARACTERISTCS (continued)
Symbol
Parameter
Iocc
Test Condition
Current limiting
Iq
Quiescent current
Ish
Shutdown current
2V < Vin < 14V
Ripple Rejection
f = 120Hz, Io = 1A
Vin = 5V, ∆Vin = 2Vpp
Ven
Typ.
Max.
Unit
2.3
2.5
2.7
A
0.2
0.4
mA
25
µA
*
EN Input Threshold
Pgood threshold
Min.
60
75
0.5
0.65
Vo rise
Pgood Hysteresis
Ipgood =1mA
Pgood saturation
Figure 1. Output Voltage vs. Junction
Temperature (L6932D1.2)
dB
0.8
V
90
%Vo
10
%Vo
0.2
0.4
V
Figure 3. Output Voltage vs. Junction
Temperature (L6932D2.5)
1.213
2.520
1.212
2.515
1.212
2.510
1.211
V
V
1.211
2.505
1.210
2.500
1.210
1.209
-60
-40
-20
0
20
40
60
80
2.495
100 120 140 160
-60 -40
-20
0
20
Temp [°C]
40
60
80
100 120 140 160
Temp [°C]
Figure 2. Output Voltage vs. Junction
Temperature (L6932D1.8)
Figure 4. Quiescent Current vs. Junction
Temperature
310
1.808
300
1.804
Vin=5V
290
1.800
Iq 280
V
1.796
(uA)
270
1.792
260
1.788
-60 -40 -20
4/11
0
20
40 60 80
Temp [°C]
100 120 140 160
250
-40
-20
0
20
40
60
Temp [°C ]
80
100
120
140
L6932
Figure 5. Shutdown Current vs. Junction TemperatureAPPLICATION INFORMATIONS
7.5
7
6.5
Ishdn
Vin=5V
6
(uA)
5.5
5
4.5
4
-40
-20
0
20
40
60
80
100
120
140
Temp [°C ]
APPLICATION CIRCUIT
In figure 6 the schematic circuit of the demoboards are shown.
Figure 6. Demoboards Schematic Circuit
VIN
VOUT
OUT
IN
2
EN
3
L6932D1.5
L6932D1.8
L6932D2.5
1
C1
6
5
7
4
PGOOD
C2
8
GND
VIN
IN
4
2
VOUT
OUT
1.2V to 5V
EN
R1
L6932D1.2
1
C1
3
6
5
7
ADJ
C2
VOUT =
8
R2
GND
1.2
× (R1+ R2)
R2
COMPONENT LIST
Fixed version
Reference
Part Number
Description
Manufacturer
C1
C34Y5U1E106Z
10uF, 25V
TOKIN
C2
C34Y5U1E106Z
10uF, 25V
TOKIN
5/11
L6932
Figure 7. Demoboard Layout (Fixed Version)
Adjustable version
Reference
Part Number
Description
Manufacturer
C1
C34Y5U1E106Z
10uF, 25V
TOKIN
C2
C34Y5U1E106Z
10uF, 25V
TOKIN
R1
5.6K, 1%, 0.25W
Neohm
R2
3.3K, 1%, 0.25W
Neohm
Figure 8. Demoboard Layout (Adjustable Version)
COMPONENTS SELECTION
Input Capacitor
The input capacitor value depends on a lot of factors such as load transient requirements, input source (battery
or DC/DC converter) and its distance from the input cap. Usually a 47µF is enough for any application but a
much lower value can be sufficient in many cases.
Output Capacitor
The output capacitor choice depends basically on the load transient requirements.
Tantalum, Speciality Polimer, POSCAP and aluminum capacitors are good and offer very low ESR values.
6/11
L6932
Multilayer ceramic caps have the lowest ESR and can be required for particular applications. Nevertheless in
several applications they are ok, the loop stability issue has to be considered (see loop stability section).
Below a list of some suggested capacitor manufacturers.
Manufacturer
Type
Cap Value (µF)
Rated Voltage (V)
PANASONIC
CERAMIC
1 to 47
4 to 16
TAYO YUDEN
CERAMIC
1 to 47
4 to 16
TDK
CERAMIC
1 to 47
4 to 16
TOKIN
CERAMIC
1 to 47
4 to 16
SANYO
POSCAP
1 to 47
4 to 16
PANASONIC
SP
1 to 47
4 to 16
KEMET
TANTALUM
1 to 47
4 to 16
Loop Stability
The stability of the loop is affected by the zero introduced by the output capacitor.
The time constant of the zero is given by:
T = ESR ⋅ C OUT
1
F ZERO = -------------------------------------------2π ⋅ ESR ⋅ C OUT
This zero helps to increase the phase margin of the loop until the time constant is higher than some hundreds
of nsec, depending also on the output voltage and current.
So, using very low ESR ceramic capacitors could produce oscillations at the output, in particular when regulating
high output voltages (adjustable version).
To solve this issue is sufficient to add a small capacitor (e.g. 1nF to 10nF) in parallel to the high side resistor of
the external divider, as shown in figure 9.
Figure 9. Compensation Network
VIN=2V TO 14V
IN
OUT
2
R1
L6932D1.2
EN
C1
VOUT=1.2V TO 5V
UP to 2A
4
C3
ADJ
1
5
6
GND
7
3
8
C2
R2
Thermal Considerations
Since the device is housed in a small SO(4+2+2) package the thermal issue can be the bottleneck of many applications. The power dissipated by the device is given by:
PDISS = (VIN - VOUT) · IOUT
7/11
L6932
The thermal resistance junction to ambient of the demoboard is approximately 62°C/W. This mean that, considering an ambient temperature of 60°C and a maximum junction temperature of 150°C, the maximum power that
the device can handle is 1.5W.
This means that the device is able to deliver a DC output current of 2A only with a very low dropout.
In many applications, high output current pulses are required. If their duration is shorter than the thermal constant time of the board, the thermal impedance (not the thermal resistance) has to be considered.
In figure 10 the thermal impedance versus the duration of the current pulse for the SO(4+2+2) mounted on board
is shown.
Figure 10. Thermal Impedance
Considering a pulse duration of 1sec, the thermal impedance is close to 20°C/W, allowing much bigger power
dissipated.
Example:
Vin = 3.3V
Vout = 1.8V
Iout = 2A
Pulse Duration = 1sec
The power dissipated by the device is:
PDISS = (VIN - VOUT) · IOUT = 1.5 · 2 3W
Considering a thermal impedance of 20°C/W, the maximum junction temperature will be:
TJ = TA + ZTHJA · PDISS = 60 + 60 = 120°C
Obviously, with pulse durations longer than approximately 10sec the thermal impedance is very close to the
thermal resistance (60°C/W to 70°C/W).
8/11
L6932
Figure 11. SO-8 Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D (1)
4.80
5.00
0.189
0.197
E
3.80
4.00
0.15
0.157
e
1.27
0.050
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
k
ddd
OUTLINE AND
MECHANICAL DATA
0˚ (min.), 8˚ (max.)
0.10
0.004
Note: (1) Dimensions D does not include mold flash, protrusions or gate burrs.
Mold flash, potrusions or gate burrs shall not exceed
0.15mm (.006inch) in total (both side).
SO-8
0016023 C
9/11
L6932
Table 1. Revision History
Date
Revision
February 2003
8
First Issue
December 2005
9
Added new Ordering Numbers: L6932D1.5 & L6932D1.5TR.
10/11
Description of Changes
L6932
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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