ONSEMI NUD3160DMT1G

NUD3160
Industrial Inductive
Load Driver
This MicroIntegrationt part provides a single component solution
to switch inductive loads such as relays, solenoids, and small DC
motors without the need of a free−wheeling diode. It accepts logic
level inputs, thus allowing it to be driven by a large variety of devices
including logic gates, inverters, and microcontrollers.
http://onsemi.com
MARKING DIAGRAMS
Features
3
• Provides Robust Interface between D.C. Relay Coils and Sensitive
1
Logic
2
• Capable of Driving Relay Coils Rated up to 150 mA at 12 V, 24 V
•
•
•
•
JW8 MG
G
JW8 = Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
or 48 V
Replaces 3 or 4 Discrete Components for Lower Cost
Internal Zener Eliminates Need for Free−Wheeling Diode
Meets Load Dump and other Automotive Specs
Pb−Free Packages are Available
SC−74
CASE 318F
STYLE 7
6
Typical Applications
1
• Automotive and Industrial Environment
• Drives Window, Latch, Door, and Antenna Relays
JW8 MG
G
JW8 = Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
Benefits
•
•
•
•
SOT−23
CASE 318
STYLE 21
Reduced PCB Space
Standardized Driver for Wide Range of Relays
Simplifies Circuit Design and PCB Layout
Compliance with Automotive Specifications
ORDERING INFORMATION
Device
NUD3160LT1
NUD3160LT1G
NUD3160DMT1
Package
Shipping†
SOT−23
SOT−23
(Pb−Free)
3000/Tape & Reel
SC−74
3000/Tape & Reel
SC−74
NUD3160DMT1G
(Pb−Free)
3000/Tape & Reel
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Drain (3)
Gate (1)
Gate (2)
10 k
100 k
Drain (3)
Drain (6)
10 k
10 k
100 k
100 k
Source (2)
Source (4)
Source (1)
CASE 318
Gate (5)
CASE 318F
Figure 1. Internal Circuit Diagrams
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 2
1
Publication Order Number:
NUD3160/D
NUD3160
MAXIMUM RATINGS (TJ = 25°C unless otherwise specified)
Rating
Symbol
Value
Unit
VDSS
Drain−to−Source Voltage – Continuous
(TJ = 125°C)
60
V
VGSS
Gate−to−Source Voltage – Continuous
(TJ = 125°C)
12
V
ID
Drain Current – Continuous
(TJ = 125°C)
150
mA
EZ
Single Pulse Drain−to−Source Avalanche Energy
(For Relay’s Coils/Inductive Loads of 80 W or Higher)
(TJ Initial = 85°C)
200
mJ
PPK
Peak Power Dissipation, Drain−to−Source (Notes 1 and 2)
(TJ Initial = 85°C)
20
W
ELD1
Load Dump Pulse, Drain−to−Source (Note 3)
RSOURCE = 0.5 W, T = 300 ms)
(For Relay’s Coils/Inductive Loads of 80 W or Higher)
(TJ Initial = 85°C)
60
V
ELD2
Inductive Switching Transient 1, Drain−to−Source
(Waveform: RSOURCE = 10 W, T = 2.0 ms)
(For Relay’s Coils/Inductive Loads of 80 W or Higher)
(TJ Initial = 85°C)
100
V
ELD3
Inductive Switching Transient 2, Drain−to−Source
(Waveform: RSOURCE = 4.0 W, T = 50 ms)
(For Relay’s Coils/Inductive Loads of 80 W or Higher)
(TJ Initial = 85°C)
300
V
Rev−Bat
Reverse Battery, 10 Minutes (Drain−to−Source)
(For Relay’s Coils/Inductive Loads of 80 W or more)
−14
V
Dual−Volt
Dual Voltage Jump Start, 10 Minutes (Drain−to−Source)
28
V
2000
V
Value
Unit
ESD
Human Body Model (HBM)
According to EIA/JESD22/A114 Specification
THERMAL CHARACTERISTICS
Symbol
TA
Operating Ambient Temperature
−40 to 125
°C
TJ
Maximum Junction Temperature
150
°C
−65 to 150
°C
TSTG
Storage Temperature Range
PD
Total Power Dissipation (Note 4)
Derating above 25°C
SOT−23
225
1.8
mW
mW/°C
PD
Total Power Dissipation (Note 4)
Derating above 25°C
SC−74
380
3.0
mW
mW/°C
SOT−23
SC−74
556
329
°C/W
RqJA
1.
2.
3.
4.
Rating
Thermal Resistance Junction–to–Ambient (Note 4)
Nonrepetitive current square pulse 1.0 ms duration.
For different square pulse durations, see Figure 12.
Nonrepetitive load dump pulse per Figure 3.
Mounted onto minimum pad board.
http://onsemi.com
2
NUD3160
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Symbol
Min
Typ
Max
Unit
VBRDSS
61
66
70
V
−
−
−
−
−
−
−
−
0.5
1.0
50
80
−
−
−
−
−
−
−
−
60
80
90
110
1.3
1.3
1.8
−
2.0
2.0
−
−
−
−
−
−
−
−
2.4
3.7
1.8
2.9
150
100
200
−
−
−
gFS
−
400
−
mmho
Input Capacitance
(VDS = 12 V, VGS = 0 V, f = 10 kHz)
Ciss
−
30
−
pf
Output Capacitance
(VDS = 12 V, VGS = 0 V, f = 10 kHz)
Coss
−
14
−
pf
Transfer Capacitance
(VDS = 12 V, VGS = 0 V, f = 10 kHz)
Crss
−
6.0
−
pf
tPHL
tPLH
−
−
918
798
−
−
tPHL
tPLH
−
−
331
1160
−
−
tf
tr
−
−
2290
618
−
−
tf
tr
−
−
622
600
−
−
Characteristic
OFF CHARACTERISTICS
Drain to Source Sustaining Voltage
(ID = 10 mA)
Drain to Source Leakage Current
(VDS = 12 V, VGS = 0 V)
(VDS = 12 V, VGS = 0 V, TJ = 125°C)
(VDS = 60 V, VGS = 0 V)
(VDS = 60 V, VGS = 0 V, TJ = 125°C)
IDSS
Gate Body Leakage Current
(VGS = 3.0 V, VDS = 0 V)
(VGS = 3.0 V, VDS = 0 V, TJ = 125°C)
(VGS = 5.0 V, VDS = 0 V)
(VGS = 5.0 V, VDS = 0 V, TJ = 125°C)
IGSS
mA
mA
ON CHARACTERISTICS
Gate Threshold Voltage
(VGS = VDS, ID = 1.0 mA)
(VGS = VDS, ID = 1.0 mA, TJ = 125°C)
VGS(th)
Drain to Source On−Resistance
(ID = 150 mA, VGS = 3.0 V)
(ID = 150 mA, VGS = 3.0 V, TJ = 125°C)
(ID = 150 mA, VGS = 5.0 V)
(ID = 150 mA, VGS = 5.0 V, TJ = 125°C)
RDS(on)
Output Continuous Current
(VDS = 0.3 V, VGS = 5.0 V)
(VDS = 0.3 V, VGS = 5.0 V, TJ = 125°C)
IDS(on)
Forward Transconductance
(VDS = 12 V, ID = 150 mA)
V
W
mA
DYNAMIC CHARACTERISTICS
SWITCHING CHARACTERISTICS
Propagation Delay Times:
High to Low Propagation Delay; Figure 2, (VDS = 12 V, VGS = 3.0 V)
Low to High Propagation Delay; Figure 2, (VDS = 12 V, VGS = 3.0 V)
High to Low Propagation Delay; Figure 2, (VDS = 12 V, VGS = 5.0 V)
Low to High Propagation Delay; Figure 2, (VDS = 12 V, VGS = 5.0 V)
Transition Times:
Fall Time; Figure 2, (VDS = 12 V, VGS = 3.0 V)
Rise Time; Figure 2, (VDS = 12 V, VGS = 3.0 V)
ns
ns
Fall Time; Figure 2, (VDS = 12 V, VGS = 5.0 V)
Rise Time; Figure 2, (VDS = 12 V, VGS = 5.0 V)
http://onsemi.com
3
NUD3160
TYPICAL WAVEFORMS
(TJ = 25°C unless otherwise specified)
VIH
Vin
50%
0V
tPHL
tPLH
VOH
90%
Vout
50%
10%
VOL
tr
tf
Figure 2. Switching Waveforms
tr
Load Dump Pulse Not Suppressed:
Vr = 13.5 V Nominal ±10%
VS = 60 V Nominal ±10%
T = 300 ms Nominal ±10%
tr = 1 − 10 ms ±10%
90%
10% of Peak;
Reference = Vr, Ir
10%
Vr, Ir
Figure 3. Load Dump Waveform Definition
http://onsemi.com
4
VS
T
NUD3160
TYPICAL PERFORMANCE CURVES
(TJ = 25°C unless otherwise specified)
80
VDS = 60 V
70
IGSS GATE LEAKAGE (mA)
IDSS, DRAIN LEAKAGE (mA)
80
60
50
40
30
20
10
0
−50
−25
0
25
50
100
75
VGS = 5 V
50
40
VGS = 3 V
30
−25
100
75
Figure 5. Gate−to−Source Leakage vs.
Junction Temperature
125
1E+03
VGS = 5 V
ID = 10 mA
65.8
65.6
65.4
65.2
VGS = 2.5 V
VGS = 3 V
1E+02
VGS = 2 V
1E+01
1E+00
1E−01
VGS = 1.5 V
1E−02
65.0
−25
0
25
75
50
100
1E−03
0.0
125
0.1
TJ, JUNCTION TEMPERATURE (°C)
0.1
0.01
0.001
125 °C
1E−04
1E−05
1.2
1.4
−40 °C
1.6
1.8
2.0
2.2
2.4
VGS, GATE−TO−SOURCE VOLTAGE (V)
2.6
RDS(ON), DRAIN−TO−SOURCE RESISTANCE (mW)
VDS = 0.8 V
25 °C
0.3
0.4
0.5
0.6
0.7
0.8
Figure 7. Output Characteristics
1
85 °C
0.2
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 6. Breakdown Voltage vs.
Junction Temperature
ID DRAIN CURRENT (mA)
50
Figure 4. Drain−to−Source Leakage vs.
Junction Temperature
66.0
1E−07
1.0
25
TJ, JUNCTION TEMPERATURE (°C)
66.2
1E−06
0
TJ, JUNCTION TEMPERATURE (°C)
ID DRAIN CURRENT (mA)
BVDSS BREAKDOWN VOLTAGE (V)
60
20
−50
125
66.4
64.8
−50
70
3200
ID = 0.15 A
2800
2400
VGS = 3.0 V
2000
1600
VGS = 5.0 V
1200
800
−50
Figure 8. Transfer Function
−25
0
25
50
75
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. On Resistance Variation vs
Junction Temperature
http://onsemi.com
5
100
125
NUD3160
TYPICAL PERFORMANCE CURVES
100
ID = 250 mA
125 °C
VZ ZENER CLAMP VOLTAGE (V)
90
80
70
60
85 °C
50
25 °C
40
30
−40 °C
20
10
0
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
68.0
67.5
67.0
66.5
−40 °C
66.0
65.5
25 °C
85 °C
65.0
64.5
64.0
63.5
63.0
62.5
62.0
0.1
125 °C
1.0
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
Figure 11. Zener Clamp Voltage vs. Zener
Current
100
10
1
0.1
100
IZ, ZENER CURRENT (mA)
Figure 10. On Resistance Variation vs.
Gate−to−Source Voltage
POWER (WATTS)
RDS(ON), DRAIN−TO−SOURCE RESISTANCE (mW)
(TJ = 25°C unless otherwise specified)
1.0
10
PW, PULSE WIDTH (ms)
Figure 12. Maximum Non−repetitive Surge
Power vs. Pulse Width
http://onsemi.com
6
100
1000
NUD3160
APPLICATIONS INFORMATION
12 V Battery
−
+
NC
NO
Relay, Vibrator,
or
Inductive Load
Drain (3)
Gate (1)
Micro
Processor
Signal
for
Relay
10 k
100 K
NUD3160
Source (2)
Figure 13. Applications Diagram
http://onsemi.com
7
NUD3160
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AN
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. 318−01 THRU −07 AND −09 OBSOLETE, NEW
STANDARD 318−08.
D
SEE VIEW C
3
HE
E
c
1
DIM
A
A1
b
c
D
E
e
L
L1
HE
2
b
0.25
e
q
A
L
A1
MIN
0.89
0.01
0.37
0.09
2.80
1.20
1.78
0.10
0.35
2.10
MILLIMETERS
NOM
MAX
1.00
1.11
0.06
0.10
0.44
0.50
0.13
0.18
2.90
3.04
1.30
1.40
1.90
2.04
0.20
0.30
0.54
0.69
2.40
2.64
STYLE 21:
PIN 1. GATE
2. SOURCE
3. DRAIN
L1
VIEW C
SOLDERING FOOTPRINT*
0.95
0.037
0.95
0.037
2.0
0.079
0.9
0.035
0.8
0.031
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
8
MIN
0.035
0.001
0.015
0.003
0.110
0.047
0.070
0.004
0.014
0.083
INCHES
NOM
0.040
0.002
0.018
0.005
0.114
0.051
0.075
0.008
0.021
0.094
MAX
0.044
0.004
0.020
0.007
0.120
0.055
0.081
0.012
0.029
0.104
NUD3160
PACKAGE DIMENSIONS
SC−74
CASE 318F−05
ISSUE L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. 318F−01, −02, −03 OBSOLETE. NEW
STANDARD 318F−04.
D
6
5
4
2
3
E
HE
1
DIM
A
A1
b
c
D
E
e
L
HE
q
b
e
C
A
0.05 (0.002)
q
L
A1
MIN
0.90
0.01
0.25
0.10
2.90
1.30
0.85
0.20
2.50
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.37
0.50
0.18
0.26
3.00
3.10
1.50
1.70
0.95
1.05
0.40
0.60
2.75
3.00
10°
−
MIN
0.035
0.001
0.010
0.004
0.114
0.051
0.034
0.008
0.099
0°
INCHES
NOM
0.039
0.002
0.015
0.007
0.118
0.059
0.037
0.016
0.108
−
MAX
0.043
0.004
0.020
0.010
0.122
0.067
0.041
0.024
0.118
10°
STYLE 7:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
SOLDERING FOOTPRINT*
2.4
0.094
0.95
0.037
1.9
0.074
0.95
0.037
0.7
0.028
1.0
0.039
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MicroIntegration is a trademark of Semiconductor Components Industries, LLC (SCILLC)
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
9
For additional information, please contact your
local Sales Representative.
NUD3160/D