AD ADG1211 Low capacitance, low charge injection, â±15 v/12 v icmos quad spst switch Datasheet

FUNCTIONAL BLOCK DIAGRAM
FEATURES
1 pF off capacitance
2.6 pF on capacitance
<1 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at ±15 V, +12 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead LFCSP
Typical power consumption: <0.03 µW
S1
IN1
GENERAL DESCRIPTION
The ADG1211/ADG1212/ADG1213 are monolithic complementary metal-oxide semiconductor (CMOS) devices containing
four independently selectable switches designed on an iCMOS®
(industrial CMOS) process. iCMOS is a modular manufacturing
process combining high voltage CMOS and bipolar technologies.
It enables the development of a wide range of high performance
analog ICs capable of 33 V operation in a footprint that no
previous generation of high voltage parts has been able to achieve.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can tolerate high supply voltages while providing
increased performance, dramatically lower power consumption,
and reduced package size.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-andhold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the parts suitable for video signal switching.
D1
S2
S2
IN2
ADG1211
D2
IN3
ADG1212
S2
D2
D2
ADG1213
S3
IN3
S3
IN3
D3
D3
S4
S4
IN4
IN4
D1
IN2
S3
D3
S4
IN4
D4
D4
SWITCHES SHOWN FOR A LOGIC 1 INPUT
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
IN1
D1
IN2
S1
S1
IN1
D4
04778-001
Data Sheet
Low Capacitance, Low Charge Injection,
±15 V/+12 V iCMOS Quad SPST Switches
ADG1211/ADG1212/ADG1213
Figure 1.
iCMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and batterypowered instruments.
The ADG1211/ADG1212/ADG1213 contain four independent
single-pole/single-throw (SPST) switches. The ADG1211 and
ADG1212 differ only in that the digital control logic is inverted.
The ADG1211 switches are turned on with Logic 0 on the
appropriate control input, while Logic 1 is required for the
ADG1212. The ADG1213 has two switches with digital control
logic similar to that of the ADG1211; the logic is inverted on
the other two switches. The ADG1213 exhibits break-beforemake switching action for use in multiplexer applications.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
Ultralow capacitance.
<1 pC charge injection.
3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
No VL logic power supply required.
Ultralow power dissipation: <0.03 µW.
16-lead TSSOP and 3 mm × 3 mm LFCSP packages.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2012 Analog Devices, Inc. All rights reserved.
ADG1211/ADG1212/ADG1213
Data Sheet
TABLE OF CONTENTS
Specifications..................................................................................... 3
Terminology .......................................................................................8
Dual Supply ................................................................................... 3
Typical Performance Characteristics ..............................................9
Single Supply ................................................................................. 5
Test Circuits ..................................................................................... 12
Absolute Maximum Ratings............................................................ 6
Outline Dimensions ....................................................................... 14
ESD Caution .................................................................................. 6
Ordering Guide .......................................................................... 15
Pin Configurations and Function Descriptions ........................... 7
REVISION HISTORY
8/12—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Change to Table 6 ............................................................................. 7
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
2/09—Rev. 0 to Rev. A
Changes to Power Requirements, IDD, Digital Inputs = 5 V
Parameter, Table 1............................................................................. 4
Changes to Power Requirements, IDD, Digital Inputs = 5 V
Parameter, Table 2............................................................................. 5
7/05—Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet
ADG1211/ADG1212/ADG1213
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
25°C
Y Version 1
−40°C to
+85°C
−40°C to
+125°C
VDD to VSS
120
190
2.5
6
20
57
230
260
10
11
72
79
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VS = ±10 V, IS = −1 mA; see Figure 20
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
Ω max
Ω typ
Ω max
VS = −5 V/0 V/+5 V; IS = −1 mA
nA typ
VS = ±10 V, VD = ∓10 V; see Figure 21
VS = ±10 V, VD = ∓10 V; see Figure 21
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
±0.02
±0.1
±0.02
±0.6
±1
Drain Off Leakage, ID (Off)
nA max
nA typ
±0.1
±0.02
±0.1
±0.6
±1
VS = VD = ±10 V; see Figure 22
±0.6
±1
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
VIN = VINL or VINH
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 23
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 23
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 24
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF; see Figure 28
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
VDD = +16.5 V, VSS = −16.5 V
2.0
0.8
0.005
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
tON
tOFF
Break-Before-Make Time Delay, tD
(ADG1213 Only)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
CS (Off)
CD (Off)
CD, CS (On)
2.5
110
130
85
115
25
160
195
130
150
10
−0.3
80
90
0.15
1000
0.9
1.1
1
1.2
2.6
3
Rev. B | Page 3 of 16
ADG1211/ADG1212/ADG1213
Parameter
POWER REQUIREMENTS
IDD
25°C
Data Sheet
Y Version 1
−40°C to
+85°C
−40°C to
+125°C
0.001
1.0
IDD
220
380
ISS
0.001
1.0
ISS
0.001
VDD/VSS
1
2
1.0
±4.5/±16.5
Temperature range for Y version is −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. B | Page 4 of 16
Unit
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
V min/max
Test Conditions/Comments
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Data Sheet
ADG1211/ADG1212/ADG1213
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
Y Version 1
−40°C to
+85°C
−40°C to
+125°C
0 V to VDD
300
475
4.5
12
60
±0.02
±0.1
±0.02
±0.1
±0.02
±0.1
567
625
26
27
±0.6
±1
±0.6
±1
±0.6
±1
2.0
0.8
0.001
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
tON
tOFF
Break-Before-Make Time Delay, tD
(ADG1213 Only)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
3
130
170
95
120
50
210
240
145
180
10
0
80
90
900
1.2
1.4
1.3
1.5
3.2
3.9
0.001
1.0
IDD
220
VDD
1
2
1.0
5/165
Temperature range for Y version is −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. B | Page 5 of 16
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −1 mA; see Figure 20
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
µA typ
µA max
µA typ
µA max
V min/max
VS = 3 V/6 V/9 V, IS = −1 mA
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 21
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 21
VS = VD = 1 V or 10 V; see Figure 22
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 23
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 23
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 24
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
RL = 50 Ω, CL = 5 pF; see Figure 28
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
VSS = 0 V, GND = 0 V
ADG1211/ADG1212/ADG1213
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs 1
Digital Inputs1
Peak Current, S or D
Continuous Current per
Channel, S or D
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
16-Lead TSSOP, θJA Thermal
Impedance (4-Layer Board)
16-Lead LFCSP, θJA Thermal
Impedance
Reflow Soldering Peak
Temperature, Pb free
1
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS – 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND – 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
100 mA (pulsed at 1 ms,
10% duty cycle max)
25 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating may be applied at any one
time.
Table 4. ADG1211/ADG1212 Truth Table
ADG1211 INx
0
1
−40°C to +125°C
−65°C to +150°C
150°C
112°C/W
ADG1212 INx
1
0
Switch Condition
On
Off
Table 5. ADG1213 Truth Table
72.7°C/W
ADG1213 INx
0
1
260°C
Switch 1, 4
Off
On
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 6 of 16
Switch 2, 3
On
Off
Data Sheet
ADG1211/ADG1212/ADG1213
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN2
S1 1
D1
2
15
D2
VSS 2
S1
3
14
S2
VSS
4
GND
5
S4
6
D4
IN4
12
NC
11
S3
7
10
D3
8
9
IN3
TOP VIEW
NC = NO CONNECT
Mnemonic
IN1
D1
S1
VSS
GND
S4
D4
IN4
IN3
D3
S3
NC
VDD
S2
D2
IN2
14 IN2
NC = NO CONNECT
Figure 3. LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
LFCSP
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
9 S3
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
Figure 2. TSSOP Pin Configuration
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
13 D2
TOP VIEW
(Not to Scale)
S4 4
12 S2
11 VDD
10 NC
Description
Logic Control Input.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
Logic Control Input.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
No Internal Connection.
Most Positive Power Supply Potential.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
Rev. B | Page 7 of 16
04778-003
VDD
GND 3
D4 5
13
04788-002
ADG1211/
ADG1212/
ADG1213
PIN 1
INDICATOR
D3 8
16
IN3 7
1
IN4 6
IN1
15 IN1
16 D1
ADG1211/ADG1212/ADG1213
ADG1211/ADG1212/ADG1213
Data Sheet
TERMINOLOGY
IDD
The positive supply current.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
ISS
The negative supply current.
CIN
The digital input capacitance.
VD (VS)
The analog voltage on Terminals D and S.
tON
The delay between applying the digital control input and the
output switching on. See Figure 23.
RON
The ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.
ID, IS (On)
The channel leakage current with the switch on.
VINL
The maximum input voltage for Logic 0.
VINH
The minimum input voltage for Logic 1.
IINL (IINH)
The input current of the digital input.
CS (Off)
The off switch source capacitance, measured with reference
to ground.
tOFF
The delay between applying the digital control input and the
output switching off. See Figure 23.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
CD (Off)
The off switch drain capacitance, measured with reference
to ground.
Rev. B | Page 8 of 16
Data Sheet
ADG1211/ADG1212/ADG1213
TYPICAL PERFORMANCE CHARACTERISTICS
200
250
VDD = +15V
VSS = –15V
TA = +25°C
180
VDD = +13.5V
VSS = –13.5V
200
140
ON RESISTANCE (Ω)
120
100
VDD = +15V
VSS = –15V
80
VDD = +16.5V
VSS = –16.5V
60
40
TA = +125°C
150
TA = +85°C
100
04778-008
50
20
0
–18 –15 –12
–9 –6
–3
0
3
6
9
SOURCE OR DRAIN VOLTAGE (V)
12
15
0
–15
18
Figure 4. On Resistance as a Function of VD (VS) for Dual Supply
–10
–5
0
5
SOURCE OR DRAIN VOLTAGE (V)
10
15
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
450
600
TA = +25°C
VDD = +12V
VSS = 0V
400
TA = +125°C
500
350
TA = +85°C
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
TA = +25°C
TA = –40°C
04778-006
ON RESISTANCE (Ω)
160
VDD = +5.5V
VSS = –5.5V
300
250
200
150
400
300
200
TA = –40°C
100
TA = +25°C
50
0
–5
–4
–3
–2
–1
0
1
2
3
SOURCE OR DRAIN VOLTAGE (V)
4
04778-007
04778-004
100
0
0
5
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
4
6
8
SOURCE OR DRAIN VOLTAGE (V)
10
12
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
0.20
450
TA = 25°C
400
ID, IS (ON)
0.10
LEAKAGE (nA)
300
250
VDD = 13.2V
VSS = 0V
200
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
0.15
VDD = 12V
VSS = 0V
VDD = 10.8V
VSS = 0V
350
0.05
ID (OFF)
0
–0.05
IS (OFF)
150
–0.10
100
50
0
0
2
4
6
8
10
SOURCE OR DRAIN VOLTAGE (V)
–0.20
0
12
Figure 6. On Resistance as a Function of VD (VS) for Single Supply
04778-012
–0.15
04778-005
ON RESISTANCE (Ω)
2
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 9. Leakage Currents as a Function of Temperature, Dual Supply
Rev. B | Page 9 of 16
ADG1211/ADG1212/ADG1213
Data Sheet
0.30
200
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
0.25
180
12V SS TON
160
0.20
140
TIME (ns)
LEAKAGE (nA)
ID, IS (ON)
0.15
0.10
IS (OFF)
0.05
120
15V DS TON
100
80
12V SS TOFF
60
0
40
–0.10
0
20
40
60
80
TEMPERATURE (°C)
100
15V DS TOFF
20
0
–40
120
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 13. TON/TOFF Times vs. Temperature
Figure 10. Leakage Currents as a Function of Temperature, Single Supply
0
60
IDD PER CHANNEL
TA = +25°C
VDD = +15V
VSS = –15V
TA = +25°C
–10
50
OFF ISOLATION (dB)
–20
VDD = +15V, VSS = –15V
40
IDD (µA)
04778-016
04778-013
ID (OFF)
–0.05
30
20
–30
–40
–50
–60
–70
–80
04778-011
10
0
0
2
4
6
8
LOGIC, INX (V)
10
12
–100
–110
10k
14
6
1M
10M
FREQUENCY (Hz)
100M
1G
0
SOURCE TO DRAIN
DRAIN TO SOURCE
TA = +25°C
–10
–20
VDD = +15V
VSS = –15V
TA = +25°C
–30
0
CROSSTALK (dB)
2
VDD = +5V, VSS = –5V
VDD = +12V, VSS = 0V
–2
–40
–50
–60
–70
–80
–90
–6
–15
VDD = +15V, VSS = –15V
–10
–5
0
VS (V)
–100
5
10
04778-018
–4
04778-015
CHARGE INJECTION (pC)
100k
Figure 14. Off Isolation vs. Frequency
Figure 11. IDD vs. Logic Level
4
04778-017
–90
VDD = +12V, VSS = 0V
–110
–120
10k
15
Figure 12. Charge Injection vs. Source Voltage
100k
1M
FREQUENCY (Hz)
10M
Figure 15. Crosstalk vs. Frequency
Rev. B | Page 10 of 16
100M
Data Sheet
ADG1211/ADG1212/ADG1213
0
–5
3.0
VDD = +15V
VSS = –15V
TA = +25°C
SOURCE/DRAIN ON
VDD = +15V
VSS = –15V
TA = +25°C
CAPACITANCE (pF)
ATTENUATIOIN (dB)
2.5
–10
–15
–20
2.0
1.5
DRAIN OFF
1.0
–25
100k
1M
10M
100M
FREQUENCY (Hz)
1G
0.5
–10
10G
–8
–6
–4
04778-031
04778-019
–30
10k
SOURCE OFF
–2
0
2
VBIAS (V)
4
6
8
10
Figure 18. Capacitance vs. Source Voltage, Dual Supply
Figure 16. On Response vs. Frequency
10.00
4.0
LOAD = +10kΩ
TA = +25°C
VDD = 12V
VSS = 0V
TA = 25°C
3.5
SOURCE/DRAIN ON
CAPACITANCE (pF)
3.0
THD+N (%)
VDD = +5V, VSS = –5V, VS = +3.5Vrms
VDD = +15V, VSS = –15V, VS = +5Vrms
0.01
10
100
1k
FREQUENCY (Hz)
10k
2.0
1.5
DRAIN OFF
1.0
SOURCE OFF
0.5
04778-029
0.10
2.5
04778-030
1.00
0
100k
0
Figure 17. THD + N vs. Frequency
2
4
6
VBIAS (V)
8
10
Figure 19. Capacitance vs. Source Voltage, Single Supply
Rev. B | Page 11 of 16
12
ADG1211/ADG1212/ADG1213
Data Sheet
TEST CIRCUITS
IDS
V1
VD
Figure 20. On Resistance
A
VD
Figure 22. On Leakage
VSS
0.1µF
0.1µF
VSS
VDD
S
VS
NC = NO CONNECT
Figure 21. Off Leakage
VDD
D
VIN
ADG1212
50%
50%
VIN
ADG1211
50%
50%
VOUT
D
CL
35pF
RL
300Ω
IN
90%
VOUT
90%
GND
tOFF
tON
Figure 23. Switching Times
VDD
VSS
VSS
S1
D1
S2
D2
RL
300Ω
IN1,
IN2
CL
35pF
RL
300Ω
VOUT2
CL
35pF
VOUT1
VOUT1
50%
90%
90%
0V
90%
VOUT2
90%
0V
ADG1213
tD
GND
tD
Figure 24. Break-Before-Make Time Delay
RS
VS
VDD
VSS
VDD
VSS
S
D
VIN
CL
1nF
IN
GND
ADG1212
ON
VOUT
VIN
OFF
ADG1211
VOUT
QINJ = CL × DVOUT
Figure 25. Charge Injection
Rev. B | Page 12 of 16
DVOUT
04778-025
VS2
50%
0V
04778-024
VDD
VS1
VIN
0.1µF
0.1µF
04778-022
VS
S
NC
A
04778-023
RON = V1/IDS
D
04778-021
VS
S
A
ID (ON)
ID (OFF)
IS (OFF)
D
04778-020
S
Data Sheet
ADG1211/ADG1212/ADG1213
VSS
VDD
0.1µF
VDD
NETΩORK
ANALYZER
VSS
S
0.1µF
VDD
50Ω
IN
VS
VS
D
D
VIN
RL
50Ω
GND
VOUT
VIN
RL
50Ω
04778-026
GND
OFF ISOLATION = 20 LOG
VOUT
VS
INSERTION LOSS = 20 LOG
Figure 26. Off Isolation
VDD
VOUT
RL
50W
VOUT
VOUT ΩITH SΩITCH
VOUT ΩITHOUT SΩITCH
Figure 28. Bandwidth
VSS
VDD
0.1µF
0.1µF
NETWORK
ANALYZER
NETΩORK
ANALYZER
VSS
S
50Ω
50Ω
IN
VSS
0.1µF
04778-028
VDD
0.1µF
VDD
VSS
0.1µF
0.1µF
AUDIO PRECISION
VSS
VDD
VSS
RS
S1
S
D
S2
IN
R
50W
VS
V p-p
D
VS
VIN
GND
VOUT
VS
Figure 27. Channel-to-Channel Crosstalk
Figure 29. THD + Noise
Rev. B | Page 13 of 16
VOUT
04778-032
GND
04778-027
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
RL
10kΩ
ADG1211/ADG1212/ADG1213
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.65
BSC
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
0.60 MAX
3.00
BSC SQ
BOTTOM VIEW
13
12
0.45
TOP
VIEW
2.75
BSC SQ
0.80 MAX
0.65 TYP
12° MAX
SEATING
PLANE
0.05 MAX
0.02 NOM
0.30
0.23
0.18
1
*1.65
1.50 SQ
1.35
EXPOSED
PAD
0.50
BSC
0.90
0.85
0.80
16
PIN 1
INDICATOR
9
4
8
5
0.25 MIN
1.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 31. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
Rev. B | Page 14 of 16
07-17-2008-A
PIN 1
INDICATOR
0.50
0.40
0.30
Data Sheet
ADG1211/ADG1212/ADG1213
ORDERING GUIDE
Model 1
ADG1211YRUZ
ADG1211YRUZ-REEL
ADG1211YRUZ-REEL7
ADG1211YCPZ-500RL7
ADG1211YCPZ-REEL7
ADG1212YRUZ
ADG1212YRUZ-REEL
ADG1212YRUZ-REEL7
ADG1212YCPZ-500RL7
ADG1212YCPZ-REEL7
ADG1213YRUZ
ADG1213YRUZ-REEL
ADG1213YRUZ-REEL7
ADG1213YCPZ-500RL7
ADG1213YCPZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP_VQ)
Lead Frame Chip Scale Package (LFCSP_VQ)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP_VQ)
Lead Frame Chip Scale Package (LFCSP_VQ)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP_VQ)
Lead Frame Chip Scale Package (LFCSP_VQ)
Z = RoHS Compliant Part.
Rev. B | Page 15 of 16
Package Option
RU-16
RU-16
RU-16
CP-16-3
CP-16-3
RU-16
RU-16
RU-16
CP-16-3
CP-16-3
RU-16
RU-16
RU-16
CP-16-3
CP-16-3
Branding
S07
S07
S08
S08
S09
S09
ADG1211/ADG1212/ADG1213
Data Sheet
NOTES
©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04778-0-8/12(B)
Rev. B | Page 16 of 16
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