Sharp LH28F004SU-Z1 4m (512k ã 8) flash memory Datasheet

LH28F004SU-Z1
FEATURES
• 512K × 8 Word Configuration
• 5 V Write/Erase Operation (5 V VPP)
40-PIN TSOP
TOP VIEW
A16
1
40
A17
A15
2
39
GND
A14
3
38
NC
A13
4
37
NC
100 ns Maximum Access Time
A12
5
36
A10
32 Independently Lockable Blocks (16K)
A11
6
35
DQ7
A9
7
34
DQ6
A8
8
33
DQ5
WE
9
32
DQ4
RP
10
31
VCC
– No Requirement for DC/DC Converter
to Write/Erase
•
•
•
•
4M (512K × 8) Flash Memory
100,000 Erase Cycles per Block
Automated Byte Write/Block Erase
– Command User Interface
– Status Register
– RY /» BY » Status Output
• System Performance Enhancement
– Erase Suspend for Read
– Two-Byte Write
– Full Chip Erase
• Data Protection
– Hardware Erase/Write Lockout during
Power Transitions
– Software Erase/Write Lockout
• Independently Lockable for Write/Erase
on Each Block (Lock Block and Protect
Set/Reset)
VPP
11
30
VCC
RY/BY
12
29
NC
A18
13
28
DQ3
A7
14
27
DQ2
A6
15
26
DQ1
A5
16
25
DQ0
A4
17
24
OE
A3
18
23
GND
A2
19
22
CE
A1
20
21
A0
28F004SUT-Z1-1
Figure 1. TSOP Configuration
• 5 µA (Typ.) ICC in CMOS Standby
• 0.2 µA (Typ.) Deep Power-Down
• State-of-the-Art 0.55 µm ETOX™ Flash
Technology
• 40-pin, 1.2 mm × 10 mm × 20 mm TSOP
(Type I) Package
1
LH28F004SU-Z1
4M (512K × 8) Flash Memory
DQ0 - DQ7
OUTPUT
BUFFER
INPUT
BUFFER
DATA
QUEUE
REGISTER
ID
REGISTER
I/O
LOGIC
CSR
OUTPUT
MULTIPLEXER
REGISTER
ESRs
CE
OE
CUI
WE
RP
DATA
COMPARATOR
ADDRESS
COUNTER
16KB BLOCK 31
...
16KB BLOCK 30
X-DECODER
16KB BLOCK 1
ADDRESS
QUEUE
LATCH
Y GATING/SENSING
Y-DECODER
16KB BLOCK 0
INPUT
BUFFER
...
A0 - A18
...
WSM
PROGRAM/
ERASE
VOLTAGE
SWITCH
RY/BY
VPP
VCC
GND
28F004SUT-Z1-2
Figure 2. LH28F004SU-Z1 Block Diagram
2
4M (512K × 8) Flash Memory
LH28F004SU-Z1
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
A0 - A13
INPUT
WORD-SELECT ADDRESSES: Select a word within one 16K block. These
addresses are latched during Data Writes.
A14 - A18
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
INPUT/OUTPUT
DATA INPUT/OUTPUT: Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate Read mode.
Floated when the chip is de-selected or the outputs are disabled.
INPUT
CHIP ENABLE INPUT: Activate the device’s control logic, input buffers, decoders
and sense amplifiers. CE » must be low to select the device.
RP »
INPUT
RESET/POWER-DOWN: RP » low places the device in a Deep Power-Down state. All
circuits that burn static power, even those circuits enabled in standby mode, are
turned off. When returning from Deep Power-Down, a recovery time of 550 ns is
required to allow these circuits to power-up. When RP» goes low, any current or
pending WSM operation(s) are terminated, and the device is reset. All Status
Registers return to ready (with all status flags cleared).
OE »
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when low. The
outputs float to tri-state off when OE » is high.
WE
INPUT
WRITE ENABLE: Controls access to the CUI, Data Queue Registers and Address
Queue Latches. WE is active low, and latches both address and data (command or
array) on its rising edge.
OPEN DRAIN
OUTPUT
READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the
WSM is busy performing an operation. When the WSM is ready for new operation
or Erase is Suspended, or the device is in deep power-down mode RY»/BY » pin is
floated.
VPP
SUPPLY
ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V): For erasing memory array blocks
or writing words/bytes into the flash array.
VCC
SUPPLY
DEVICE POWER SUPPLY (5.0 V ±0.5 V): Do not leave any power pins floating.
GND
SUPPLY
GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.
DQ0 - DQ7
CE »
RY »/BY »
NC
NO CONNECT: No internal connection to die, lead may be driven or left floating
3
LH28F004SU-Z1
INTRODUCTION
Sharp’s LH28F004SU-Z1 4M Flash Memory is a revolutionary architecture which enables the design of truly
mobile, high performance, personal computing and communication products. With innovative capabilities, 5 V
single voltage operation and very high read/write performance, the LH28F004SU-Z1 is also the ideal choice
for designing embedded mass storage flash memory
systems.
The LH28F004SU-Z1 is a very high density, highest
performance non-volatile read/write solution for solidstate storage applications. Its independently lockable
32 symmetrical blocked architecture (16K each)
extended cycling, low power operation, very fast write
and read performance and selective block locking provide a highly flexible memory component suitable for
high density memory cards, Resident Flash Arrays and
PCMCIA-ATA Flash Drives. The LH28F004SU-Z1’s
single power supply operation enables the design of
memory cards which can be read/written in 5.0 V systems. Its x8 architecture allows the optimization of
memory to processor interface. The flexible block locking option enables bundling of executable application
software in a Resident Flash Array or memory card.
Manufactured on Sharp’s 0.55 µm ETOX™ process
technology, the LH28F004SU-Z1 is the most costeffective, high-density 5.0 V flash memory.
Description
The LH28F004SU-Z1 is a high perfor mance
4M (4,194,304 bit) block erasable non-volatile random
access memor y organized as 512K × 8. The
LH28F004SU-Z1 includes thirty-two 16K (16,384)
blocks. A chip memory map is shown in Figure 3.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F004SU-Z1:
• 5 V Read, Write/Erase Operations (5 V VCC, VPP)
• Low Power Capability
• Improved Write Performance
• Dedicated Block Write/Erase Protection
• Command-Controlled Memory Protection
Set/Reset Capability
The LH28F004SU-Z1 will be available in a 40-pin,
1.2 mm thick × 10 mm × 20 mm TSOP (Type I) package. This form factor and pinout allow for very high board
layout densities.
4
4M (512K × 8) Flash Memory
A Commander User Interface (CUI) serves as the
system interface between the microprocessor or
microcontroller and the internal memory operation.
Internal Algorithm Automation allows Byte Writes and
Block Erase operations to be executed using a TwoWrite command sequence to the CUI in the same way
as the LH28F008SA 8M Flash Memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
• Software Locking of Memory Blocks
• Memory Protection Set/Reset Capability
• Two-Byte Successive Writes in 8-bit Systems
• Erase All Unlocked Blocks
Writing of memory data is performed typically within
13 µs. A Block Erase operation erases one of the 32
blocks in typically 0.6 seconds, independent of the other
blocks.
LH28F004SU-Z1 allows to erase all unlocked blocks.
It is desirable in case you have to implement Erase operation maxmum 32 times.
LH28F004SU-Z1 enablesTwo-Byte serialWrite which
is operated by three times command input. This feature
can improve system write performance by up to typically 10 µs per byte.
All operations are started by a sequence of Write
commands to the device. Status Register (described in
detail later) and a RY »/BY » output pin provide information on the progress of the requested operation.
Same as the LH28F008SA, LH28F004SU-Z1
requires an operation to complete before the next
operation can be requested, also it allows to suspend
block erase to read data from any other block, and allow to resume erase operation.
The LH28F004SU-Z1 provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable OS or
Application Code. Each block has an associated nonvolatile lock-bit which determines the lock status of the
block. In addition, the LH28F004SU-Z1 has a software
controlled master Write Protect circuit which prevents
any modifications to memory blocks whose lock-bits are
set.
4M (512K × 8) Flash Memory
When the device power-up or RP » turns High, Write
Protect Set/Confirm command must be written. Otherwise, all lock bits in the device remain being locked,
can’t perform the Write to each block and single Block
Erase. Write Protect Set/Confirm command must be
written to reflect the actual lock status. However, when
the device power-on or RP » turns High, Erase All Unlocked Blocks can be used. If used, Erase is performed
with reflecting actual lock status, and after that Write
and Block Erase can be used.
The LH28F004SU-Z1 contains Status Register to
accomplish various functions:
• A Compatible Status Register (CSR) which is
100% compatible with the LH28F008SA Flash
Memory’s Status Register. This register, when used
alone, provides a straightforward upgrade capability to the LH28F004SU-Z1 from a LH28F008SA
based design.
The LH28F004SU-Z1 incorporates an open drain
RY »/BY » output pin. This feature allows the user to ORtie many RY /» BY » pins together in a multiple memory configuration such as a Resident Flash Array.
The LH28F004SU-Z1 is specified for a maximum
access time of 100 ns (tACC) at 5 V operation (4.5 to
5.5 V) over the commercial temperature range (0 to
+70°C).
The LH28F004SU-Z1 incorporates an Automatic
Power Saving (APS) feature which substantially reduces
the active current when the device is in static mode of
operation (addresses not switching).
In APS mode, the typical ICC current is 2 mA at 5.0 V.
A Deep Power-Down mode of operation is invoked
when the RP » (called PWD on the LH28F008SA) pin
transitions low. This mode brings the device power consumption to less than 5 µA, and provides additional write
protection by acting as a device reset pin during power
transitions. A reset time of 550 ns is required from RP »
switching high until outputs are again valid. In the Deep
Power-Down state, the WSM is reset (any current
operation will abort) and the CSR register is cleared.
A CMOS Standby mode of operation is enabled when
CE » transitions high and RP » stays high with all input
control pins at CMOS levels. In this mode, the device
draws an ICC standby current of 10 µA.
LH28F004SU-Z1
MEMORY MAP
7FFFFH
7C000H
7BFFFH
78000H
77FFFH
74000H
73FFFH
70000H
6FFFFH
6C000H
6BFFFH
68000H
67FFFH
64000H
63FFFH
60000H
5FFFFH
5C000H
5BFFFH
58000H
57FFFH
54000H
53FFFH
50000H
4FFFFH
4C000H
4BFFFH
48000H
47FFFH
44000H
43FFFH
40000H
3FFFFH
3C000H
3BFFFH
38000H
37FFFH
34000H
33FFFH
30000H
2FFFFH
2C000H
2BFFFH
28000H
27FFFH
24000H
23FFFH
20000H
1FFFFH
1C000H
1BFFFH
18000H
17FFFH
14000H
13FFFH
10000H
0FFFFH
0C000H
0BFFFH
08000H
07FFFH
04000H
03FFFH
16KB BLOCK
31
16KB BLOCK
30
16KB BLOCK
29
16KB BLOCK
28
16KB BLOCK
27
16KB BLOCK
26
16KB BLOCK
25
16KB BLOCK
24
16KB BLOCK
23
16KB BLOCK
22
16KB BLOCK
21
16KB BLOCK
20
16KB BLOCK
19
16KB BLOCK
18
16KB BLOCK
17
16KB BLOCK
16
16KB BLOCK
15
16KB BLOCK
14
16KB BLOCK
13
16KB BLOCK
12
16KB BLOCK
11
16KB BLOCK
10
16KB BLOCK
9
16KB BLOCK
8
16KB BLOCK
7
16KB BLOCK
6
16KB BLOCK
5
16KB BLOCK
4
16KB BLOCK
3
16KB BLOCK
2
16KB BLOCK
1
16KB BLOCK
0
00000H
28F004SUT-Z1-3
Figure 3. Memory Map
5
LH28F004SU-Z1
4M (512K × 8) Flash Memory
BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
Bus Operations
RP »
CE »
OE »
WE
A0
DQ0-7
RY/BY#
NOTE
Read
VIH
VIL
VIL
VIH
X
DOUT
X
1, 2, 7
Output Disable
VIH
VIL
VIH
VIH
X
High-Z
X
1, 6, 7
Standby
VIH
VIH
X
X
X
High-Z
X
1, 6, 7
Deep Power-Down
VIL
X
X
X
X
High-Z
VOH
1, 3
Manufacturer ID
VIH
VIL
VIL
VIH
VIL
B0H
VOH
4
Device ID
VIH
VIL
VIL
VIH
VIH
ID
VOH
4
Write
VIH
VIL
VIH
VIL
X
DIN
X
1, 5, 6
MODE
NOTES:
1. X can be VIH or VIL for address or control pins except for RY »/BY », which is either VOL or VOH .
2. RY »/BY » output is open drain. When the WSM is ready, Erase is suspended or the device is in deep
power-down mode, RY »/BY » will be at VOH if it is tied to VCC through a resistor. When the RY /» BY »
at VOL is independent of OE » while a WSM operation is in progress.
3. RP » at GND ± 0.2 V ensures the lowest deep power-down current.
4. A0 at VIL provide manufacturer ID codes. A0 at VIH provide device ID codes. Device ID code = 21H.
All other addresses are set to zero.
5. Commands for different Erase operations, Data Write Operations, and lock-block operations can only
be successfully completed when VPP = VPPH.
6. While the WSM is running, RY »/BY » in Level-Mode (default) stays at VOL until all operations are complete.
RY »/BY » goes to VOH when the WSM is not busy or in erase suspend mode.
7. RY »/BY » may be at VOL while the WSM is busy performing various operations. For example, a status register
read during a write operation.
8. Only to RP », VIH (MIN.) = 2.4 V at TTL-level input.
6
4M (512K × 8) Flash Memory
LH28F004SU-Z1
LH28F008SA-Compatible Mode Command Bus Definitions
FIRST BUS CYCLE
SECOND BUS CYCLE
COMMAND
NOTE
OPER.
ADDRESS
DATA
OPER.
ADDRESS
DATA
Read Array
Write
X
FFH
Read
AA
AD
Intelligent Identifier
Write
X
90H
Read
IA
ID
1
Read Compatible Status Register
Write
X
70H
Read
X
CSRD
2
Clear Status Register
Write
X
50H
Word Write
Write
X
40H
Write
WA
WD
Alternate Word Write
Write
X
10H
Write
WA
WD
Block Erase/Confirm
Write
X
20H
Write
BA
D0H
4
Erase Suspend/Resume
Write
X
B0H
Write
X
D0H
4
ADDRESS
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don’t Care
3
DATA
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
WD = Write Data
NOTES:
1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.
3. Clears CSR.3, CSR.4, and CSR.5. See Status register definitions.
4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is
set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WSMS = 1), be sure
to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued, while
the device is not in Erase, be sure to issue Resume command (D0H) after the next erase complete.
LH28F004SU-Z1 Performance Enhancement Command Bus Definitions
COMMAND
MODE
FIRST BUS CYCLE
SECOND BUS CYCLE
OPER. ADD. DATA OPER. ADD.
DATA
THIRD BUS CYCLE
OPER. ADD.
NOTE
DATA
Protect Set/Confirm
Write
X
57H
Write
0FFH
D0H
1, 2
Protect Reset/Confirm
Write
X
47H
Write
0FFH
D0H
3
Lock Block/Confirm
Write
X
77H
Write
BA
D0H
1, 2, 4
Erase All Unlocked
Blocks
Write
X
A7H
Write
X
D0H
1, 2
Write
X
FBH
Write
A10
WD (L, H)
Two-Byte Write
ADDRESS
BA = Block Address
WA = Write Address
X = Don’t Care
x8
Write
WA
WD (H, L) 1, 2, 5
DATA
AD = Array Data
WD (L, H) = Write Data (Low, High)
WD (H, L) = Write Data (High, Low)
NOTES:
1. After initial device power-up, or return from deep power-down mode, the block lock status bit default to the locked state independent of
the data in the corresponding lock bits. In order to upload the lock bit status, it requires to write Protect Set/Confirm command.
2. To reflect the actual lock-bit status, the Protect Set/Confirm command must be written after Lock Block/Confirm command.
3. When Protect Reset/Confirm command is written, all blocks can be written and erased regardless of the state of the lock-bits.
4. The Lock Block/Confirm command must be written after Protect Reset/Confirm command was written.
5. A10 is automatically complemented to load second byte of data A10 value determines which WD is supplied first: A10 = 0 looks at the
WDL, A10 = 1 looks at the WDH.
6. Second bus cycle address of Protect Set/Confirm and Protect Reset/Confirm command is 0FFH. Specifically A9 - A8 = 0, A7 - A0 = 1,
others are don’t care.
7
LH28F004SU-Z1
4M (512K × 8) Flash Memory
Compatible Status Register
WSMS
ESS
ES
DWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
CSR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
2 = Busy
CSR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase in Progress/Completed
CSR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
CSR.4 = DATA-WRITE STATUS (DWS)
1 = Error in Data Write
0 = Data Write Successful
CSR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
4M FLASH MEMORY
SOFTWARE ALGORITHMS
Overview
With the advanced Command User Interface, its Performance Enhancement commands and Status Registers, the software code required to perform a given
operation may become more intensive but it will result
in much higher write/erase performance compared with
current flash memory architectures.
The software flowcharts describing how a given
operation proceeds are shown here. Figures 4 through
6 depict flowcharts using the 2nd generation flash device in the LH28F008SA-compatible mode. Figures 7
through 12 depict flowcharts using the 2nd generation
flash device’s performance enhancement commands
mode.
When the device power-up or the device is reset by
RP » pin, all blocks come up locked. Therefore, Word
Write, Two Byte Serial Write and Block Erase can not
8
NOTES:
1. RY »/BY » output or WSMS bit must be checked to determine
completion of an operation (Erase Suspend, Erase or Data
Write) before the appropriate Status bit (ESS, ES or DWS)
is checked for success.
2. If DWS and ES are set to ‘1’ during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
3. The VPPS bit, unlike an A/D converter, does not provide
continuous indication of VPP level. The WSM interrogates
VPP’s level only after the Data-Write or Erase command
sequences have been entered, and informs the system if
VPP has not been switched on. VPPS is not guaranteed to
report accurate feedback between VPPL and VPPH.
4. CSR.2 - CSR.0 = Reserved for further enhancements.
These bits are reserved for future use and should be
masked out when polling the CSR.
be performed in each block. However, at that time, Erase
All Unlocked Block is performed normally, if used, and
reflect actual lock status, also the unlocked block data
is erased. When the device power-up or the device is
reset by RP » pin, Set Write Protect command must be
written to reflect actual block lock status.
Reset Write Protect command must be written before Write Block Lock command. To reflect actual block
lock status, Set Write Protect command is succeeded.
Reset Write Protect command enables Write/Erase
operation to each block.
In the case of Block Erase is performed, the block
lock information is also erased. Block Lock command
and Set Write Protect command must be written to prohibit Write/Erase operation to each block.
There are unassigned commands. It is not recommended that the customer use any command other than
the valid commands specified in “Command Bus Definitions”. Sharp reserved the right to redefine these codes
for future functions.
4M (512K × 8) Flash Memory
LH28F004SU-Z1
BUS
OPERATION
START
Write
WRITE 40H or 10H
COMMAND
Word/Byte
Write
D = 40H or 10H
A=X
Write
D = WD
A = WA
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
A=X
Standby
Check CSR.7
1 = WSM Ready
0 = WSM Busy
WRITE
DATA/ADDRESS
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
COMMENTS
0
Repeat for subsequent Word/Byte Writes.
CSR Full Status Check can be done after each Word/Byte
Write, or after a sequence of Word/Byte Writes.
1
Write FFH after the last operation to reset device
to read array mode.
CSR FULL STATUS
CHECK IF DESIRED
See Command Bus Cycle notes for description of codes.
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD
(see above)
CSR.4, 5 =
BUS
OPERATION
0
DATA WRITE
SUCCESSFUL
1
CSR.3 =
1
VPP LOW
DETECT
COMMAND
COMMENTS
Standby
Check CSR.4, 5
1 = Data Write Unsuccessful
0 = Data Write Successful
Standby
Check CSR.3
1 = VPP Low Detect
0 = VPP OK
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
0
CLEAR CSRD
RETRY/ERROR
RECOVERY
28F004SUT-Z1-4
Figure 4. Word/Byte Writes with Compatible Status Register
9
LH28F004SU-Z1
4M (512K × 8) Flash Memory
START
WRITE 20H
BUS
OPERATION
COMMAND
Write
Block Erase
D = 20H
A=X
Write
Confirm
D = D0H
A = BA
WRITE D0H AND
BLOCK ADDRESS
Read
Q = CSRD
Toggle CE or OE
to update CSRD
A=X
Standby
Check CSR.7
1 = WSM Ready
0 = WSM Busy
READ COMPATIBLE
STATUS REGISTER
SUSPEND
NO ERASE LOOP
CSR.7 =
0
SUSPEND YES
ERASE
COMMENTS
Repeat for subsequent Block Erasures.
CSR Full Status Check can be done after each Block Erase,
or after a sequence of Block Erasures.
1
Write FFH after the last operation to reset
device to read array mode.
CSR FULL STATUS
CHECK IF DESIRED
See Command Bus Cycle notes for description of codes.
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD
(see above)
CSR.4, 5 =
BUS
OPERATION
0
CSR.3 =
1
VPP LOW
DETECT
COMMENTS
Standby
Check CSR.4, 5
1 = Erase Error
0 = Erase Successful
Both 1 = Command
Sequence Error
Standby
Check CSR.3
1 = VPP Low Detect
0 = VPP OK
ERASE
SUCCESSFUL
1
COMMAND
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
0
CLEAR CSRD
RETRY/ERROR
RECOVERY
28F004SUT-Z1-5
Figure 5. Block Erase with Compatible Status Register
10
4M (512K × 8) Flash Memory
LH28F004SU-Z1
START
WRITE B0H
BUS
OPERATION
COMMAND
Write
Erase
Suspend
Q = CSRD
Toggle CE or OE
to update CSRD.
A=X
Standby
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check CSR.6
1 = Erase Suspended
0 = Erase Completed
0
1
CSR.6 =
0
Write
ERASE COMPLETED
Read
Array
Read
1
Write
D = FFH
A=X
Q = AD
Read must be from
block other than the
one suspended.
WRITE FFH
READ ARRAY DATA
D = B0H
A=X
Read
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
COMMENTS
Erase
Resume
D = D0H
A=X
See Command Bus Cycle notes for description of codes.
DONE
READING
NO
YES
WRITE D0H
WRITE FFH
ERASE RESUMED
READ ARRAY DATA
28F004SUT-Z1-6
Figure 6. Erase Suspend to Read array with Compatible Status Register
11
LH28F004SU-Z1
4M (512K × 8) Flash Memory
BUS
COMMAND
OPERATION
START
Read
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
Write
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
Reset
Write Protect
Read
1
CSR.7 =
After Write D = 47H A = X,
Write D = D0H A = 0FFH
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
RESET WP
READ COMPATIBLE
STATUS REGISTER
COMMENTS
Write
Lock Block
D = 77H
A=X
Write
Confirm
D = D0H
A = BA
0
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
Read
1
WRITE 77H
Write
WRITE D0H AND
BLOCK ADDRESS
Set
Write Protect
After Write D = 57H A = X,
Write D = D0H A = 0FFH
NOTE:
See CSR Full Status Check for Data-Write operation.
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
READ COMPATIBLE
STATUS REGISTER
Write FFH after the last operation to reset device to read
array mode.
See Command Bus Definitions for description of codes.
CSR.7 =
0
1
CSR.4, 5 =
1
(NOTE)
0
LOCK
YES
ANOTHER
BLOCK
NO
SET WP
OPERATION COMPLETE
28F004SUT-Z1-7
Figure 7. Block Locking Scheme
12
4M (512K × 8) Flash Memory
LH28F004SU-Z1
START
START
RESET WP
(NOTE 1)
RESET WP
(NOTE 1)
ERASE BLOCK
(NOTE 2)
WRITE MORE
DATA TO BLOCK
(NOTE 4)
SET WP
(NOTE 3)
WRITE NEW DATA
TO BLOCK
(NOTE 4)
SET WP
(NOTE 3)
OPERATION
COMPLETE
FLOW TO ADD DATA
RELOCK BLOCK
(NOTE 5)
OPERATION
COMPLETE
FLOW TO REWRITE DATA
NOTES:
1. Use Reset-Write-Protect flowchart. Enable Write/Erase operation to all blocks.
2. Use Block-Erase flowchart. Erasing a block clears any previously established lockout for that block.
3. Use Set-Write-Protect flowchart. This step re-implements protection to locked blocks.
4. Use Word/Byte-Write or 2-Byte-Write flowchart sequences to write data.
5. Use Block-Lock flowchart to write lock bit if desired.
28F004SUT-Z1-8
Figure 8. Updating Data in a Locked Block
13
LH28F004SU-Z1
4M (512K × 8) Flash Memory
(Apply to LH28F004SU, x8, 40TSOP)
START
BUS
COMMAND
OPERATION
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
Read
1
WRITE FBH
WRITE
DATA/ADDRESS
Write
D = WD
A = WA
Internally, A10 is automatically
complemented to load the
alternate byte location of the
Data Register.
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
1
CSR.4, 5 =
D = FBH
A=X
D = WD
A10 = 0 loads low byte
of Data Register.
A10 = 1 loads high byte
of Data Register.
Other Addresses = X
READ COMPATIBLE
STATUS REGISTER
0
2-Byte
Write
Write
WRITE DATA/A10
CSR.7 =
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
0
Write
COMMENTS
1
(NOTE)
CSR Full Status Check can be done after each 2-Byte Write,
or after a sequence of 2-Byte Writes.
Write FFH after the last operation to reset device to read
array mode.
0
See Command Bus Cycle notes for description of codes.
ANOTHER
2-BYTE
WRITE
YES
NO
OPERATION COMPLETE
28F004SUT-Z1-9
Figure 9. Two-Byte Serial Writes with Compatible Status Registers (40-pin TSOP)
14
4M (512K × 8) Flash Memory
(Apply to LH28F400SU, x16/8, 56TSOP/44SOP)
START
BUS
COMMAND
OPERATION
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
LH28F004SU-Z1
Read
Write
WRITE FBH
WRITE
DATA/ADDRESS
Write
D = WD
A = WA
Internally, A-1 is automatically
complemented to load the
alternate byte location of the
Data Register.
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
1
CSR.4, 5 =
D = FBH
A=X
D = WD
A-1 = 0 loads low byte
of Data Register.
A-1 = 1 loads high byte
of Data Register.
Other Addresses = X
READ COMPATIBLE
STATUS REGISTER
0
2-Byte
Write
Write
WRITE DATA/A-1
CSR.7 =
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
0
1
COMMENTS
1
(NOTE)
CSR Full Status Check can be done after each 2-Byte Write,
or after a sequence of 2-Byte Writes.
Write FFH after the last operation to reset device to read
array mode.
0
See Command Bus Cycle notes for description of codes.
ANOTHER
2-BYTE
WRITE
YES
NO
OPERATION COMPLETE
28F004SUT-Z1-10
Figure 10. Two-Byte Serial Writes with Compatible Status Registers (56-pin TSOP, 44-pin SOP)
15
LH28F004SU-Z1
4M (512K × 8) Flash Memory
START
BUS
OPERATION
COMMAND
Write
Erase All
Unlocked
Blocks
D = A7H
A=X
Write
Confirm
D = D0H
A=X
WRITE A7H
WRITE D0H
Read
Q = CSRD
Toggle CE or OE
to update CSRD
A=X
Standby
Check CSR.7
1 = WSM Ready
0 = WSM Busy
READ COMPATIBLE
STATUS REGISTER
SUSPEND
NO ERASE LOOP
0
CSR.7 =
SUSPEND
ERASE
COMMENTS
YES
CSR Full Status Check can be done after Erase All Unlocked
Block, or after a sequence of Erasures.
Write FFH after the last operation to reset
device to read array mode.
1
See Command Bus Cycle notes for description of codes.
CSR FULL STATUS
CHECK IF DESIRED
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD
(see above)
CSR.4, 5 =
BUS
OPERATION
0
CSR.3 =
1
VPP LOW
DETECT
COMMENTS
Standby
Check CSR.4, 5
1 = Erase Error
0 = Erase Successful
Both 1 = Command
Sequence Error
Standby
Check SR.3
1 = VPP Low Detect
0 = VPP OK
ERASE
SUCCESSFUL
1
COMMAND
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
0
CLEAR CSRD
RETRY/ERROR
RECOVERY
28F004SUT-Z1-11
Figure 11. Erase All Unlocked Blocks with Compatible Status Registers
16
4M (512K × 8) Flash Memory
LH28F004SU-Z1
BUS
COMMAND
OPERATION
START
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
COMMENTS
Write
Set
Write Protect
D = 57H
A=X
Write
Set Confirm
D = D0H
A = 0FFH
(A9 - A8 = 0, A7 - A0 = 1,
Others = X)
1
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Read
Check CSR.4, 5
1 = Unsuccesful
0 = Successful
WRITE 57H
WRITE CONFIRM
DATA/ADDRESS
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
READ COMPATIBLE
STATUS REGISTER
Upon device power-up or toggle RP, Set Write Protect
command must be written to reflect the actual lock-bit
status.
CSR.7 =
Write FFH after the last operation to reset device to
Read Array Mode.
0
See Command Bus Cycle notes for description of codes.
1
CSR.4, 5 =
1
(NOTE)
0
OPERATION
COMPLETE
28F004SUT-Z1-12
Figure 12. Set Write Protect
17
LH28F004SU-Z1
4M (512K × 8) Flash Memory
BUS
COMMAND
OPERATION
START
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
COMMENTS
Write
Reset
Write Protect
Write
Reset
Confirm
D = 47H
A=X
D = D0H
A = 0FFH
(A9 - A8 = 0, A7 - A0 = 1,
Others = X)
1
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Read
Check CSR.4, 5
1 = Unsuccesful
0 = Successful
WRITE 47H
WRITE CONFIRM
DATA/ADDRESS
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
READ COMPATIBLE
STATUS REGISTER
Reset Write Protect command enables Write/Erase
operation to all blocks.
CSR.7 =
Write FFH after the last operation to reset device to
Read Array Mode.
0
See Command Bus Cycle notes for description of codes.
1
CSR.4, 5 =
1
(NOTE)
0
OPERATION
COMPLETE
28F004SUT-Z1-13
Figure 13. Reset Write Protect
18
4M (512K × 8) Flash Memory
LH28F004SU-Z1
*WARNING: Stressing the device beyond
ELECTRICAL SPECIFICATIONS
the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond
the “Operating Conditions” is not recommended and
extended exposure beyond the “Operating Conditions”
may affect device reliability.
Absolute Maximum Ratings*
Temperature under bias ......................... 0°C to +80°C
Storage temperature ......................... -65°C to +125°C
VCC = 5.0 V ± 0.5 V Systems4
SYMBOL
TA
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
0
70.0
°C
Ambient Temperature
1
Operating Temperature, Commercial
VCC
VCC with Respect to GND
-0.2
7.0
V
2
VPP
VPP Supply Voltage with Respect to GND
-0.2
7.0
V
2
V
Voltage on any Pin (Except VCC, VPP)
with Respect to GND
-0.5
7.0
V
2
I
Current into any Non-Supply Pin
±30
mA
100.0
mA
IOUT
Output Short Circuit Current
3
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum
DC voltage on input/output pins is VCC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
4. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
Capacitance
For 5.0 V Systems
SYMBOL
TYP.
MAX.
UNITS
Capacitance Looking into an
Address/Control Pin
7
10
pF
TA = 25°C, f = 1.0 MHz
1
Capacitance Looking into an
Address/Control Pin A10
9
12
pF
TA = 25°C, f = 1.0 MHz
1
COUT
Capacitance Looking into an Output Pin
9
12
pF
TA = 25°C, f = 1.0 MHz
1
CLOAD
Load Capacitance Driven by Outputs for
Timing Specifications
100
pF
For VCC = 5.0 V ±0.5 V
1
Equivalent Testing Load Circuit VCC ± 10%
2.5
ns
25 Ω transmission line delay
CIN
PARAMETER
TEST CONDITIONS
NOTE
NOTE:
1. Sampled, not 100% tested.
19
LH28F004SU-Z1
4M (512K × 8) Flash Memory
Timing Nomenclature
For 5.0 V systems use the standard JEDEC cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
tCE
tELQV
time (t) from CE » (E) going low (L) to the outputs (Q) becoming valid (V)
tOE
tGLQV
time (t) from OE » (G) going low (L) to the outputs (Q) becoming valid (V)
tACC tAVQV
time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tAS
tAVWH time (t) from address (A) valid (V) to WE » (W) going high (H)
tDH
tWHDX time (t) from WE » (W) going high (H) to when the data (D) can become undefined (X)
PIN CHARACTERS
PIN STATES
A
Address Inputs
H
High
D
Data Inputs
L
Low
Q
Data Outputs
V
Valid
E
CE » (Chip Enable)
X
Driven, but not necessarily valid
G
OE » (Output Enable)
Z
High Impedance
W
WE (Write Enable)
P
RP » (Deep Power-Down Pin)
R
RY »/BY » (Ready/Busy)
V
Any Voltage Level
5V
VCC at 4.5 V Min.
2.4
INPUT
0.45
2.0
0.8
TEST POINTS
2.0
0.8
2.5 ns OF 25 Ω TRANSMISSION LINE
OUTPUT
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a Logic '1' and VOL
(0.45 VTTL) for a Logic '0'. Input timing begins at VIH (2.0 VTTL)
and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise
and fall times (10% to 90%) < 10 ns.
28F004SUT-Z1-14
Figure 14. Transient Input/Output
Reference Waveform (VCC = 5.0 V)
20
FROM OUTPUT
UNDER TEST
TEST
POINT
TOTAL CAPACITANCE = 100 pF
28F004SUT-Z1-15
Figure 15. Transient Equivalent Testing
Load Circuit (VCC = 5.0 V)
4M (512K × 8) Flash Memory
LH28F004SU-Z1
DC Characteristics
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
IIL
Input Load Current
±1
µA
VCC = VCC MAX., VIN = VCC or GND
1
ILO
Output Leakage Current
±10
µA
VCC = VCC MAX., VIN = VCC or GND
1
10
µA
VCC = VCC MAX.,
CE », RP » = VCC ±0.2 V
5
ICCS
ICCD
ICCR1
VCC Standby Current
VCC Deep Power-Down
Current
1,4
1
4
mA
VCC = VCC MAX.,
CE », RP » = VIH
0.2
5
µA
RP » = GND ±0.2 V
mA
VCC = VCC MAX.,
CMOS: CE » = GND ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
TTL: CE » = VIL
Inputs = VIL or VIH
f = 10 MHz, IOUT = 0 mA
1, 3, 4
1, 3, 4
VCC Read Current
60
1
ICCR2
VCC Read Current
13
30
mA
VCC = VCC MAX.,
CMOS: CE » = GND ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
TTL: CE » = VIL
Inputs = VIL or VIH
f = 5 MHz, IOUT = 0 mA
ICCW
VCC Write Current
18
35
mA
Byte/Two-Byte Serial Write
in Progress
1
ICCE
VCC Block Erase Current
18
25
mA
Block Erase in Progress
1
ICCES
VCC Erase Suspend
Current
5
10
mA
CE » = VIH
Block Erase Suspended
1, 2
IPPS
VCC Standby Current
±10
µA
VPP ≤ VCC
1
IPPD
VPP Deep Power-Down
Current
5
µA
RP » = GND ±0.2 V
1
0.2
21
LH28F004SU-Z1
4M (512K × 8) Flash Memory
DC Characteristics (Continued)
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
TYPE
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
IPPR
VPP Read Current
65
200
µA
VPP > VCC
1
IPPW
VPP Write Current
15
35
mA
VPP = VPPH, Byte/Two-Byte
Serial Write in Progress
1
IPPE
VPP Erase Current
20
40
mA
VPP = VPPH,
Block Erase in Progress
1
IPPES
VPP Erase Suspend
Current
65
200
µA
VPP = VPPH,
Block Erase Suspended
1
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
0.45
V
VCC = VCC MIN. and
IOL = 5.8 mA
0.85 VCC
V
IOL = -2.5 mA
VCC = VCC MIN.
VCC - 0.4
V
IOL = -100 µA
VCC = VCC MIN.
VOH1
Output High Voltage
VOH
2
VPPL
VPP during Normal
Operations
VPPH
VPP during Write/Erase
Operations
VLKO
VCC Erase/Write
Lock Voltage
5.0
0.0
5.5
V
4.5
5.5
V
1.4
5
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 5.0 V, T = 25°C. These currents are valid for all
product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of
ICCES and ICCR.
3. Automatic Power Saving (APS) reduces ICCR to less than 2 mA in Static operation.
4. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL Inputs are either VIL or VIH.
5. Only to RP », VIH (Min.) = 2.4 V at TTL-level input.
22
4M (512K × 8) Flash Memory
LH28F004SU-Z1
AC Characteristics - Read Only Operations1
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
tAVAV
Read Cycle Time
tAVGL
Address Setup to OE » Going Low
tAVQV
Address to Output Delay
100
ns
tELQV
CE » to Output Delay
100
ns
2
tPHQV
RP » High to Output Delay
550
ns
4
tGLQV
OE » to Output Delay
40
ns
2
tELQX
CE » to Output in Low Z
ns
3
tEHQZ
CE » to Output in High Z
ns
3
tGLQX
OE » to Output in Low Z
ns
3
tGHQZ
OE » to Output in High Z
ns
3
ns
3
tOH
Output Hold from Address, CE » or
OE » change, whichever occurs first
100
ns
0
ns
NOTE
0
35
0
35
0
3
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements, Figure 4.
2. OE » may be delayed up to tELQV - tGLQV after the failing edge of CE » without impact on tELQV.
3. Sampled, not 100% tested.
4. Only to RP », VIH (MIN.) = 2.4 V.
23
LH28F004SU-Z1
4M (512K × 8) Flash Memory
VCC
POWER-UP
ADDRESSES (A)
STANDBY
DEVICE AND
ADDRESS
SELECTION
VIH
OUTPUTS ENABLED
DATA VALID
...
...
ADDRESSES STABLE
VIL
VCC
STANDBY POWER-DOWN
tAVAV
CE (E)
VIH
VIL
...
tEHQZ
OE (G)
VIH
VIL
...
tAVGL
WE (W)
tGHQZ
...
VIH
VIL
tGLQV
tELQV
tOH
tGLQX
tELQX
DATA (D/Q)
VOH
...
HIGH-Z
VALID OUTPUT
HIGH-Z
...
VOL
tAVQV
VCC
5.0 V
GND
tPHQV
RP (P)
VIH
VIL
28F004SUT-Z1-16
Figure 16. Read Timing Waveforms
24
4M (512K × 8) Flash Memory
LH28F004SU-Z1
POWER-UP AND RESET TIMINGS
VCC POWER UP
RP (P)
5.0 V
4.5 V
VCC (5 V)
0V
tPL5V
ADDRESS (A)
VALID
tAVQV
VALID
5.0 V OUTPUTS
DATA (Q)
tPHQV
28F004SUT-Z1-17
Figure 17. VCC Power-Up and RP » Reset Waveforms
SYMBOL
PARAMETER
MIN.
MAX.
0
UNITS
NOTE
µs
1
tPL5V
RP# Low to VCC at 4.5 V MIN.
tAVQV
Address Valid to Data Valid for VCC 5 V ± 10%
100
ns
2
tPHQV
RP# High to Data Valid for VCC 5 V ± 10%
550
ns
2
NOTES:
CE » and OE » are switched low after Power-Up.
1. The power supply may start to switch concurrently with RP » going Low.
2. The address access time and RP » high to data valid time are shown for 5 V VCC operation. Refer to the
AC Characteristics Read Only Operations also.
25
LH28F004SU-Z1
4M (512K × 8) Flash Memory
AC Characteristics for WE » - Controlled Command Write Operations1
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
NOTE
tAVAV
Write Cycle Time
100
ns
tVPWH
VPP Set up to WE Going High
100
ns
tPHEL
RP » Setup to CE » Going Low
480
ns
tELWL
CE » Setup to WE Going Low
0
ns
tAVWH
Address Setup to WE Going High
60
ns
2, 6
tDVWH
Data Setup to WE Going High
60
ns
2, 6
tWLWH
WE Pulse Width
60
ns
tWHDX
Data Hold from WE High
0
ns
2
tWHAX
Address Hold from WE High
10
ns
2
tWHEH
CE » Hold from WE High
10
ns
tWHWL
WE Pulse Width High
50
ns
tGHWL
Read Recovery before Write
0
ns
tWHRL
WE High to RY »/BY » Going Low
tRHPL
RP » Hold from Valid Status Register
Data and RY »/BY » High
0
ns
tPHWL
RP » High Recovery to WE Going Low
1
µs
tWHGL
Write Recovery before Read
80
ns
tQVVL
VPP Hold from Valid Status Register
Data and RY »/BY » High
0
µs
4.5
µs
4, 5
0.3
s
4
tWHQV1
Duration of Byte Write Operation
tWHQV2
Duration of Block Erase Operation
100
13
NOTES:
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Byte write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WE » for all Command Write operations.
26
3
ns
3
4M (512K × 8) Flash Memory
DEEP
POWER-DOWN
LH28F004SU-Z1
WRITE VALID
ADDRESS AND DATA
WRITE
(DATA-WRITE) OR
DATA-WRITE
ERASE CONFIRM
OR ERASE
COMMAND
SETUP COMMAND
ADDRESSES (A) VIH
(NOTE 1)
VIL
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
AIN
tAVAV
READ
COMPATIBLE
STATUS
REGISTER DATA
tAVWH
tWHAX
ADDRESSES (A) VIH
(NOTE 2)
VIL
tAVWH tWHAX
tAVAV
CE (E)
(NOTE 3)
AIN
VIH
VIL
tWHGL
tWHEH
tELWL
OE (G)
VIH
VIL
tWHWL
WE (W)
tWHQV 1, 2
tGHWL
VIH
VIL
tWLWH
tWHDX
tDVWH
DATA (D/Q)
VIH
HIGH-Z
VIL
DIN
DIN
tPHWL
RY/BY (R)
DIN
DIN
DOUT
tWHRL
VOH
VOL
tRHPL
RP (P)
VIH
(NOTE 4)
VIL
tVPWH
tQWL
VPPH
VPP (V) V
PPL
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. RP low transition is only to show tRHPL; not valid for above Read and Write cycles.
28F004SUT-Z1-18
Figure 18. AC Waveforms for Command Write Operations
27
LH28F004SU-Z1
4M (512K × 8) Flash Memory
AC Characteristics for CE » - Controlled Command Write Operations1
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
NOTE
tAVAV
Write Cycle Time
100
ns
tPHWL
RP » Setup to WE Going Low
480
ns
3
tVPEH
VPP Setup to CE » Going High
100
ns
3
tWLEL
WE Setup to CE » Going Low
0
ns
tAVEH
Address Setup to CE » Going High
60
ns
2, 6
tDVEH
Data Setup to CE » Going High
60
ns
2, 6
tELEH
CE » Pulse Width
60
ns
tEHDX
Data Hold from CE » High
0
ns
2
tEHAX
Address Hold from CE » High
10
ns
2
tEHWH
WE Hold from CE » High
10
ns
tEHEL
CE » Pulse Width High
50
ns
tGHEL
Read Recovery before Write
0
ns
tEHRL
CE » High to RY »/BY » Going Low
tRHPL
RP » Hold from Valid Status Register
Data and RY »/BY » High
0
ns
tPHEL
RP » High Recovery to CE » Going Low
1
µs
tEHGL
Write Recovery before Read
80
ns
tQVVL
VPP Hold from Valid Status Register
Data and RY/BY# High
0
µs
tEHQV1
Duration of Byte Write Operation
4.5
µs
4, 5
tEHQV2
Duration of Block Erase Operation
0.3
s
4
100
13
NOTES:
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CE » for all Command Write operations.
28
ns
3
4M (512K × 8) Flash Memory
DEEP
POWER-DOWN
ADDRESSES (A)
(NOTE 1)
LH28F004SU-Z1
WRITE VALID
WRITE
ADDRESS AND DATA
DATA-WRITE
(DATA-WRITE) OR
OR ERASE
ERASE CONFIRM
SETUP COMMAND
COMMAND
VIH
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
AIN
VIL
tAVAV
READ
COMPATIBLE
STATUS
REGISTER DATA
tAVEH
tEHAX
ADDRESSES (A)
(NOTE 2)
VIH
tAVEH
tAVAV
WE (W)
(NOTE 3)
AIN
VIL
tEHAX
VIH
VIL
tEHWH
tWLEL
OE (G)
tEHGL
VIH
VIL
tEHEL
CE (E)
tEHQV 1, 2
tGHEL
VIH
VIL
tELEH
tEHDX
tDVEH
DATA (D/Q)
VIH
HIGH-Z
VIL
DIN
DIN
tPHEL
RY/BY (R)
DIN
DOUT
DIN
tEHRL
VOH
VOL
tRHPL
RP (P)
VIH
VIL
(NOTE 4)
tVPEH
VPP (V)
tQWL
VPPH
VPPL
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. RP low transition is only to show tRHPL; not valid for above Read and Write cycles.
28F004SUT-Z1-19
Figure 19. Alternate AC Waveforms for Command Write Operations
29
LH28F004SU-Z1
4M (512K × 8) Flash Memory
Erase and Byte Write Performance
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
TYP.(1)
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
tWHRH1
Byte Write Time
13
µs
2
tWHRH2
Two-Byte Serial Write Time
20
µs
2
tWHRH3
16KB Block Write Time
0.22
1.0
s
Byte Write Mode
2
tWHRH4
16KB Block Write Time
0.17
1.0
s
Two-Byte Serial Write Mode
2
Block Erase Time (16KB)
0.6
10
s
2
s
2, 3
Full Chip Erase Time
NOTES:
1. 25°C, VPP = 5.0 V
2. Excludes System-Level Overhead.
3. Depends on the number of protected blocks.
30
8.8 - 14.4
4M (512K × 8) Flash Memory
LH28F004SU-Z1
40TSOP (TSOP040-P-1020)
40
1
0.50 [0.020]
TYP.
10.20 [0.402]
9.80 [0.386]
0.25 [0.010]
0.15 [0.006]
20
21
1.10 [0.043]
0.90 [0.035]
SEE DETAIL
1.19
[0.047]
MAX.
0.49 [0.019]
0.39 [0.015]
DETAIL
0.125 [0.005]
18.60 [0.732]
18.20 [0.717]
19.30 [0.760]
18.70 [0.736]
0.49 [0.019]
0.39 [0.015]
20.30 [0.799]
19.70 [0.776]
DIMENSIONS IN MM [INCHES]
0.22 [0.009]
0.02 [0.001]
MAXIMUM LIMIT
MINIMUM LIMIT
0 - 10°
0.18 [0.007]
0.08 [0.003]
40TSOP
ORDERING INFORMATION
LH28F004SU
Device Type
T
Package
-Z1
Speed
100 Access Time (ns)
40-pin, 1.2 x 10 x 20 mm TSOP (Type I) (TSOP040-P-1020)
4M (512K x 8) Flash Memory
Example: LH28F004SUT-Z1 (4M (512K x 8) Flash Memory, 100 ns, 40-pin TSOP)
28F004SUT-Z1-20
31
LH28F004SU-Z1
4M (512K × 8) Flash Memory
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications
where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
WARRANTY
SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for
a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair
or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the
failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its
return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or
which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The
warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY
EXCLUDED.
SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility
for the use of any circuitry described; no circuit patent licenses are implied.
®
NORTH AMERICA
EUROPE
ASIA
SHARP Electronics Corporation
Microelectronics Group
5700 NW Pacific Rim Blvd., M/S 20
Camas, WA 98607, U.S.A.
Phone: (360) 834-2500
Telex: 49608472 (SHARPCAM)
Facsimile: (360) 834-8903
http://www.sharpmeg.com
SHARP Electronics (Europe) GmbH
Microelectronics Division
Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Telex: 2161867 (HEEG D)
Facsimile: (49) 40 2376-2232
SHARP Corporation
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: (07436) 5-1321
Telex: LABOMETA-B J63428
Facsimile: (07436) 5-1532
©1997 by SHARP Corporation
Issued July 1995
Reference Code SMT96109
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