GENESYS GL811E-MNNXX Usb 2.0 to ata / atapi bridge controller Datasheet

Genesys Logic, Inc.
GL811E
USB 2.0 to ATA / ATAPI
Bridge Controller
Datasheet
Revision 1.25
May. 03, 2006
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Copyright:
Copyright © 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be
reproduced in any form or by any means without prior written consent of Genesys Logic Inc..
Disclaimer:
ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY
KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF
GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND
CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR
EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND
NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC
BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING
FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS
MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE
MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE.
Trademarks:
is a registered trademark of Genesys Logic, Inc.
All trademarks are the properties of their respective owners.
Office:
Genesys Logic, Inc.
12F, No. 205, Sec. 3, Beishin Rd., Shindian City,
Taipei, Taiwan
Tel: (886-2) 8913-1888
Fax: (886-2) 6629-6168
http ://www.genesyslogic.com
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 2
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Revision History
Revision
Date
Description
1.00
06/13/2003
First formal release.
1.01
06/24/2003
Changed product name from GL811 to GL811E.
1.10
11/26/2003
2. Added 64 pin LQFP data in pinouts, pin description and package dimension.
1.11
11/27/2003
Changed pin# 38,39,21 name from IOADR0~2 to DA0~2.
1.20
05/05/2004
1.21
09/23/2004
1.22
12/29/2004
1.23
02/02/2005
1. Removed PIO mode description.
2. Changed package dimension
1. Added USB2.0 certified Test ID in Chapter 2 Features
2. Updated IC Marking in package dimension diagram
Added TQFP package information in Features, Package Dimension and
Ordering Information.
Changed IC marking in package dimension
1.24
10/14/2005
Add IDE Bus voltage tolerance information, table3.1, p.11~12
1.25
05/03/2006
Delete 48 Pin TQFP and 64 Pin TQFP Pinout/Package
1. Added some features in Chapter 2.
3. Added Chapter 8 “Ordering Infromation”.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 3
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
TABLE OF CONTENTS
CHAPTER 1
GENERAL DESCRIPTION................................................. 7
CHAPTER 2
FEATURES ........................................................................... 8
CHAPTER 3
PIN ASSIGNMENT .............................................................. 9
3.1 PINOUTS .................................................................................................. 9
3.2 PIN DESCRIPTIONS ................................................................................ 11
CHAPTER 4
BLOCK DIAGRAM............................................................ 13
CHAPTER 5
FUNCTION DESCRIPTION ............................................. 14
CHAPTER 6
ELECTRICAL CHARACTERISTICS.............................. 15
6.1 ABSOLUTE MAXIMUM RATINGS ............................................................ 15
6.2 TEMPERATURE CONDITIONS ................................................................. 15
6.3 DC CHARACTERISTICS.......................................................................... 15
6.3.1 I/O 8 Type digital pins (For pad type I/O 8 @ VCC=3.6V) ......... 15
6.3.2 I/O 16 Type digital pins (For pad type I/O 16 @ VCC=3.6V)...... 16
6.3.3 D+/ D- (For pad type u20mia @ VCC=3.6V)................................ 16
6.3.4 Switching Characteristics ............................................................ 16
6.4 AC CHARACTERISTICS- ATA/ ATAPI ................................................. 17
6.4.1 Register Transfers ........................................................................ 18
6.4.2 Multiword DMA data transfer .................................................... 19
6.4.3 Ultra DMA data transfer ............................................................. 23
6.5 AC CHARACTERISTICS - USB 2.0.......................................................... 30
CHAPTER 7
PACKAGE DIMENSION................................................... 31
CHAPTER 8
ORDERING INFORMATION........................................... 33
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 4
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
LIST OF FIGURES
FIGURE 3.1 - 48 PIN LQFP PINOUT DIAGRAM .................................................................9
FIGURE 3.2 - 64 PIN LQFP PINOUT DIAGRAM ...............................................................10
FIGURE 4.1 - BLOCK DIAGRAM ......................................................................................13
FIGURE 6.1 - INITIATING A MULTIWORD DMA DATA BURST ........................................20
FIGURE 6.2 - SUSTAINING A MULTIWORD DMA DATA BURST .......................................21
FIGURE 6.3 - DEVICE TERMINATING A MULTIWORD DMA DATA BURST ......................21
FIGURE 6.4 - HOST TERMINATING A MULTIWORD DMA DATA BURST ..........................22
FIGURE 6.5 - INITIATING AN ULTRA DMA DATA-IN BURST ...........................................24
FIGURE 6.6 - SUSTAINED ULTRA DMA DATA-IN BURST ................................................24
FIGURE 6.7 - HOST PAUSING AN ULTRA DMA DATA-IN BURST .....................................25
FIGURE 6.8 - DEVICE TERMINATING AN ULTRA DMA DATA-IN BURST.........................25
FIGURE 6.9 - HOST TERMINATING AN ULTRA DMA DATA-IN BURST ............................26
FIGURE 6.10 - INITIATING AN ULTRA DMA DATA-OUT BURST .....................................27
FIGURE 6.11 - SUSTAINED ULTRA DMA DATA-OUT BURST...........................................27
FIGURE 6.12 - DEVICE PAUSING AN ULTRA DMA DATA-OUT BURST ............................28
FIGURE 6.13 - HOST TERMINATING AN ULTRA DMA DATA-OUT BURST.........................29
FIGURE 6.14 - DEVICE TERMINATING AN ULTRA DMA DATA-OUT BURST ...................30
FIGURE 7.1 - GL811E 48 PIN LQFP PACKAGE ..............................................................31
FIGURE 7.3 - GL811E 64 PIN LQFP PACKAGE ..............................................................32
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 5
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
LIST OF TABLES
TABLE 3.1 - PIN DESCRIPTIONS ......................................................................................11
TABLE 6.1 - MAXIMUM RATINGS ...................................................................................15
TABLE 6.2 - TEMPERATURE CONDITIONS.......................................................................15
TABLE 6.3 - I/O 8 TYPE DIGITAL PINS (FOR PAD TYPE I/O 8 @ VCC=3.6V) ....................15
TABLE 6.4 - I/O 16 TYPE DIGITAL PINS (FOR PAD TYPE I/O 16 @ VCC=3.6V) ................16
TABLE 6.5 - D+/ D- (FOR PAD TYPE U20MIA @ VCC=3.6V) ............................................16
TABLE 6.6 - SWITCHING CHARACTERISTICS ..................................................................16
TABLE 6.7 - ULTRA DMA DATA BURST TIMING REQUIREMENTS ....................................23
TABLE 8.1 - ORDERING INFORMATION...........................................................................33
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 6
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
CHAPTER 1
GENERAL DESCRIPTION
The GL811E is a highly-compatible, low cost USB 2.0 to ATA / ATAPI bridge controller, which integrates
Genesys Logic own design high speed UTMI (USB 2.0 Transceiver Macrocell Interface) transceiver.
As a one-chip solution which complies with Universal Serial Bus specification rev. 2.0 and ATA / ATAPI-6
specification rev 1.0, the GL811E can support various kinds of ATA / ATAPI device. There are totally 4
endpoints in the GL811E controller, Control (0), Bulk In (1), Bulk Out (2), and Interrupt (3). By complies with
the USB Storage Class specification ver.1.0 (Bulk only protocol), the GL811E can support not only plug and
play but also Windows XP/ 2000/ ME default driver.
The GL811E uses 12MHz crystal and slew-rate controlled pads to reduce the EMI issue. With 48-pin LQFP
(9mmX9mm) package, the GL811E is the best cost/ performance solution to fit different situations in the USB
2.0 high speed storage class applications such as Hard Disk, CD-ROM, CD-R / RW and DVD-ROM.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 7
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
CHAPTER 2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
FEATURES
Complies with Universal Serial Bus specification rev. 2.0.
Complies with ATA/ATAPI-6 specification rev 1.0.
Complies with USB Storage Class specification ver.1.0. (Bulk only protocol)
Operating system supported: Win XP / 2000 / Me / 98 / 98SE; Mac OS 9.X / X.
Integrated USB 2.0 Transceiver Macrocell Interface (UTMI) transceiver and Serial Interface Engine (SIE).
USB 2.0 certified (TestID=40380268)
Supports 4 endpoints: Control (0) / Bulk Read (1) / Bulk Write (2) / Interrupt (3).
64 / 512 bytes Data Payload for full / high speed Bulk Endpoint.
Supports 16-bit Multiword DMA mode and Ultra DMA mode interface (Ultra 33 / 66).
Embedded 7.5 MIPS RISC CPU.
ROM size: 4k words; RAM size: 128 bytes.
Supports Power Down mode and USB suspend indicator.
Supports USB 2.0 TEST mode features.
Supports 2 GPIO (GPIO5 & 6) for programmable AP (only for 64 pin package).
Supports device power control for power on/off when running suspend mode (only for 64 pin package).
Supports 32 bit and 48 bit LBA hard disk.
Provides LED indicator for Full Speed and High Speed (only for 64 pin package).
12 MHz external clock to provide better EMI.
3.3V power input; 5V tolerance pad for IDE interface.
Supports Wakeup ability.
Available in 48-pin LQFP and 64-pin LQFP package.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 8
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
CHAPTER 3
PIN ASSIGNMENT
X2
12
CBLID_
25
X1
11
IODD[15]
26
AGND1
10
IODD[14]
27
TEST
9
IODD[13]
28
CS0_
8
IODD[12]
29
DA0
7
DGND1
30
DA1
6
DVCC1
31
INTRQ
5
IODD[11]
32
DMACK_
4
IODD[10]
33
IORDY
3
IODD[9]
34
DIOR_
2
IODD[8]
35
1
GPIO7
36
DIOW_
3.1 Pinouts
Figure 3.1 - 48 Pin LQFP Pinout Diagram
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 9
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
NC
49
32
X2
DMARQ
50
31
AVCC1
IODD0
51
30
RREF
IODD1
52
29
AGND0
IODD2
53
28
DMH
IODD3
54
27
DMF
DGND1
55
26
DPH
DVCC1
56
25
DPF
IODD4
57
24
AVCC0
23
RPU
GL811E
IODD5
58
IODD6
59
22
RESET#
IODD7
60
21
DA2
GPIO1
61
20
CS1_
PWR_CT
L
62
19
NC
F_LED
63
18
NC
H_LED
64
17
NC
LQFP - 64
Figure 3.2 - 64 Pin LQFP Pinout Diagram
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 10
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
3.2 Pin Descriptions
Table 3.1 - Pin Descriptions
Pin Name
48Pin# 64 Pin# I/O Type
GPIO7
1
1
B
(tri)
GPIO5~6
-
3,4
O
Description
GPIO7 (**)
AP programmable
IODD[8:11]
2~5
5~8
B
(tri)
DVCC1~2
6,43
56,9
P
Digital VCC
DGND1~2
7,42
55,10
P
Digital ground
IODD[12:15]
8~11
11~14
CBLID_
12
15
CS1_
13
20
DA2/SK
14
-
RESET#
15
22
RPU
16
23
A
3.3v output
17,24
24,31
P
Analog VCC
DPF
18
25
B
Full speed DP
DPH
19
26
B
High speed DP
DMF
20
27
B
Full speed DM
DMH
21
28
B
High speed DM
22,27
29,34
P
Analog ground
RREF
23
30
A
Reference resister connect (****)
X2
25
32
B
Crystal output
X1
26
33
TEST
28
-
CS0_
29
37
30,31
38,39
-
21
INTRQ
32
44
DMACK_
33
45
IORDY
34
46
I
I
(pd)
O
(tri)
O
(tri)
O
(tri)
I
(tri)
O
(tri)
I
(pu)
AVCC0~1
AGND0~1
DA0~1
DA2
B
(tri)
I
(tri)
O
(tri)
O
(tri)
I
(pu)
©2000-2006 Genesys Logic Inc. - All rights reserved.
IDE data bus 8~11 (*****)
IDE data bus 12~15 (*****)
Cable select input (*****)
Chip select 1 (*****)
IDE address 2 / Serial data clock for EEPROM (*****)
Reset pin (***)
Crystal input, 12Mhz
TEST mode input
Chip select 0 (*****)
IDE address 0~1 (*****)
IDE address 2 (*****)
IDE interrupt input (*****)
IDE acknowledge (*****)
IDE ready (*****)
Page 11
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
DIOR_
35
47
DIOW_
36
48
DMARQ
37
50
IODD[0:3]
38~41
51~54
IODD[4:7]
44~47
57~60
48
61
PWR_CTL
-
62
O
(tri)
O
(tri)
I
(pd)
B
(tri)
B
(tri)
B
(tri)
O
F_LED
-
63
O
H_LED
-
64
O
GPIO1
IDE read signal (*****)
IDE write signal (*****)
IDE request (*****)
IDE data bus 0~3 (*****)
IDE data bus 4~7 (*****)
GPIO1
Power control
Full speed LED
High speed LED
2,16~19,
NC
No connection
35,49,
(*) The different of I/O 8 type from I/O 16 type is the typical drive current. The typical drive current of
I/O 8 type is 8 mA, and for I/O pad 16 is 16 mA.
(**) When operating in default mode: GPIO7 is the ATA/ ATAPI reset input , 5V tolerance.
(***) When Reset pin is pulled low, the IDE bus will be in tri-state.
(****) RREF must be connected with a 510 ohm resister to ground.
(*****) 5V tolerance
Notation:
Type
O
I
B
B/I
B/O
P
A
SO
pu
pd
odpu
tri
Output
Input
Bi-directional
Bi-directional, default input
Bi-directional, default output
Power / Ground
Analog
Automatic output low when suspend
Internal pull up
Internal pull down
Open drain with internal pull up
Tri-state
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 12
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
CHAPTER 4
DMACK_
DIOR_
DIOW_
CS1_,
CS0_
DA2
DA1
DA0
BLOCK DIAGRAM
CLK15
GPIO1
CPU
Control Register
GPIO7
RPU
8
CONTROL FIFO
CLK30
DPF
RXSTS
TXFIFO0
IODD15-0
8/16-Bit
INTRQ
CBLID_
DMARQ
IORDY
IDE
4
DPH
TXFIFO1
SIE
TXCTL
Engine
UTMI
USB2.0
LOGIC TXCVR
DMF
16
RXFIFO0
DMH
12-96MHz
DATA
RXFIFO1
X10
12MHz
RREF
Clkgen
X40
Figure 4.1 - Block Diagram
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 13
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
CHAPTER 5
FUNCTION DESCRIPTION
1. USB 2.0 TXCVR
The USB 2.0 Transceiver is the analog circuitry to handle the USB HS/FS signaling.
2. UTMI (USB 2.0 Transceiver Macrocell Interface) Logic
The UTMI Logic is compliant to Intel’s UTMI specification 1.01. This block handles the low level USB
protocol and signaling. The major jobs of UTMI Logic is data and clock recovery, NRZI encoding/decoding,
Bit Stuffing/De-stuffing, USB2.0 test modes supporting and serial / parallel conversion.
3. SIE (Serial Interface Engine)
The SIE contains the USB packet ID and address recognition logic, and other sequencing and state machine
logic to handle USB packets and transactions.
4. PLL
10XPLL provides the 120MHz clock output for UTMI Logic block. UTMI operates in 120MHz for USB HS
data processing. 40XPLL block will provide 480MHz for USB HS data transmission.
5. CLKGEN
CLKGEN is the clock generator block for the logic blocks. It generates 15MHz clock for micro controller,
48MHz for MDMA mode, 96MHz for UDMA mode, and 30MHz clock for UTMI, SIE, and FIFO.
6. CPU
The CPU is the control center of GL811E. It’s an 8-bit micro controller operating in 15MHz, 7.5 MIPS. After
receiving a USB command, it decodes the host command, then it re-assigns tasks to the IDE engine, GPIO,
FIFO, and response proper data/status to USB host.
7. IDE Engine
The IDE engine is extended from standard ATA / ATAPI protocol. It supports multiword DMA mode, and ultra
DMA mode data transfers.
8. FIFOs
Control FIFO is used as Control Read / Write FIFO. TXFIFO0 / TXFIFO1 are two sets of 512-byte ping-pong
FIFO for Bulk Read endpoint. It buffers data from IDE engine, and re-direct to USB SIE logic. RXFIFO0 /
RXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Write endpoint. It buffers data from USB SIE
logic, and re-direct to IDE engine.
9. Control Registers
Control Register configures GL811E to proper operation. For example, CPU can set register to generate
wakeup event, enter suspend, transmits proper USB packet to host.
10. ATA/ATAPI
The GL811E complies with ATA/ATAPI-6 specification rev. 1.0. Please refer to the specifications for more information.
11. USB 2.0
The GL811E complies with Universal Serial Bus specification rev. 2.0, and it integrates Genesys Logic own
design UTMI transceiver that fully complies with the USB 2.0 Transceiver Macercell Interface (UTMI)
specification rev. 1.01. Please refer to the specifications for more information.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 14
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
CHAPTER 6
ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings
Table 6.1 - Maximum Ratings
Symbol
Parameter
Min.
Max.
Unit
VCC
DC supply voltage
+3.0
+3.6
V
VI
DC input voltage
-0.3
VCC + 0.3
V
VI/O
DC input voltage range for I/O
-0.3
VCC + 0.3
V
VAI/O
DC input voltage for USB D+/D- pins
-0.3
VCC + 0.3
V
VESD
Static discharge voltage
4000
TA
Ambient Temperature
V
0
100
o
C
6.2 Temperature Conditions
Table 6.2 - Temperature Conditions
Item
Value
Storage Temperature
-50oC ~ 150 oC
Operating Temperature
0 oC ~ 70 oC
6.3 DC Characteristics
6.3.1 I/O 8 Type digital pins (For pad type I/O 8 @ VCC=3.6V)
Table 6.3 - I/O 8 Type digital pins (For pad type I/O 8 @ VCC=3.6V)
Parameter
Min.
Typ.
Max.
Unit
Current sink @ VOL = 0.4V
7.79
10.83
14.09
mA
Current output @ VOH = 2.4V (TTL high)
16.36
19.87
23.39
mA
Falling slew rate at 30 pF loading capacitance
0.26
0.50
0.80
V/ns
Rising slew rate at 30 pF loading capacitance
0.30
0.57
0.91
V/ns
1.64
V
Input high threshold voltage
Input low threshold voltage
Hysteresis voltage
Leakage current for pads with internal pull up or pull
down resistor
1.36
-
V
0
-
V
46
µA
Pad internal pull down resister
51K
105K
152K
Ohms
Pad internal pull up resister
85K
168K
251K
Ohms
109
mA
Supply current
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 15
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
6.3.2 I/O 16 Type digital pins (For pad type I/O 16 @ VCC=3.6V)
Table 6.4 - I/O 16 Type digital pins (For pad type I/O 16 @ VCC=3.6V)
Parameter
Min.
Typ.
Max.
Unit
Current sink @ VOL = 0.4V
16.20
21.90
27.68
mA
Current output @ VOH = 2.4V (TTL high)
24.13
29.46
34.80
mA
Falling slew rate at 30 pF loading capacitance
0.51
0.93
1.35
V/ns
Rising slew rate at 30 pF loading capacitance
0.46
0.83
1.27
V/ns
2.15
V
Input high threshold voltage
Input low threshold voltage
0.89
Pad internal pull down resister
51K
V
105K
152K
Ohms
Max.
Unit
6.3.3 D+/ D- (For pad type u20mia @ VCC=3.6V)
Table 6.5 - D+/ D- (For pad type u20mia @ VCC=3.6V)
Parameter
Min.
Typ.
D+/D- static output LOW (RL of 1.5K to VCC )
0
0.3
V
D+/D- static output HIGH (RL of 15K to GND )
2.8
3.6
V
Differential input sensitivity
0.2
Single-ended receiver threshold
0.8
V
Transceiver capacitance
2.0
V
20
pF
Hi-Z state data line leakage
-10
+10
µA
Driver output resistance
28
43
Ohms
6.3.4 Switching Characteristics
Table 6.6 - Switching Characteristics
Parameter
X1 crystal frequency
Min.
Typ.
Max.
Unit
11.97
12
12.03
MHz
X1 cycle time
83.3
ns
D+/D- rise time with 50pF loading
4
20
ns
D+/D- fall time with 50pF loading
4
20
ns
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 16
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
6.4 AC Characteristics- ATA/ ATAPI
The GL811E complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes:
1.
DMA (Direct Memory Access) data transfer:
DMA data transfer means of data transfer between device and host memory without host processor
intervention.
- Multiword DMA: Multiword DMA is a data transfer protocol used with the READ DMA, WRITE
DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When a
Multiword DMA transfer is enabled as indicated by IDENTIFY DEVICE or IDENTIFY PACKET
DEVICE data, this data transfer protocol shall be used for the data transfers associated with these
commends. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.)
- Ultra DMA: Ultra DMA Is a data transfer protocol used with the READ DMA, WRITE DMA,
READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When this protocol is
enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these
commands are issued by the host. This protocol applies to the Ultra DMA data burst only. (Please
refer to the ATA / ATAPI-6 specification rev 1.0 for more information.)
Following listed the symbols and their respective definitions that are used in the timing diagram:
-
Signal transition (asserted or negated)
-
Data transition (asserted or negated)
-
Data valid
-
Undefined but not necessarily released
-
Asserted, negated or released
-
Released
-
The “other” condition if a signal is shown with no change
All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown
towards the bottom of the page relative to the asserted condition.
The interface uses a mixture of negative and positive signals for control and data. The terms asserted and
negated are used for consistency and are independent of electrical characteristics.
In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following
illustrates the representation of a signal named Test going from negated to asserted and back to negated, based
on the polarity of the signal.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 17
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
6.4.1 Register Transfers
Notes:
1. Device address consists of signals CS0_, CS1_ and DA(2:0).
2. Data consists of IODD(7:0).
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of
whether the cycle is to be extended is made by the host after tA from the assertion of DIOR_ or DIOW_.
The assertion and negation of IORDY are described as following:
3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3.2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released
prior to negation and may be asserted for no more than 5 ns before release: no wait generated.
3.3 Device negates IORDY before tA, IORDY is released prior to negation and may be asserted for no
more than 5 ns before release: wait generated. The cycle completes after IORDY is released. For
cycles where a wait is generated and DIOR_ is asserted, the device shall read data on IODD(0:7) for
tRD before asserting IORDY.
4. DMACK_ shall remain negated during a register transfer.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 18
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Register transfer timing parameters
Timing (ns)
t0
Cycle time
2000
t1
Address valid to DIOR_/ DIOW_ setup
1000
t2
DIOR_/ DIOW_ pulse width 8-bit
300
t2i
DIOR_/ DIOW_ recovery time
900
t3
DIOW_ data setup
80
t4
DIOW_ data hold
40
t5
DIOR_ data setup
-
t6
DIOR_ data hold
-
t6Z
DIOR_ data tristate
-
t9
DIOR_/ DIOW_ to address valid hold
Read Data Valid to IORDY active
(if IORDY initially low after tA)
tRD
900
tA
IORDY Setup time
-
tB
IORDY Pulse Width
-
tC
IORDY assertion to release (max)
-
6.4.2 Multiword DMA data transfer
Register transfer timing parameters
Timing (ns)
t0
Cycle time
120
tD
DIOR_/ DIOW_ asserted pulse width
80
tE
DIOR_ data access
-
tF
DIOR_ data hold
-
tG
DIOR_/ DIOW_ data setup
40
tH
DIOW_ data hold
18
tI
DMACK to DIOR_/ DIOW_ setup
18
tJ
DIOR_/ DIOW_ to DMACK hold
20
tKR
DIOR_ negated pulse width
36
tKW
DIOW_ negated pulse width
36
tLR
DIOR_ to DMARQ delay
-
tLW
DIOW_ to DMARQ delay
-
tM
CS(1:0) (max) valid to DIOR_/ DIOW_
36
tN
CS(1:0) hold
18
tZ
DMACK_ to read data released
©2000-2006 Genesys Logic Inc. - All rights reserved.
-
Page 19
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Note:
The host shall not assert DMACK_ or negate both CS0_ and CS1_ until the assertion of DMARQ is detected.
The maximum time from the assertion of DMARQ to the assertion of DMACK_ or the negation of both CS0_
and CS1_ is not defined.
Figure 6.1 - Initiating a Multiword DMA Data Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 20
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Figure 6.2 - Sustaining a Multiword DMA Data Burst
Note:
To terminate the data burst, the Device shall negate DMARQ within the tL of the assertion of the current
DIOR_ or DIOW_ pulse. The last data word for the burst shall then be transferred by the negation of the
current DIOR_ or DIOW_ pulse. If all data for the command has not been transferred, the device shall reassert
DMARQ again at any later time to resume the DMA operation.
Figure 6.3 - Device Terminating a Multiword DMA Data Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 21
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Note:
1. To terminate the transmission of a data burst, the Host shall negate DMACK_ within the specified time
after a DIOR_ or DIOW_ pulse. No further DIOR_ or DIOW_ pulses shall be asserted for this burst.
2.
If the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait
for the host to reassert DMACK_ or may negate DMARQ at any time after detecting that DMACK_
has been negated.
Figure 6.4 - Host terminating a Multiword DMA Data Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 22
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
6.4.3 Ultra DMA data transfer
Table 6.7 - Ultra DMA data burst timing requirements
Mode 0
(in ns)
Name
min
max
Mode 1
(in ns)
min
max
Mode 2
(in ns)
min
max
Mode 3
(in ns)
min
max
Mode 4
(in ns)
Min
Comment
max
Typical sustained average
two cycle time
Cycle time allowing for
asymmetry and clock
variations
Two cycle time allowing
for clock variations
Data setup time at
recipient
t2CYCTYP
240
160
120
90
60
tCYC
112
73
54
39
25
t2CYC
230
154
115
86
57
tDS
15
10
7
7
5
tDH
5
5
5
5
5
tDVS
70
48
30
20
6
tDVH
6
6
6
6
6
tFS
0
230
0
200
0
170
0
130
0
120
Data valid setup time at
sender
Data valid hold time at
sender
First STORBE time
tLI
0
150
0
150
0
150
0
100
0
100
Limited interlock time
tMLI
20
20
20
20
20
tUI
0
0
0
0
0
tAZ
10
10
10
10
20
20
20
20
20
tZAD
0
0
0
0
0
tENV
20
20
70
20
70
20
55
Interlock time with
minimum
Unlimited interlock time
10
tZAH
70
Data hold time at recipient
20
Drivers to assert or negate
55
tSR
50
30
20
NA
NA
tRFS
75
70
60
60
60
tRP
160
tIORDYZ
125
20
100
20
100
20
100
20
20
tZIORDY
0
0
0
0
0
tACK
20
20
20
20
20
tSS
50
50
50
50
50
©2000-2006 Genesys Logic Inc. - All rights reserved.
Maximum time allowed
for output drivers to
release
Minimum delay time
required for output
Envelope time
STROBE to DMARDY_
time
Ready to final STROBE
time
Minimum time to assert
STOP or negate DMARQ
Maximum time before
releasing IORDY
Minimum time before
driving STROBE
Setup and hold times for
DMACK_
Time from STROBE edge
to negation of DMARQ or
assertion of STOP
Page 23
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are not in efficient until DMARQ and DMACK are asserted.
Figure 6.5 - Initiating an Ultra DMA Data-In Burst
Notes:
IODD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling
time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until
some time after they are driven by the device.
Figure 6.6 - Sustained Ultra DMA Data-In Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 24
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Notes:
1. The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after
HDMARDY_ is negated.
2. If the tSR timing is not satisfied, the host may receive zero, one, or two more data words from the device.
Figure 6.7 - Host Pausing an Ultra DMA Data-In Burst
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are
negated.
Figure 6.8 - Device Terminating an Ultra DMA Data-In Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 25
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are
negated.
Figure 6.9 - Host Terminating an Ultra DMA Data-In Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 26
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.
Figure 6.10 - Initiating an Ultra DMA Data-Out Burst
Notes:
IODD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling
time as well as cable propagation delay shall not allow the data signals to be considered stable at the devicet
until some time after they are driven by the host.
Figure 6.11 - Sustained Ultra DMA Data-Out Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 27
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Notes:
1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after
DDMARDY_ is negated.
2. If the tSR timing is not satisfied, the device may receive zero, one, or two more data words from the host.
Figure 6.12 - Device Pausing an Ultra DMA Data-Out Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 28
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are
negated.
Figure 6.13 - Host terminating an Ultra DMA data-out burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 29
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are
negated.
Figure 6.14 - Device Terminating an Ultra DMA Data-Out Burst
6.5 AC Characteristics - USB 2.0
The GL811E conforms to all timing diagrams and specifications for Universal Serial Bus specification rev. 2.0.
Please refer to this specification for more information.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 30
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
CHAPTER 7
PACKAGE DIMENSION
D
D1
A
D2
A2
D
37
24
N : Normal package
G : Green package
Internal No.
GL811E
A
B
AAAAAAAGAA
YWWXXXXXXXX
Date Code
Version
No.
Lot Code
48
13
12 4X
1
e
0- 1
4X
b
aaa C A B D
bbb H A B D
C
ccc C
0- 2
R1
R2
GAGE PLANE
0.25mm
S
L
0- 3
NOTES :
1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm
PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY
SIZE DIMENSIONS INCLUDING MOLD MISMATCH.
2. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE
MAXIMUM b DIMENSION BY MORE THAN 0.08mm.
DAMBAR CAN NOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN
PROTRUSION AND AN ADJACENT LEAD IS 0.07mm.
c
ddd M C A B s D s
0-
H
A1
25
36
SEATING
PLANE
CONTROL DIMENSIONS ARE IN MILLIMETERS.
MILLIMETER
INCH
SYMBOL
MIN. NOM. MAX. MIN. NOM. MAX.
A
1.60
0.063
A1
0.05
0.15 0.002
0.006
1.35
A2
1.40
1.45 0.053 0.055 0.057
D
9.00 BASIC
0.354 BASIC
E
9.00 BASIC
0.354 BASIC
D1
7.00 BASIC
0.276 BASIC
E1
7.00 BASIC
0.276 BASIC
D2
5.50 BASIC
0.217 BASIC
E2
5.50 BASIC
0.217 BASIC
R1
0.08
0.003
R2
0.08
0.20 0.003
0.008
0°
3.5°
7°
0°
3.5°
7°
0-01
0°
0°
-02
11°
12°
13°
11°
12°
13°
-03
11°
12°
13°
11°
12°
13°
c
0.09
0.20 0.004
0.008
L
0.45
0.60
0.75 0.018 0.024 0.030
L1
1.00 REF
0.039 REF
S
0.20
0.008
b
0.17
0.20
0.27 0.007 0.008 0.011
e
0.50 BASIC
0.020 BASIC
TOLERANCES OF FORM AND POSITION
aaa
0.20
0.008
bbb
0.20
0.008
ccc
0.08
0.003
ddd
0.08
0.003
Figure 7.1 - GL811E 48 Pin LQFP Package
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 31
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
D
D1
A
D2
A2
D
48
49
32
N : Normal package
G : Green package
InternalNo
.
A
A1
33
B
GL811E
AAAAAAAGAA
YWWXXXXXXXX
Date Code
Version
No.
Lot Code
17
64
16 4X
1
4X
e
0-1
b
aaa C A B D
bbb H A B D
c
ddd M C A B s D s
0-
C
SEATING
PLANE
ccc C
0-2
R1
R2
H
GAGE PLANE
0.25mm
S
L
0-3
NOTES :
1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm
PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY
SIZE DIMENSIONS INCLUDING MOLD MISMATCH.
2.
DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE
MAXIMUM b DIMENSION BY MORE THAN 0.08mm.
DAMBAR CAN NOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN
PROTRUSION AND AN ADJACENT LEAD IS 0.07mm.
CONTROL DIMENSIONS ARE IN MILLIMETERS.
MILLIMETER
INCH
SYMBOL
MIN. NOM. MAX. MIN. NOM. MAX.
A
1.60
0.063
A1
0.05
0.15 0.002
0.006
1.35
A2
1.40
1.45 0.053 0.055 0.057
D
12.00 BASIC
0.472 BASIC
E
12.00 BASIC
0.472 BASIC
D1
10.00 BASIC
0.393 BASIC
E1
10.00 BASIC
0.393 BASIC
D2
7.50 BASIC
0.295 BASIC
E2
7.50 BASIC
0.295 BASIC
R1
0.08
0.003
R2
0.08
0.20 0.003
0.008
0
3.5
7
0
3.5
7
00
0
0- 1
0- 2
11
12
13
11
12
13
0- 3
11
12
13
11
12
13
c
0.09
0.20 0.004
0.008
L
0.45
0.60
0.75 0.018 0.024 0.030
L1
1.00 REF
0.039 REF
S
0.20
0.008
b
0.17
0.20
0.27 0.007 0.008 0.011
e
0.50 BASIC
0.020 BASIC
TOLERANCES OF FORM AND POSITION
aaa
0.20
0.008
bbb
0.20
0.008
ccc
0.08
0.003
ddd
0.08
0.003
Figure 7.3 - GL811E 64 Pin LQFP Package
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 32
GL811E USB 2.0 to ATA/ATAPI Bridge Controller
CHAPTER 8
ORDERING INFORMATION
Table 8.1 - Ordering Information
Part Number
Package
Normal/Green
Version
Status
GL811E -MSNXX
64-pin LQFP
Normal Package
XX
Available
GL811E -MNNXX
48-pin LQFP
Normal Package
XX
Available
GL811E -MSGXX
64-pin LQFP
Green Package
XX
Available
GL811E -MNGXX
48-pin LQFP
Green Package
XX
Available
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 33
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