NCP5810D Dual 1 W Output AMOLED Driver Supply The NCP5810D is a dual-output DC/DC converter which can generate both a positive and a negative voltage. Both PWM converters achieve high efficiency for portable application. Thanks to the high output voltage accuracy and signal integrity the NCP5810D is particularly suitable for powering applications such as AMOLED display drivers. The output voltage of the inverter is fully configurable using external feedback resistors, where the output voltage of the boost is internally fixed. The switching regulator operates at 1.75MHz which allows the use of small inductors and ceramic capacitors. In addition both converters are internally compensated which simplifies the design and reduces the PCB component count. Cycle-by-cycle peak current limit and thermal shut down provide value added features to protect the device. The NCP5810D is housed in low profile space-efficient 3x3 mm UDFN package. http://onsemi.com 1 12 PIN UDFN MU SUFFIX CASE 517AM MARKING DIAGRAM Features 5810D AYWG G •High Overall Efficiency: 83% (Refer to Figure 4) •Low Noise 1.75 MHz PWM DC/DC Converter •Positive Output Fixed + 4.6 V •Negative Output from - 2.0 to - 15.0 V •High Output Voltage Accuracy •Excellent Line Transient Rejection •Soft Start to Limit Inrush Current •Enable Control Facility with True-Cutoff •Out-of-Regulation Protection •Small UDFN 3x3 mm Packages •These are Pb-Free Devices 5810D = Device Code A = Assembly Location Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) VOUTP 1 12 LXP SWP 2 11 PVIN Typical Applications PGND 3 10 SWN •AMOLED Driver Supply AGND 4 9 EN VREF 5 8 AVIN VS 6 7 FBN NCP5810D ♦Cellular Phones ♦Digital Cameras ♦Personal ♦GPS Digital Assistant and Portable Media Player (Top View) 12-pin 3 x 3 x 0.55 mm UDFN Exposed pad must be soldered to PCB Ground plane ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. © Semiconductor Components Industries, LLC, 2008 March, 2008 - Rev. P2 1 Publication Order Number: NCP5810D/D NCP5810D L1 4.7 mH VBAT U1 12 LXP 11 PVIN SWP VOUTP C1 4.7 mF 3 ENABLE 9 8 VOUTP 1 C3 4.7 mF PGND NCP5810D EN VS 6 AVIN D1 C2 1 mF 4 FBN AGND VREF VBAT 2 5 SWN 7 C4 4.7 mF L2 4.7 mH R2 56 k C5 0.1 mF D1: ON NSR0320MW2 L1, L2: TDK VLF3010AT-4R7 C1: 4.7 mF 6.3 V X5R C2: 1 mF 6.3 V X5R 0603 C1,C3,C4: 4.7 mF 6.3 V X5R 0805 VOUTN 10 R1 536 k C6 10 pF Figure 1. Typical Application Circuit Option of powering CINP 4.7 mF Vbat L1 4.7 mH CINA 1 mF AVIN PVIN D2 SWP LXP VOUTP Thermal Shut down VOUTP MP0 COUTP 4.7 mF ENABLE BOOST PWM CONTROLLER EN Bangap 1.26 V MN1 Osc 1.75 Mhz VS MP1 SWN NEGATIVE BUCK PWM CONTROLLER D1 VOUTN 4.7 mH L2 Verf 1.26 V COUTN 4.7 mF R1 AGND FBN PGND VREF 0.1 mF Figure 2. Simplified Block Diagram http://onsemi.com 2 R2 10 pF NCP5810D PIN FUNCTION DESCRIPTION Pin Pin Name Type Description 1 VOUTP OUTPUT Positive Power Output: A filter capacitor is necessary on this pin for the stability of the loop, to smooth the current flowing into the load, and limit the noise created by the fast transients present in this circuitry. A 4.7 mF ceramic bypass capacitor to GND is recommended. Care must be observed to avoid EMI through the PCB copper tracks connected to this pin. 2 SWP POWER Switch LXP: Positive power switch pin where one end of the L1 inductor is connected. Typical ap‐ plication uses a 4.7 mH inductor. 3 PGND POWER Power Ground: This pin is the power ground and carries the high switching current. A high quality ground must be provided to avoid any noise spikes/uncontrolled operation. Care must be observed to avoid high-density current flow in a limited PCB copper track. 4 AGND POWER Analog Ground: This pin is the analog ground of the device notably used by VREF. 5 VREF OUTPUT Voltage Reference: This output provides a 1.265 V voltage reference used notably for the negative feedback resistive network. 6 VS INPUT Positive Output Voltage Sense: This pin is the output voltage sense input for the positive boost converter and must be connected to COUTP bypass capacitor. 7 FBN INPUT Feedback Negative: This pin is the feedback voltage input for the negative Buck-Boost inverter. The middle point of a resistive bridge divider must be connected here. The resistive network must be con‐ nected between VREF and the anode of external Schottky. 8 AVIN POWER Analog Power Supply: The external voltage supply is connected to this pin. A 4.7 mF ceramic ca‐ pacitor must be connected across this pin and the power ground to achieve the specified output pow‐ er parameters. 9 EN INPUT Enable: An active high logic level on this pin enables the circuit. A built-in pull-down resistor disables the device if the pin is left open. Also in disable condition the device provides a true cut-off from PVIN to VOUTP and SWN. 10 SWN INPUT Switch Negative: Negative power switch pin where one end of the L2 inductor is connected. Typical application uses a 4.7 mH inductor. 11 PVIN POWER Power Supply: This pin is the power supply of the device. A 4.7 mF ceramic capacitor or larger must bypass this input to the ground. This capacitor should be placed as close as possible to this input. 12 LXP POWER Switch LXP: The inductor should be connected between this node and SWP. This output supplies power from PVIN and gives a true-cut off function in disable condition. http://onsemi.com 3 NCP5810D MAXIMUM RATINGS (Note 1) Symbol Value Unit AVIN and PVIN Pin: Power Supply Voltage (Note 2) VBAT 7.0 V EN Pin: Digital Logic Input (Note 2) VEN -0.3 ≤ VIN ≤ VBAT +0.3 V LXP Pin: Output (Note 2) VLXP -0.3 ≤ VIN ≤ VBAT +0.3 V VREF Pin: Output Reference Voltage (Note 2) VVREF -0.3 ≤ VIN ≤ VBAT +0.3 V VVS +17 V SWN Pin: Output (Note 2) VSWN -17 V SWP Pin: Input (Note 2) VSWP 9.8 V VVOUTP +17 V VFBN -0.3 ≤ VIN ≤ VBAT +0.3 V Human Body Model (HBM) ESD Rating are (Note 3) ESD HBM 2000 V Machine Model (MM) ESD Rating are (Note 3) ESD MM 200 V EN -0.3 ≤ VIN ≤ VBAT +0.3 1 V mA RqJC 12 °C/W Rating VS Pin: Input (Note 2) VOUTP Pin: Output (Note 2) FBN Pin: Input (Note 2) Digital Input Voltage Digital Input Current UDFN 3x3 mm package (Notes 6 and 7) Thermal Resistance Junction-to-Case Operating Ambient Temperature Range TA -40 to +85 °C Operating Junction Temperature Range TJ -40 to +125 °C Maximum Junction Temperature TJMAX +150 °C Storage Temperature Range TSTG -65 to +150 °C Moisture Sensitivity (Note 5) MSL Level 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTES: 1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25°C 2. According to JEDEC standard JESD22-A108B. 3. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22-A114 for all pins. Machine Model (MM) ±200 V. 4. Latchup Current Maximum Rating: ±100 mA per JEDEC standard: JESD78., class II 5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J-STD-020A. 6. The thermal shutdown set to 165°C (typical) avoids irreversible damage on the device due to power dissipation. 7. The RqCA is dependent on the PCB heat dissipation. The maximum power dissipation (PD) is dependent on the min input voltage, the max output current and external components selected. RqCA + 125 * TA * R qJC PD http://onsemi.com 4 NCP5810D ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between -40°C to +85°C and VIN between 2.7 V to 4.6 V (Unless otherwise noted). Typical values are referenced to TA = +25°C and VIN = 3.7 V (Unless otherwise noted) Characteristic Symbol Min Typ Max Unit VOUTP 4.55 4.6 4.65 V IPEAKP_MAX 630 800 900 mA Switches P0 ON Resistance P0MOS RDSON - 320 640 mW Switches N1 ON Resistance N1MOS RDSON - 300 600 mW N1MOS L - 0.05 0.5 mA EFF - 85 - % - 270 - 230 200 BOOST REGULATOR Positive Operational Output Voltage Range Maximum Inductor Peak Current Switches N1 Leakage Current At VIN = 4.2 V Efficiency (Notes 8, 9) VOUTP Range Load Current (Notes 9, 10) IOUTP VIN ≥ 3.2 V, TA between 0 to +85°C VIN ≥ 2.9 V, TA between 0 to +85°C mA Output Voltage Line Regulation IOUTP = 0 mA 2.7 < VIN < 4.6 LINE_RP - - 10 mV Output Voltage Line Transient Overshoot (Note 12) LINE_TP - 4.0 - mV Power Supply Ripple Rejection (Notes 9, 13) 1.0 Hz to 1.0 kHz 1.0 kHz to 10 kHz PSRRP - 60 40 - LOAD_RP - - 0.5 %/100mA LTRP - - 100 mV VOUTN -15 - -2.0 V IPEAKN_MAX 720 900 1020 mA P2MOS RDSON - 1.0 2.0 W P2MOS L - 0.05 0.5 mA EFF - 80 - % - 1000 - 800 700 Output Voltage Load Regulation (Note 14) Output Voltage Load Transient Response: Overshoot and Undershoot Vs. Steady State Voltage (Notes 9, 15) dB BUCK/BOOST REGULATOR Typical Negative Operational Output Voltage Range Peak Inductor Current (Note 9) Switches P2 ON Resistance Switches P2 Leakage Current At VIN = 4.2 V Efficiency (Notes 8, 9) VOUTN Range Load Power (Notes 9, 10) POUTN VIN ≥ 3.2 V, TA between 0 to +85°C VIN ≥ 2.9 V, TA between 0 to +85°C mW Output Voltage Reference 0 mA < IREF < 100 mA OVR -1 % 1.265 +1 % V Feedback Voltage Threshold in Steady State: 2.7 < VIN < 4.6 FBVN -2 % 0.632 +2 % mV Feedback Input Current FBICN -50 - 50 nA Output Voltage Line Regulation at IOUTN = 0 mA (Note 11) 2.7 < VIN < 4.6 LINE_RN - - 20 mV Output Voltage Line Transient Overshoot (Note 12) LINE_TN - 4.0 - mV Power Supply Ripple Rejection (Notes 9, 13) 1.0 Hz to 1.0 kHz 1.0 kHz to 10 kHz PSRRN - 60 40 - LOAD RN - - 0.5 %/100mA LTRN - - 100 mV Load Regulation (Notes 11, 14) Load Transient Response: Overshoot and Undershoot Vs. Steady State Voltage (Notes 9, 15) http://onsemi.com 5 dB NCP5810D ELECTRICAL CHARACTERISTICS (Min & Max Limits apply for TA between -40°C to +85°C and VIN between 2.7 V to 4.6 V. Typical values are referenced to TA = +25°C and VIN = 3.7 V, unless otherwise noted) Rating Symbol Min Typ Max Unit VIN 2.7 - 4.6 V Internal Oscillator Frequency, TA = 25°C, VIN = 3.7V FOSC 1.6 1.75 1.9 MHz Maximum Duty Cycle MDCY 87 90 - % Stand by Current at IOUTP = IOUTN = 0 mA, EN = Low VIN = 4.2 V, TA = +25°C ISTB - - 2.0 mA Quiescent Current @ VOUTN = -5.4 V @ TA = +25°C Switching (Note 9) No Switching IQ - 1.5 1.0 3.0 - Operational Power Supply mA Soft Start Time to limit the Inrush Current SST - 2.0 - ms Thermal Shut Down Protection TSD - 165 - °C Thermal Shut Down Protection Hysteresis TSDH - 15 - °C VIL - - 0.4 V Voltage Input Logic Low Voltage Input Logics High VIH 1.2 - - V EN pin Pull Down Resistance REN 280 400 670 kW NOTES: 8. Efficiency is defined by 100 * (Pout / Pin), Vin = 3.1 to 4.2 V, L = VLF3010AT-4R7MR70 (DCR = 280 mW max, Isat = 700 mA), Load = 15 to 30mA, Voutn = -5.4 V. 9. Guaranteed by design and characterized. 10. Typical application circuit and components depicted Figure 1. 11. Tested at 25°C and guaranteed from -40°C to +85°C by characterization. 12. Line drop and rise between 3.4 to 2.9 V in 50 ms at IOUT = 25 mA, VOUTN = -5.4 V. 13. Ripple = 0.2 V p-p at 25°C, Cout = 4.7 mF, IOUT = 0 to 100 mA, VIN = 3.7 V. 14. IOUT from 0 to 100 mA. 15. Load step 10 to 90 mA and 90 to 10 mA, rising and falling edge in 10 ms, Cout = 4.7 mF, VIN = 3.7 V. 16. Maximum range load (IOUTN_MAX) is dependent by the output voltage setup (VOUTN), POUTN for a given condition and work out by equation below. IOUTN_MAX + P OUTN V OUTN For example, should one need setup - 4.9 for VOUTN, at VIN ≥ 3.2 V, IOUTN_MAX + 0.8 + 163mA 4.9 http://onsemi.com 6 NCP5810D TYPICAL OPERATING CHARACTERISTICS 80 80 VIN = 3.7 V EFFICIENCY (%) EFFICIENCY (%) VIN = 4.5 V 70 VIN = 3.7 V VIN = 2.9 V 60 VOUTN = -5.4 V 50 0 50 100 150 200 70 VIN = 2.9 V 60 VOUTN = -5.4 V 50 250 0 50 100 150 200 IOUT (mA) IOUT (mA) Figure 3. Efficiency vs. IOUT Figure 4. Efficiency vs. IOUT, L = MARUWA CXFU0208-4R7 plus Optional D2 NSR0320MW2 L = MARUWA CXFU0208-4R7 250 Figure 5. Line Transient Response VOUTP at 100mA Figure 6. Line Transient Response VOUTN = -5.4 V, 1 VBAT, 500 mV/div DC, from 3.5 to 3.0 V in 50 ms 2 VOUTP, 10 mV/div AC, T = 400 ms/div 100 mA 1 VBAT, 500 mV/div DC, from 3.5 to 3.0 V in 50 ms 2 VOUTN, 10 mV/div AC, T = 400 ms/div Figure 7. Continuous Conduction Mode (CCM) Figure 8. Discontinuous Current Mode (DCM) 1 SWP, 5 V/div DC, 4 ILP, 100 mA/div, DC, IOUTP = 100 mA 1 SWP, 5 V/div, DC 4 ILP, 50 mA/div, DC, IOUTP = 20 mA Figures 7 and 8 have been done at VBAT = 3.7 V, VOUTN = -5.4 V http://onsemi.com 7 NCP5810D TYPICAL OPERATING CHARACTERISTICS Figure 9. Continuous Conduction Mode (CCM) Figure 10. Discontinuous Current Mode (DCM) 1 SWN, 5 V/div DC, 4 ILN, 100 mA/div, DC, IOUTN = 100 mA 1 SWN, 5 V/div, DC 4 ILN, 50 mA/div, DC, IOUTN = 20 mA Figure 11. Positive Output Voltage Ripple in CCM Figure 12. Negative Output Voltage Ripple in CCM 1 VOUTP, 10 mV/div AC, 4 ILP, 100 mA/div DC, IOUTP = 100 mA 1 VOUTN, 10 mV/div AC, 4 ILN, 100 mA/div DC, IOUTN = 100 mA EN EN VOUTP VOUTP VOUTN VOUTN IC Figure 13. Start-Up Figure 14. Inrush Current at IOUT = 100 mA 1 VOUTP, 2 V/div, 2 VOUTN, 2 V/div, 3 EN pin, 2 V/div 1 VOUTP, 2 V/div, 2 VOUTN, 2 V/div, 3 EN pin, 5 V/div, 4 IC (Input Current), 100 mA/div Figures 9 through 12 have been done at VBAT = 3.7 V and schematic depict Figure 1 http://onsemi.com 8 NCP5810D DETAILED OPERATING DESCRIPTION Option of powering V Bat L1 2.7 to 5.5 V CINA 1 mF AVIN PVIN AVIN THERMAL PROTECTION - SWP SCHOTTKY MPO VOUTP COUTP ENABLE + 1 ms ERROR AMP 4.7 mF X5R 10V True Cut-Off Timer FBP 1.265 MAX DP 1.265 V VOUTP TSD OUT OFF REGULATION FBP LXP NMOS BAND GAP 1.265 V CINP 4.7 mF 4.7 mH OORP 1 2 TSD + 3 4 5 6 7 - OPAMP PWM COMPP + RST 8 MN1 Driver RAMP COMP SENSE CURRENT SET CLOCK ONE SHOT + IPEAK MAX P IPEAK COMP OSC Ipeak Max Threshold P - 1.75 Mhz ENABLE ENABLE EN IPEAK MAX N 400 k Ipeak Max Threshold N IPEAK COMP PIVIN + SENSE CURRENT FBN + FBN ERROR AMP PWM COMPN - 632.5 mV + NSR0320 SWN D1 MP1 1 2 3 4 TSD 5 6 OORN 7 8 VOUTN RST COUTN LX2 4.7 mH MAX DN 4.7 mF X5R 10V R3 OPAMP VREF R4 1.265 V 623.5 mV + 1 ms ONE S SET Timer PGND AGND AGND PGND Figure 15. Functional Block Diagram Boost Operation Detailed Descriptions The NCP5810D is a dual-output DC/DC converter which can generate both a positive and a negative voltage. The output voltage of the inverter is fully configurable using external feedback resistors. The switching regulator operates at 1.75 MHz which allows the use of small inductors and ceramic capacitors. The both converters are internally compensated which simplifies the design and reduces the PCB component count. Cycle-by-cycle peak current limit and thermal provide value added features to protect the device. The internal oscillator provides a 1.75 MHz clock signal to trigger the PWM controller on each rising edge (SET signal) which starts a cycle. During this phase the low side MN1 switch is turned on thus increasing the current through the inductor L1. The switch current is measured by the SENSE CURRENT and added to the RAMP COMP signal. Then PWM COMPP compares the output of the adder and the signal from ERROR AMP. When the comparator threshold is exceeded, the MN1 power switch is turned off until the rising edge of the next clock cycle. In http://onsemi.com 9 NCP5810D bypass VOUTN. Moreover in order to achieve excellent the line transient rejection in critical conduction mode two 10mF X5R in parallel for COUTN can be used. In this case the feed-forward capacitor (C6) must be change from 10pF to 68 pF as depicted Figure 16. addition, there are five functions which can reset the flip-flop logic to switch off the MN1. The MAX DP monitors the pulse width and if it exceeds 88% (nom) of the cycle time the switch will be turned off. This limits the switch from being on for more than one cycle. IPEAK COMP compares the sensed inductor current with the IPEAK_MAX threshold set at 700 mA (nom). If the current exceeds this value, the controller turns off the NMOS switch for the remainder of the cycle. This is a safety function to prevent any excessive current that could overload the inductor and the power stage. The boost regulator is internally compensated and provides a minimum of 45° phase margin. VREF 5 Buck-Boost Inverter Operation VIN C4 * μF C4 * μF R1 * pF C6 Feed-forward Figure 9 depicts the two intervals of the buck-boost operation in Continuous Conduction Mode (CCM) in a simplified way. During the first interval, the internal PMOS power switch is turned on and the external Schottky diode is reverse biased. The inductor stores energy through the battery while the load is supplied by the output capacitor to maintain regulation. During the second interval, the switch is turned off and the diode is forward biased, this allows the energy stored in the inductor to be supplied to both the load and the capacitor. In CCM, the voltage ratio of a buck-boost inverter converter can be expressed as: VOUT_N D1 L2 4.7 μH R2 C5 0.1 μF VOUTN 10 FBN SWN 7 Figure 16. Inverter Compensation High Output Voltage Accuracy NCP5810D integrates a very accurate internal voltage reference (1% nom). Combined with the use of precision feedback resistors, the NCP5810D will achieve highly precise output voltages. Excellent Line Transient Rejection and High Power Supply Rejection Ratio High output voltage accuracy and signal integrity makes the NCP5810D the perfect solution for biasing Active Matrix OLED displays. In order to have a steady, clean display, OLEDs have to be biased by a very accurate voltage with high immunity to line and load transients. Both regulators have been specifically designed with high loop gain and high phase margin to satisfy the great constraints of AMOLED driving. The boost converter features a high power supply rejection ratio of 60 dB (nom). PSRR is defined by T + D whereD + ON TSW 1*D The internal oscillator provides a 1.75 MHz clock signal to trigger the PWM controller on each rising edge (SET signal) which starts a cycle. During this phase the high side PMOS switch is turned on thus increasing the current through the inductor. The switch current is measured by the SENSE CURRENT and added to the RAMP COMP signal. Then PWM COMPN compares the output of the adder and the signal from ERROR AMP. When the comparator threshold is exceeded, the PMOS power switch is turned off until the rising edge of the next clock cycle. In addition, there are five functions which can reset the flip-flop logic to switch off the NMOS. The MAX DUTY CYCLE COMP monitors the pulse width and if it exceeds 88% (nom) of the cycle time the switch will be turned off. This limits the switch from being on for more than one cycle. IPEAK COMP compares the sensed inductor current with the IPEAK_MAX threshold set at 800 mA (nom). If the current exceeds this value, the controller turns off the PMOS switch for the remainder of the cycle. This is a safety function to prevent any excessive current that could overload the inductor and the power stage. ǒOutputRipple Ǔ VinRipple * 20LOG Out-of-Regulation Protection Both DC/DC regulators have implemented monitoring feedback voltage protection. After soft-start sequence the device is set to detect an out-of-regulation condition. Under normal operation if the feedback voltage goes beyond the nominal value by typically +/- 15% a fault is detected. This fault could be caused by an overload, a short-circuit or an open feedback condition. If this fault remains for more than 1 ms, both converters shuts down to protect device itself and any connected circuitry. The NCP5810D remains in disable condition until reinitialized by a rising edge on EN pin. Moreover to limit any overvoltage during the power-up or the 1 ms delay caused by and open feedback condition a small zener diode (D2) is recommended as depicted Figure 17. Buck-Boost Compensation Basically the buck-boost inverter is internally compensated and provides a minimum of 45° phase margin. But a 10 pF (C6) feed-forward capacitor is needed to improved stability with COUTN = 4.7 mF (C4) used to http://onsemi.com 10 NCP5810D FBN SWN 7 R2 VOUTN 10 D1 L2 4.7 μH R1 too high to keep good voltage accuracy. Therefore it is recommended to use values in the 10 kW to 100 kW range for the lower resistor R2. The upper feedback resistor R1 can calculated using the following equation: C4 4.7 μF D2 R1 + R 2 MM3Z_XX ǒ But : VFBN + Ǔ V OUTN * V FBN VFBN * VREF VREF 2 C6 So: R1 + R2 Figure 17. Zener Protection Zener voltage must choose to be 25 % above steady state voltage operation setup. For example, if one needs VOUTN = -5.4 V, VZ = 5.4 + 25 % = 6.8 V. Some recommended zener diodes include but are not limited to: ON SEMICONDUCTOR: MM3Z6V8T1 ǒ 1) 2 ŤV OUTNŤ V REF Ǔ For example, should one need –5.4 V for VOUTN, if a 56kW ±1% is selected of R2, R1 should be selected according to the following equation: R1 + 56 Enable This input logic allows enabling and disabling the converter. An active high logic level on this pin enables the device. A built-in pull-down resistor disables the device if the pin is left open. 5.4Ǔ + 536kW "1% ǒ1 ) 21.265 Components Selection Inductor Selection Three different electrical parameters need to be considered when selecting an inductor, the absolute value of the inductor, the saturation current and the DCR. During normal operation, the NCP5810D is intended to operate in Continuous Conduction Mode (CCM). The two equations below can be used to calculate the peak current for each converters: True Shut Down When in disable condition, the switch MP0 is turned off and truly isolates the battery from the output. The True shut down eliminates the leakage current from the battery to the load and significantly reduces battery consumption during disable condition, thus increasing battery life. IPEAK_P + Inrush Current Limiting Circuitry Before the NCP5810D boost converter is turned on, it is unknown whether the output capacitor COUTP is charged or discharged. If the output capacitor is discharged, a common boost converter shows high inductor inrush current at start-up. The internal circuitry of the NCP5810D has been carefully designed to limit the amplitude of the inrush current at start-up. I OUT_P hP (1 * DP) ) V IN D P 2 LP F ) V IN D N 2 LN F For the boost converter IPEAK_N + I OUT_N hN DN (1 * DN) For the buck-boost inverter Where VIN is the battery voltage, IOUT_X is the load current, L the inductor value, F the switching frequency, and DX the duty cycle. The global converter efficiency h varies with load current. A good approximation is to use h = 0.8 from the boost and h = 0.75 for the buck-boost inverter. It is important to ensure that the inductor current rating is high enough such that it not saturate. As the inductor size is reduced, the peak current for a given set of conditions increases along with higher current ripple so it is not possible to deliver maximum output power at lower inductor values. Finally an acceptable DCR must be selected regarding losses in the coil and must be lower than 300mW to limit excessive voltage drop. In addition, as DCR is reduced, overall efficiency will improve. The inductor value should range between 2.7mH and 6.8 mH, typically for each DC/DC converter, it is recommended to use a 4.7 mH low profile inductor. Some recommended inductors include but are not limited to: Thermal Shutdown When the IC junction temperature exceeds 165°C (nom), the power section of the device is disabled. Normal operation will resume when the junction temperature drops below 150°C (nom). Design Procedure Buck-Boost Inverter Output Voltage Setting The output voltage of the buck-boost inverter is also adjusted using external feedback resistors, and can be set from -2 V down to -15 V. Unlike for the boost converter, the lower feedback resistor R2 does not use the ground as a reference but uses the reference voltage (nom 1.265 V). R2 is placed between the feedback pin FBN (nom 632 mV) and the reference pin REF. As for the boost converter, the current flowing out of the feedback resistors must be as low as possible to ensure high efficiency in low load conditions. Nevertheless the feedback resistor impedance must not be http://onsemi.com 11 NCP5810D TDK: VLF3010AT-4R7MR70 (1.0 mm) TDK: MLP3216S2R7T (0.6 mm) SUMIDA: CDH2D09BNP (1.0 mm) MARUWA CXFU0208-4R7 (0.8 mm) characteristic is DC bias effect that especially affects capacitor in small case-size. The capacitance value can drop below 50% to 70% or even more of the nominal value. For the boost and buck-boost regulator stability viewpoint the percentage drop in capacitance for the chosen input and output operating voltage must be limit to 30% maximum over operating temperature range. Also too low capacitance will increase the output voltage ripple and the noise. Below is a list of recommended capacitors include but are not limited to, please consult the manufacturers for more detailed information. 4.7 mF 6.3 V 0603 TDK: C1608X5R0J475MT TDK: CGB4B1X5R0J475M (0.5 mm) 4.7 mF 10 V 0805 TDK: C2012X5R1A475MT MURATA: GRM219R61A475KE 10.0 mF 6.3 V 0805 TDK: C2012X5R0J106M (0.95 mm max) 10.0 mF 10 V 0805 TDK: C2012X5R1A106MT (1.25 mm) Schottky Diode Selection An external diode is required for the rectification of the negative output. The reverse voltage rating of the selected diode must be equal to or greater than the difference between the output voltage of the inverter and the input voltage. The average current rating of the diode must be greater than the maximum output load current. The peak current rating must be larger than the maximum peak inductor current. It is recommended to use a Schottky diode with lower forward voltage to minimize the power dissipation and therefore to maximize the efficiency of the converter. Also a particular care must be observed for parasitic capacitance versus reverse voltage and leakage current versus junction diode temperature. Both parameters are impacting the efficiency in low load condition and switching quiescent current. Some recommended Schottky diodes include but are not limited to: ON SEMICONDUCTOR: NSR0320MW2 Layout Recommendations The high speed operation of the NCP5810D demands careful attention to board layout and component placement. To prevent electromagnetic interference (EMI) problems and reduce voltage ripple of the device any high current copper trace which see high frequency switching should be optimized. Therefore, use short and wide traces for power current paths and for power ground tracks. In this application both couples of elements formed by the Schottky diode D1 / capacitor C4 and D2 (optional) / C3 are in the high frequency switching path where current flow is discontinuous. These components (D1/C4) in one hand and (D2/C3) in other hand should be placed as close as possible to reduce parasitic inductance connection. Also it is important to minimize the area of the SWP and SWN nodes and used the ground plane under them to minimize cross-talk to sensitive signals and IC. The exposed pad of the package must be connected to ground plane of the board that is important for EMI and thermal management. Also, PGND and AGND pin connection must be connected to the ground plane. In addition, the inductors track connection L1, L2 and input bypass capacitor C1, C2 must be placed shortly to the NCP5810D pins connection to reduce EMI. Finally it is always good practice to keep the sensitive tracks such as feedback connection (VS and FBN) away from switching signal connections (SWP and SWN) by laying the tracks on the other side of PCB. Figure 18 show an example of optimized PCB layout. ON SEMICONDUCTOR: RB521S30 ROHM: RSX051VA-30 PHILIPS: PMEG2005AEL Input Capacitor Selection To achieve high performances (signal integrity) one 4.7 F 6.3 V X5R should be used to bypass the power input supply CINP (PVIN) and one 1.0 F 6.3 V X5R to bypass the analog input supply CINA (AVIN). Output Capacitor Selection The output capacitor directly affects the output ripple voltage and the loop stability. COUTP and COUTN store energy during the TOFF phase and sustain the load during the TON phase. In order to minimize the output ripple, typically a 4.7 mF low ESR multi-layer ceramic capacitor type X5R is recommended. Moreover two 10 mF in parallel can be used to improved the line transient rejection in critical conduction mode of the inverter in this case see recommendation in Buck-Boost Compensation paragraph. Ceramic Capacitor Caution A particular care must be observed to select ceramic capacitors. Actually capacitance can decrease dramatically with the increased applied DC voltage. This http://onsemi.com 12 NCP5810D Thermal Considerations 10.48 Careful attention must be paid to the internal power dissipation of the NCP5810D. The power dissipation is a function of efficiency and output power. Hence, increasing the output power requires better components selection. For example, should one change inductors: larger inductor value (in micro Henri) and/or lower DCR may improve efficiency. Adding the optional Schottky diode D2 provides a lower drop when the current flowing from the inductor to the load, thereby improving the boost converter efficiency. The exposed thermal pad that is designed to be soldered to the ground plane to used the PCB as a heatsink. This ground should then be connected to an internal copper ground plane with thermal via placed directly under the package to spread out the heat dissipated by the NCP5810D as depicted in Figure 18. 10.48 Figure 18. Recommended PCB Layout ORDERING INFORMATION Device NCP5810DMUTXG Package Shipping† UDFN-12 3x3 mm (Pb-Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Demo Board Available: • The NCP5810DGEVB/D evaluation board that configures the device in typical application to supply constant voltage. http://onsemi.com 13 NCP5810D PACKAGE DIMENSIONS UDFN12, 3x3 MU SUFFIX CASE 517AM-01 ISSUE O A D PIN ONE REFERENCE 2X 0.10 C 2X ÇÇÇ ÇÇÇ ÇÇÇ 0.10 C E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW A 0.10 C 12X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B 0.08 C MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.07 REF 0.20 0.30 3.00 BSC 2.40 2.60 3.00 BSC 1.60 1.80 0.50 BSC 0.20 --0.30 0.50 A3 A1 C SIDE VIEW SEATING PLANE SOLDERING FOOTPRINT* 2.60 11X D2 0.35 6 1 12X K 12X (0.15) 0.60 E2 12X L 12 7 12X b e 1.80 3.30 0.10 C A B 0.05 C NOTE 3 1 0.48 BOTTOM VIEW 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 http://onsemi.com 14 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative NCP5810D/D