INTERSIL ISL85033EVAL2Z

Application Note 1585
Author: Paul Orfanu
ISL85033EVAL2Z (Small Form) Wide VIN Dual
Standard Buck Regulator With 3A/3A Output
Current - Short Form
Description
The ISL85033EVAL2Z kit demonstrates performance of
the ISL85033 switching regulator IC. An input range of
4.5V to 28V and 3A output per channel (connect in
parallel to 6A) allows the ISL85033 to meet a wide
variety of POL requirements.
The ISL85033 is offered in a 4mmx4mm 28 Ld TQFN
package with 1mm maximum height. The complete
converter occupies 6.25cm2 area.
100
EFFICIENCY (%)
90
80
12VOUT 1MHz
9VOUT 1MHz
70
5VOUT 500kHz
60
3.3VOUT 500kHz
1.8VOUT 300kHz
0.5
• Wide Input Voltage Range from 4.5V to 28V
• Adjustable Output Voltage with Continuous Output
Current up to 3A per channel
• Current Mode Control
• Adjustable Switching Frequency from 300kHz to
2MHz
• Independent Power-Good Detection
• Selectable In-Phase or Out-of-Phase PWMs Switching
Operation
• Independent, Sequential, Ratiometric or Absolute
Tracking Between Outputs
• Internal 2ms Soft-start Time
• Overcurrent and Hiccup Mode Short Circuit
Protection, Thermal Overload Protection, UVLO
• Boot Undervoltage Detection
• Channels are Out-of-phase, Reducing Voltage Ripple
and Component Size
Quick Setup Guide
50
40
0.0
Key Features
1.0
1.5
2.0
OUTPUT LOAD (A)
2.5
3.0
FIGURE 1. EFFICIENCY vs LOAD, TA = +25°C,
VIN = 28V
1. Ensure correct board connection to the supply (“+”
to VIN1 and “-” to GND2) and loads prior to applying
power, then turn on the power supply.
2. Verify the output voltage is 5V for VOUT1 and 3.3V
for VOUT2.
Frequency Control
ISL85033 has an FS pin that controls the frequency of
operation. Programmable frequency allows for
optimization between efficiency and external
component size. ISL85033EVAL2Z has the switching
frequency set to 500kHz (FS is tied to VCC).
1.629’
SYNC Control
0.595’
The ISL85033 has a SI pin for external synchronization.
Default board configuration has R8 = 0 to GND, which
defaults to the internally selected switching frequency.
Removing R8 allows the synchronization to be external
between 600kHz to 4MHz. Do not leave this pin floating.
Output Voltage Selection
FIGURE 2. ISL85033EVAL2Z TOP LAYER COMPONENTS
ISL85033EVAL2Z board has VOUT1 set to 5V and VOUT2 set
to 3.3V. The output voltage programming resistor, R3 (R10
respectively), will depend on the value chosen for the
feedback resistor, R2 (R12 respectively), and the desired
output voltage, VOUT, see Equation 1. The value for R2 (R12
respectively) is typically between 1k and 10k.
R 3 = ( V OUT1 – V FB ) • R 2 ⁄ 0.8
R 10 = ( V OUT2 – V FB ) • R 12 ⁄ 0.8
(EQ. 1)
Please note that if VOUT is less than 2.5V, switching
frequency and compensation must be changed for
300kHz operation due to minimum on-time limitation.
Please refer to data sheet FN6676 for further information.
November 29, 2010
AN1585.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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All other trademarks mentioned are the property of their respective owners.
VCC
PGOOD2
SYNCOUT
SYNCIN
PGOOD1
VCC
Application Note 1585
R13
DNP
NC1
A
VOUT1
A
R2
8.06K
1
4
C2
OPEN
BOOT1
5
C5
A
A
6
0.01UF
7
GND1
29
A
ISL85033IRTZ
SS1
PGND1
BOOT1
U1
SS2
PGND2
BOOT2
PHASE2
PHASE2
PHASE1
PHASE1
EP
A
A
VIN1
A
A
GND4
FB1
L2
7UH
D2
B340B
C14
47UF
COMP1
C7
10UF
C8
10UF
VIN2
SS1
R18
SS2
DNP
C10
10UF
A
GND2
COMP2
A
VIN2
C9
4.7UF
R17
DNP
A
VIN1
FB2
VO2
2
SQL004
R16
DNP
VOUT2
VOUT2=3.3V
2
1
1
A
VIN1
VIN2
R12
8.06K
C12
0.01UF
15
R15
0
C15
OPEN
BOOT2
16
2
A
FB2
18
17
A
R11
0
A
VCC
D1
B340B
SQL004
C13
C16
68PF
SS2
19
8
9
10
11
12
13
14
2
7UH
C3
47UF
R10
25.5K
20 69.8K 470PF
1
1
21
COMP2
FB2
A
L1
VOUT1
VOUT1=5V
COMP1
FB1
COMP2
28
27
26
25
24
23
22
C4
FB1 470PF 69.8K 2
SS1 3
C11
12PF
R9
VIN1
VIN1
EN1
VCC
EN2
VIN2
VIN2
A
12PF
R4
PGOOD1
FS
NC
SGND
SYNCIN
SYNCOUT
PGOOD2
C6
R3
42.2K
R1
0
COMP1
C1
68PF
VO1
R14
DNP
VOUT2
GND3
SGND
A
A
A
A
A
IF VOUT1=5V (4.5V-5.5V) PLS POPULATE R26
IF VOUT2=5V (4.5V-5.5V) PLS POPULATE R27
OTHERWISE PLS LEAVE R26, R27 DNP!
R5
0
ONLY
ONLY
R7
DNP
R6
0
SYNCIN
SS1
DRAWN BY:
SS2
R8
0
RELEASED
UPDATED
PAUL ORFANU
BY:
BY:
TIM KLEMANN
A
DATE:
06/21/2010
DATE:
ENGINEER:
PAUL ORFANU
TITLE:
ISL85033
DATE:
06/23/2010
WIDE VIN DUAL S
1.500’
FIGURE 3. ISL85033EVAL2Z SCHEMATIC
1.875’
FIGURE 4. ISL85033EVAL2Z TOP LAYER ETCH
FIGURE 5. ISL85033EVAL2Z BOTTOM LAYER
COMPONENTS
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reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
2
AN1585.1
November 29, 2010