MC10H424 Quad TTL to ECL Translator with ECL Strobe The MC10H424 is a Quad TTL–to–ECL translator with an ECL strobe. Power supply requirements are ground, +5.0 volts, and –5.2 volts. • Propagation Delay, 1.5 ns Typical • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K – Compatible http://onsemi.com MARKING DIAGRAMS 16 CDIP–16 L SUFFIX CASE 620 LOGIC DIAGRAM 5 4 6 2 7 MC10H424L AWLYYWW 1 16 PDIP–16 P SUFFIX CASE 648 3 1 MC10H424P AWLYYWW 1 10 12 1 15 11 PLCC–20 FN SUFFIX CASE 775 13 14 GND VCC (+5.0 VDC) VEE (–5.2 VDC) = PIN 16 = PIN 9 = PIN 8 A WL YY WW DIP PIN ASSIGNMENT 10H424 AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION BOUT 1 16 GND AOUT 2 15 COUT BOUT 3 14 DOUT AOUT 4 13 DOUT AIN COMMON STROBE 5 12 COUT 6 11 DIN BIN 7 10 CIN VEE 8 9 VCC Device Package Shipping MC10H424L CDIP–16 25 Units/Rail MC10H424P PDIP–16 25 Units/Rail MC10H424FN PLCC–20 46 Units/Rail Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 6 1 Publication Order Number: MC10H424/D MC10H424 MAXIMUM RATINGS Symbol VEE VCC VI VI Characteristic Rating Unit –8.0 to 0 Vdc Power Supply (VEE = – 5.2 V) 0 to +7.0 Vdc Input Voltage (ECL) 0 to VEE Vdc Input Voltage (TTL) 0 to VCC Vdc 50 100 mA 0 to +75 °C –55 to +150 –55 to +165 °C Power Supply (VCC = 5.0 V) Iout Output Current – Continuous – Surge TA Tstg Operating Temperature Range Storage Temperature Range – Plastic – Ceramic ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ± 5%, VCC = 5.0 V ± 5.0%) 0° Symbol Characteristic 25° 75° Min Max Min Max Min Max Unit IE Negative Power Supply Drain Current – 72 – 66 – 72 mAdc ICCH ICCL Positive Power Supply Drain Current – 16 – 16 – 18 mAdc – 25 – 25 – 25 mAdc IR Reverse Current Pin 5,7,10,11 – 50 – 50 – 50 µAdc IF Forward Current Pin 5,7,10,11 – –3.2 – –3.2 – –3.2 mAdc IinH IinL Input HIGH Current Pin 6 – 450 – 310 – 310 µAdc Input LOW Current Pin 6 0.5 – 0.5 – 0.3 – µAdc V(BR)in VI Input Breakdown Voltage 5.5 – 5.5 – 5.5 – Vdc Input Clamp Voltage – –1.5 – –1.5 – –1.5 Vdc VOH VOL High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc VIH High Input Voltage Pin 5,7,10,11 2.0 – 2.0 – +2.0 – Vdc VIL Low Input Voltage Pin 5,7,10,11 – 0.8 – 0.8 – 0.8 Vdc VIH VIL High Input Voltage Pin 6 –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc Low Input Voltage Pin 6 –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc AC PARAMETERS Propagation Delay Data Strobe tpd Rise Time tr tf Fall Time NOTE: Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.1 volts. ns 0.5 0.5 2.2 2.2 0.5 0.5 2.3 2.3 0.5 0.5 2.4 2.4 0.5 2.0 0.5 2.0 0.5 2.2 ns 0.5 2.0 0.5 2.0 0.5 2.2 ns APPLICATIONS INFORMATION An advantage of this device is that TTL–level information can be transmitted differentially, via balanced twisted pair lines, to MECL equipment, where the signal can be received by the MC10H115 or MC10H116 differential line receivers. The MC10H424 has TTL–compatible inputs, an ECL strobe and MECL complementary open–emitter outputs that allow use as an inverting/non–inverting translator or as a differential line driver. When the common strobe input is at the low–logic level, it forces all true outputs to a MECL low–logic state and all inverting outputs to a MECL high–logic state. http://onsemi.com 2 MC10H424 PACKAGE DIMENSIONS PLCC–20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) M T L–M B Y BRK –N– U N S 0.007 (0.180) M T L–M S S N S D –L– –M– Z W 20 D 1 G1 X V 0.010 (0.250) S T L–M S N S VIEW D–D A 0.007 (0.180) M T L–M S N S R 0.007 (0.180) M T L–M S N S 0.007 (0.180) M T L–M H S N S Z K1 K C E F 0.007 (0.180) M T L–M S 0.004 (0.100) G J –T– VIEW S G1 0.010 (0.250) S T L–M S N S VIEW S SEATING PLANE NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 3 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10 _ 0.310 0.330 0.040 ––– MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10 _ 7.88 8.38 1.02 ––– N S MC10H424 –A– 16 9 1 8 –B– CDIP–16 L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE T C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M –A– 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 16 S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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