IDT IDT71V016S20Y 3.3v cmos static ram 1 meg (64k x 16-bit) Datasheet

IDT71V016
3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Features
Description
◆
The IDT71V016 is a 1,048,576-bit high-speed Static RAM
organized as 64K x 16. It is fabricated using IDT’s high-perfomance,
high-reliability CMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost-effective solution for high-speed memory needs.
The IDT71V016 has an output enable pin which operates as fast
as 7ns, with address access times as fast as 12ns. All bidirectional
inputs and outputs of the IDT71V016 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous circuitry
is used, requiring no clocks or refresh for operation.
The IDT71V016 is packaged in a JEDEC standard 44-pin
Plastic SOJ and 44-pin TSOP Type II.
◆
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64K x 16 advanced high-speed CMOS Static RAM
Commercial (0° to +70°C) and Industrial (–40°C to +85°C)
Equal access and cycle times
— Commercial and Industrial: 15/20ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
LVTTL-compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 3.3V (±0.3V) power supply
Available in 44-pin Plastic SOJ and 44-pin TSOP
package.
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Functional Block Diagram
OE
A0 - A15
Output
Enable
Buffer
Address
Buffers
Row / Column
Decoders
I/O15
CS
Chip
Enable
Buffer
8
High
Byte
I/O
Buffer
8
I/O8
WE
O
Write
Enable
Buffer
16
64K x 16
Memory
Array
O R
O
F
Sense
Amps
and
Write
Drivers
I/O7
8
Low
Byte
I/O
Buffer
8
I/O0
BHE
Byte
Enable
Buffers
BLE
3211 drw 01
AUGUST 2000
1
©2000 Integrated Device Technology, Inc.
DSC-3211/08
IDT71V016, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configuration
Pin Description
A4
1
44
A5
A3
2
43
A6
A2
3
42
A7
A1
4
41
OE
A0
5
40
BHE
CS
6
39
BLE
I/O0
7
38
I/O15
I/O1
8
37
I/O14
I/O2
9
36
I/O13
I/O3
10
35
I/O12
VDD
11
34
Vss
33
VDD
32
I/O11
31
I/O10
30
I/O9
29
I/O8
28
NC
27
A8
26
A9
25
A10
24
A11
23
NC
Vss
12
I/O4
13
I/O5
14
I/O6
15
I/O7
16
WE
17
A15
18
A14
19
A13
20
A12
21
NC
22
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SO44-1
SO44-2
3211 drw 02
SOJ/TSOP
Top View
O
Truth Table(1)
BLE
BHE
I/O0-I/O7
I/O8-I/O15
X
X
X
High-Z
High-Z
Deselected – Standby
H
L
H
DATAOUT
High-Z
Low Byte Read
L
H
H
L
High-Z
DATAOUT
High Byte Read
L
L
H
L
O R
O
F
L
DATAOUT
DATAOUT
Word Read
L
X
L
L
L
DATAIN
DATAIN
Word Write
L
X
L
L
H
DATAIN
High-Z
Low Byte Write
L
X
L
H
L
High-Z
DATAIN
High Byte Write
L
H
H
X
X
High-Z
High-Z
Outputs Disabled
L
X
X
H
H
High-Z
High-Z
Outputs Disabled
CS
OE
H
X
L
L
L
WE
Function
3211 tbl 02
NOTE:
1. H = VIH, L = VIL, X = Don't care.
6.42
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IDT71V016, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
Recommended Operating
Temperature and Supply Voltage
(1)
Symbol
Rating
VTERM(2)
VTERM(3)
TA
Value
Unit
Terminal Voltage with
Respect to GND
–0.5 to +4.6
V
Terminal Voltage with
Respect to GND
–0.5 to VCC+0.5
Operating Temperature
V
0 to +70
o
C
C
C
TBIAS
Temperature Under Bias
–55 to +125
o
TSTG
Storage Temperature
–55 to +125
o
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
Grade
Temperature
GND
VDD
Commercial
0°C to +70°C
0V
3.3V ± 0.3V
Industrial
–40°C to +85°C
0V
3.3V ± 0.3V
3211 tbl 04
Recommended DC Operating
Conditions
Symbol
Parameter
VDD
Supply Voltage
GND
Supply Voltage
VIH
C
Input High Voltage – Inputs
Min.
Typ.
Max.
Unit
3.0
E
3.3
3.6
V
0
0
0
V
—
2.0
4.6
V
____
VDD+0.3
V
____
0.8
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3211 tbl 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VDD terminals only.
3. Input, Output,and I/O terminals; 4.6V maximum.
VIH
VIL
Input High Voltage – I/O
Input Low Voltage
2.0
(1)
–0.5
NOTE:
1. VIL (min.) = –1.5V for pulse width less than tRC/2, once per cycle.
V
3211 tbl 05
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
Parameter(1)
Symbol
CIN
Input Capacitance
CI/O
I/O Capacitance
Conditions
Max.
Unit
VIN = 3dV
6
pF
VOUT = 3dV
7
pF
3211 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
DC Electrical Characteristics
(VDD = 3.3V ± 0.3V, Commercial and Industrial Temperature Ranges)
IDT71V016
Symbol
Parameter
|ILI|
Input Leakage Current
|ILO|
Output Leakage Current
VOL
Output Low Voltage
VOH
O
Output High Voltage
Test Condition
Min.
Max.
Unit
VDD = Max., VIN = GND to VDD
___
5
µA
VDD = Max., CS = VIH, VOUT = GND to VDD
___
5
µA
___
0.4
V
2.4
___
O R
O
F
IOL = 8mA, VDD = Min.
IOH = –4mA, VDD = Min.
V
3211 tbl 07
DC Electrical Characteristics(1)
(VDD = 3.3V ± 0.3V, VLC = 0.2V, VHC = VDD–0.2V)
Symbol
71V016S15
Parameter
71V016S20
Com'l
Ind.
Com'l.
Ind.
Unit
ICC
Dynam ic Operating Current
CS ≤ VIL, Outputs Open, VDD = Max., f = f MAX(2)
130
130
120
120
mA
ISB
Standby Power Supply Current (TTL Level)
CS ≥ VIH, Outputs Open, VDD = Max., f = f MAX(2)
35
35
30
30
mA
ISB1
Standby Power Supply Current (CMOS Level)
CS ≥ VHC, Outputs Open, VDD = Max., f = 0(2)
VIN ≤ VLC or VIN ≥ VHC
5
7
5
7
mA
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .
6.42
3
3211 tbl 08
IDT71V016, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
1.5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
See Figure 1, 2 and 3
3211 tbl 09
AC Test Loads
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3.3V
3.3V
320Ω
320Ω
DATA OUT
DATA OUT
30pF*
5pF*
350Ω
350Ω
3211 drw 04
3211 drw 05
*Including jig and scope capacitance.
Figure 2. AC Test Load
Figure 1. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
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6
∆tAA, tACS
(Typical, ns) 5
4
3
•
•
•
2
•
1
•
•
•
8 20 40 60 80 100 120 140 160 180 200
CAPACITANCE (pF)
Figure 3. Output Capacitive Derating
6.42
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3211 drw 06
IDT71V016, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ± 0.3V, Commercial and Industrial Temperature Ranges)
71V016S15
Symbol
Parameter
71V016S20
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
15
____
20
____
ns
Address Access Time
____
15
____
20
ns
tACS
Chip Select Access Time
____
15
____
20
ns
tCLZ(1)
Chip Select Low to Output in Low-Z
5
____
5
____
ns
tCHZ(1)
Chip Select High to Output in High-Z
____
6
____
8
ns
tOE
Output Enable Low to Output Valid
____
8
____
Output Enable Low to Output in Low-Z
0
____
tOHZ (1)
Output Enable High to Output in High-Z
____
6
tOH
Output Hold from Address Change
4
—
tBE
Byte Enable Low to Output Valid
—
8
READ CYCLE
tRC
tAA
tOLZ
(1)
E
10
ns
____
ns
____
8
ns
5
—
ns
____
10
ns
0
____
ns
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(1)
Byte Enable Low to Output in Low-Z
0
____
tBHZ(1)
Byte Enable High to Output in High-Z
____
6
____
8
ns
15
____
20
____
ns
tBLZ
WRITE CYCLE
tWC
Write Cycle Time
tAW
Address Valid to End of Write
10
____
12
____
ns
tCW
Chip Select Low to End of Write
10
____
12
____
ns
10
____
12
____
ns
0
____
ns
tBW
Byte Enable Low to End of Write
tAS
Address Set-up Time
0
____
tWR
Address Hold from End of Write
0
____
0
____
ns
tWP
Write Pulse Width
10
____
12
____
ns
tDW
Data Valid to End of Write
8
____
10
____
ns
0
____
0
____
ns
O
tDH
Data Hold Time
tOW(1)
Write Enable High to Output in Low-Z
1
____
1
____
ns
tWHZ(1)
Write Enable Low to Output in High-Z
____
6
____
8
ns
O R
O
F
3211 tbl 10
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
Timing Waveform of Read Cycle No. 1(1,2,3)
tRC
ADDRESS
tAA
tOH
DATAOUT
tOH
DATAOUT VALID
PREVIOUS DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
3211 drw 07
6.42
5
IDT71V016, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
tRC
ADDRESS
tAA
tOH
OE
tOHZ
tOE
tOLZ
CS
tCLZ
BHE, BLE
(3)
tACS (2)
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tCHZ
(3)
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tBE
tBLZ
DATAOUT
(3)
(3)
(2)
tBHZ
(3)
(3)
DATA OUT VALID
3211 drw 08
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC
ADDRESS
tAW
CS
BHE , BLE
WE
O
tCW
tAS
O R
O
F
tWHZ
DATAOUT
PREVIOUS DATA VALID
(2)
tCHZ
(5)
tBW
tWR
tBHZ
(5)
tWP
(5)
tOW
(3)
(5)
DATA VALID
tDW
DATAIN
tDH
DATAIN VALID
3211 drw 09
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6.42
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IDT71V016, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
tWC
ADDRESS
tAW
CS
tCW (2)
tAS
tBW
BHE , BLE
tWP
tWR
WE
DATAOUT
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tDW
DATAIN
C
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tDH
DATAIN VALID
3211 drw 10
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)
tWC
ADDRESS
tAW
CS
tAS
BHE , BLE
WE
DATAOUT
DATAIN
O
tCW
(2)
tBW
tWP
O R
O
F
tWR
tDW
tDH
DATAIN VALID
3211 drw 11
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6.42
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IDT71V016, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information
IDT 71V016
Device
Type
S
XX
XXX
X
Power
Speed
Package
Process/
Temperature
Range
Blank
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PH
15
20
O
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
O R
O
F
6.42
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400-mil SOJ (SO44-1)
400-mil TSOP Type II (SO44-2)
Speed in nanoseconds
3211 drw 12
IDT71V016, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
11/1/99
Pg. 3
Pg. 5
Pg. 6
Pg. 7
Pg. 9
08/30/00
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Updated to new format
Expressed commercial and industrial ranges on DC Electrical table
Expressed commercial and industrial ranges on AC Electrical table
Revised footnotes on Write Cycle No. 1 diagram
Revised footnotes on Write Cycle No. 2 and No. 3 diagrams
Added Datasheet Document History
Part in obsolescence, order part 71V016SA. See PDN# S-0003
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9
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