CD4046BMS CMOS Micropower Phase Locked Loop December 1992 Features Description • Very Low Power Consumption: 70µW (typ.) at VCO fo = 10kHz, VDD = 5V • Operating Frequency Range Up to 1.4 MHz (typ.) at VDD = 10V, RI = 5kΩ CD4046BMS CMOS Micropower Phase-Locked Loop (PLL) consists of a low power linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signalinput amplifier and a common comparator input. A 5.2V zener diode is provided for supply regulation if necessary. • Low Frequency Drift: 0.04%/oC (typ.) at VDD = 10V The CD4046BMS is supplied in these 16-lead outline packages: • Choice of Two Phase Comparators: - Exclusive-OR Network (I) - Edge-Controlled Memory Network with Phase-Pulse Output for Lock Indication (II) Braze Seal DIP H4W Frit Seal DIP H1F Ceramic Flatpack H6W • High VCO Linearity: <1% (typ.) at VDD = 10V • VCO Inhibit Control for ON-OFF Keying and Ultra-Low Standby Power Consumption • Source-Follower (Demod. Output) Output of VCO Control Input • Zener Diode to Assist Supply Regulation • Standardize, Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • FM Demodulator and Modulator • Frequency Synthesis and Multiplication • Frequency Discriminator • Data Synchronization VCO Section The VCO requires one external capacitor C1 and one or two external resistors (R1 or R1 and R2). Resistor R1 and capacitor C1 determine the frequency range of the VCO and resistor R2 enables the VCO to have a frequency offset if required. The high input impedance (1012Ω) of the VCO simplifies the design of low pass filters by permitting the designer a wide choice of resistorto-capacitor ratios. In order not to load the low-pass filter, a source-follower output of the VCO input voltage is provided at terminal 10 (DEMODULATED OUTPUT). If this terminal is used, a load resistor (RS) of 10kΩ or more should be connected from this terminal to VSS. If unused this terminal should be left open. The VCO can be connected either directly or through frequency dividers to the comparator input of the phase comparators. A full CMOS logic swing is available at the output of the VCO and allows direct coupling to CMOS frequency dividers such as the Intersil CD4024, CD4018, CD4020, CD4029, and CD4050. One or more CD4018 (Preset Table Divide-By-N Counter) or CD4029 (Presettable Up/Down Counter) or CD4029 (Presettable Divideby-N Counter) or CD4029 (Presettable Up/Down Counter), or CD4059A (Programmable Divide-by “N” Counter), together with the CD4046BMS (Phase-Locked Loop) can be used to build a micropower low-frequency synthesizer. A logic 0 on the INHIBIT input “enables” the VCO and the source follower, while a logic 1 “turns off” both to minimize stand-by power consumption. • Voltage-to-Frequency Conversion • Tone Decoding Pinout CD4046BMS TOP VIEW • FSK - Modems • Signal Conditioning PHASE PULSES 1 PHASE COMP I OUT 2 COMPARATOR IN 3 VCO OUT 4 15 ZENER 14 SIGNAL IN 13 PHASE COMP II OUT INHIBIT 5 12 R2 TO VSS CI(1) 6 11 R1 TO VSS C1 (2) 7 VSS 8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-886 16 VDD 10 DEMODULATOR OUT 9 VCO IN File Number 3312 CD4046BMS Phase Comparators SIGNAL INPUT (TERM. 14) The phase-comparator signal input (terminal 14) can be direct-coupled provided the signal swing is within CMOS logic levels (logic “0” ≤30% (VDD-VSS). logic “1” ≥70% (VDD - VSS)]. For smaller swings the signal must be capacitively coupled to the self-biasing amplifier at the signal input. Phase-comparator I is an exclusive -OR network; it operates analogously to an overdriven balanced mixer. To maximize the lock range, the signal and comparator-input frequencies must have a 50% duty cycle. With no signal or noise on the signal input, this phase comparator has an average output voltage equal to VDD/2. The low-pass filter connected to the output of phase-comparator I supplies the averaged voltage to the VCO input, and causes the VCO to oscillate at the center frequency (fo). The frequency range of input signals on which the PLL will lock if it was initially out of lock is defined as the frequency capture range (2fc). The frequency range of input signals on which the loop will stay locked if it was initially in lock is defined as the frequency lock range (2fL). The capture range is ≤ the lock range. With phase-comparator I the range of frequencies over which the PLL can acquire lock (capture range) is dependent on the low-pass-filter characteristics, and can be made as large as the lock range. Phase-comparator I enables a PLL system to remain in lock in spite of high amounts of noise in the input signal. AVERAGE OUTPUT VOLTAGE (V) One characteristic of this type of phase comparator is that it may lock onto input frequencies that are close to harmonics of the VCO center-frequency. A second characteristic is that the phase angle between the signal and the comparator input varies between 0o and 180o, and is 90o at the center frequency. Figure 1 shows the typical, triangular, phase-to-output response characteristic of phase comparator I. Typical waveforms for a CMOS phase-locked-loop employing phase comparator I in locked condition of fo is shown in Figure 2. AVERAGE OUTPUT VOLTAGE VDD VDD/2 0 90o 180o SIGNAL-TO-COMPARATOR INPUTS PHASE DIFFERENCE FIGURE 1. PHASE-COMPARATOR I CHARACTERISTICS AT LOW-PASS FILTER OUTPUT VCO OUTPUT (TERM 4) = COMPARATOR INPUT (TERM 3) PHASE COMPARATOR I OUTPUT (TERM 2) VDD VCO INPUT (TERM 9) = = LOW-PASS FILTER OUTPUT VSS FIGURE 2. TYPICAL WAVEFORMS FOR CMOS PHASELOCKED LOOP EMPLOYING PHASE COMPARATOR IN LOCKED CONDITION OF fo. Phase comparator II is an edge-controlled digital memory network. It consists of four flip-flop stages, control gating, and a three-state output circuit comprising p- and n- type drivers having a common output node. When the p-MOS or n-MOS drivers are ON they pull the output up to VDD or down to VSS, respectively. This type of phase comparator acts only on the positive edges of the signal and comparator inputs. The duty cycles of the signal and comparator inputs are not important since positive transitions control the PLL system utilizing this type of comparator. If the signal-input frequency is higher than the comparator-input frequency, the p-type output driver is maintained ON most of the time, and both the n and p drivers OFF (3state) the remainder of the time. If the signal-input frequency is lower than the comparator-input frequency, the n-type output driver is maintained ON most of the time, and both the n and p drivers OFF (3 state) the remainder of the time. If the signal and comparator input frequencies are the same, but the signal input lags the comparator input in phase, the n-type output driver is maintained ON for a time corresponding to the phase differences. If the signal and comparator-input frequencies are the same, but the comparator input lags the signal in phase, the p-type output driver is maintained ON for a time corresponding to the phase difference. Subsequently, the capacitor voltage of the low-pass filter connected to this phase comparator is adjusted until the signal and comparator inputs are equal in both phase and frequency. At this stable point both p- and ntype output drivers remain OFF and thus the phase comparator output becomes an open circuit and holds the voltage on the capacitor of the low-pass filter constant. Moreover the signal at the “phase pulses” output is a high level which can be used for indicating a locked condition. Thus, for phase comparator II, no phase difference exists between signal and comparator input over the full VCO frequency range. Moreover, the power dissipation due to the low-pass filter is reduced when this type of phase comparator is used because both the p- and n-type output drivers are OFF for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range, independent of the low-pass filter. With no signal present at the signal input, the VCO is adjusted to its lowest frequency for phase comparator II. Figure 15 shows typical waveforms for a CMOS PLL employing phase comparator II in a locked condition. 7-887 Specifications CD4046BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current Input Leakage Current SYMBOL IDD IIL IIH CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125 C - 1000 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA VIN = VDD or GND 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV VIN = VDD or GND VDD = 20 VDD = 18V o Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Functional F VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V 3 State Leakage Current IOZL VIN = VDD or GND VOUT = 0V 1 +25oC -100 - nA 3 State Leakage Current IOZH VIN = VDD or GND VOUT = VDD VDD = 20V 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20V 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA VDD = 18V 7-888 Specifications CD4046BMS TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER Quiescent Leakage Phase Comparator (Bias Amp Leakage) LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS BIAS LKG VDD = 20V, VIN = VDD or GND PIN 14 Open Pin 5 = VDD 1 +25oC - 4 mA 3 -55oC - 4 mA VDD = 20V, VIN = VDD or GND PIN 14 = VSS or VDD Pin 5 = VDD 1 +25oC - 160 µA 3 -55oC - 160 µA SYMBOL CONDITIONS (NOTE 1) NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER AC Coupled Signal Input Voltage Sensitivity (Peak to Peak) SYMBOL VS CONDITIONS (NOTE 1) VDD = 5V, Input Frequency = 100kHz Sine Wave GROUP A SUBGROUPS TEMPERATURE 9 o +25 C LIMITS MIN MAX UNITS - 360 mV NOTES: 1. Go/No Go test with limits applied to inputs. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Output Voltage SYMBOL VOL CONDITIONS VDD = 5V, No Load NOTES TEMPERATURE MIN MAX UNITS 1, 2 +25oC, +125oC, - 50 mV -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA 0.64 - mA -55 Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B Output Current (Source) IOH10 Output Current (Source) IOH15 VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 VDD =15V, VOUT = 13.5V 1, 2 oC +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V 7-889 Specifications CD4046BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Quiescent Leakage Phase Comparator (Bias Amp Leakage) SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Pin 14 Open Pin 5 = VDD 1, 2 +25oC/-55oC - 0.2 mA Pin 14 = VSS or VDD Pin 5 = VDD 1, 2 +25oC/-55oC - 20 µA VDD = 10 Pin 14 Open VIN = Pin 5 = VDD VDD or Pin 14 = VSS or VDD GND Pin 5 = VDD 1, 2 +25oC/-55oC - 1.0 mA 1, 2 +25oC/-55oC - 40 µA VDD = 15 Pin 14 Open VIN = Pin 5 = VDD VDD or Pin 14 = VSS or VDD GND Pin 5 = VDD 1, 2 +25oC/-55oC - 1.5 mA 1, 2 +25oC/-55oC - 80 µA VDD = 10V, Input Frequency = 100kHz Sine Wave 1, 2 +25oC - 660 mV VDD = 15V, Input Frequency = 100kHz Sine Wave 1, 2 +25oC - 1800 mV BIAS LKG VDD = 5 VIN = VDD or GND AC Coupled Signal Input Voltage Sensitivity (Peak to Peak) VS NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F CONDITIONS NOTES TEMPERATURE MIN MAX UNITS 1, 4 +25oC - 25 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3 +25oC - 1.35 x +25oC Limit mV VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND AC Coupled Signal Input Voltage Sensitivity VS VDD = 5V Input Frequency = 100kHz Sine Wave NOTES: 1. All voltages referenced to device GND. 2. Go/No Go test with limits applied to inputs. 3. See Table 2 for +25oC limit. TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) 7-890 Specifications CD4046BMS TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas PDA (Note 1) Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 PDA (Note 1) Final Test Group A Group B Group D READ AND RECORD IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS Group E Subgroup 2 READ AND RECORD METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR GROUND VDD Static Burn-In 1 1, 2, 4, 6, 7, 10, 11, Note 1 13, 15 FUNCTION OPEN 3, 5, 8, 9, 14 12, 16 Static Burn-In 2 1, 2, 4, 6, 7, 10, 11, Note 1 13, 15 8 3, 5, 9, 12, 14, 16 Dynamic BurnIn Note 1 1, 2, 4, 6, 7, 10, 11, 13, 15 8, 9 3, 5, 12, 16 Irradiation Note 2 1, 2, 4, 6, 7, 10, 11, 13, 15 8 3, 5, 9, 12, 14, 16 9V ± -0.5V 50kHz 25kHz 2 14 - NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-891 CD4046BMS Design Information This information is a guide for approximating the values of external components for the CD4046BMS in a Phase-LockedLoop system. The selected external components must be within the following ranges: 5kΩ ≤ R1, R2, RS ≤ 1MΩ CHARACTERISTICS VCO Frequency C1 ≥ 100pF at VDD ≥ 5V PHASE COMPARATOR USED 1 C1 ≥ 50pF at VDD ≥ 10V DESIGN INFORMATION VCO Without Offset R2 = ∞ VCO With Offset f f MAX O f MAX 2fL f f MIN O 2fL f MIN VDD/2 VCO INPUT VOLTAGE For Number Signal Input Frequency Lock Range, 2fL Frequency Capture Range, 2fC VDD/2 VDD VCO INPUT VOLTAGE 2 Same as for Number 1 1 VCO will adjust to center frequency, fo 2 VCO will adjust to lowest operating frequency, fmin 1, 2 2fL = full VCO frequency range 1, 2 2fL = fmax - fmin 1 IN R3 VDD OUT (1), (2) Loop Filter Component Selection τI = R3C2 C2 IN R3 OUT R4 2fC ≈ 1 π √ 2πfL τ1 For 2 fC, see Ref. (2) C2 Phase Angle Between Signal and Comparator Locks On Harmonic of Center Frequency Signal Input Noise Rejection 2 fC = fL 1 90o at center frequency (fo) approximating 0o and 180o at ends of lock range (2fL) 2 Always 0o in lock 1 Yes 2 No 1 High 2 Low For further information, see (1) F. Gardner, “Phase-Lock Techniques” John Wiley and Sons, New York 1966 (2) G. S. Moschytz, “Miniaturized RC Filters Using Phase-Locked Loop”, BSTJ, May, 1965 7-892 CD4046BMS Block Diagram * SIGNAL 14 IN 16 VDD *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK PHASE COMPARATOR I COMPARATOR IN * 2 3 ÷N VDD PHASE COMP. I OUT PHASE COMP. II OUT PHASE COMPARATOR II VCO OUT 13 1 PHASE PULSES 4 R3 VSS 6 *VCO IN C1 7 LOW PASS FILTER 9 VCO R1 VSS 11 VSS SOURCE FOLLOWER 12 * C2 DEMODULATOR OUT R2 10 5 VSS RS INHIBIT VSS 8 15 ZENER VSS FIGURE 3. CMOS PHASE-LOCKED LOOP BLOCK DIAGRAM 106 o RI = 10kΩ AMBIENT TEMPERATURE (TA) = +25 C VCOIN = VDD/2, R2 = ∞, INHIBIT = VSS 105 104 SUPPLY VOLTAGE (VDD) = 15V 103 10 RI = 100kΩ 5V 10 10V 1 10-5 10-4 10-3 10-2 106 RI = 10kΩ 10V 5V 15V 10V 5V 15V RI = 1MΩ 2 10-1 1 CENTER FREQUENCY (fO) (Hz) CENTER FREQUENCY (fO) (Hz) Typical Performance Characteristics 10 VCO TIMING CAPACITOR (CI) (µF) TYPICAL CENTER FREQUENCY UNIT-TO-UNIT VARIATION VDD (V) ∆f/fO (%) 5 ±50 10 ±30 15 ±35 SUPPLY VOLTAGE (VDD) = 10V VCOIN = VDD/2, R = ∞, INHIBIT = VSS AMBIENT TEMPERATURE (TA) = -55oC 105 -55oC RI = 100kΩ +125oC 104 RI = 1MΩ -55oC +125oC 103 -55oC 102 +125oC 10 1 10-5 FIGURE 4. TYPICAL CENTER FREQUENCY AS A FUNCTION OF C1 AND R1 AT VDD = 5V, 10V, AND 15V 7-893 10-4 10-3 10-2 10-1 1 VCO TIMING CAPACITOR (CI) (µF) 10 FIGURE 5. CENTER FREQUENCY AS A FUNCTION OF C1 AND R1 FOR AMBIENT TEMPERATURE OF -55oC to +125oC CD4046BMS Typical Performance Characteristics (Continued) R2 = 10kΩ AMBIENT TEMPERATURE (TA) = +25oC VCOIN = VSS INHIBIT = VSS 105 SUPPLY VOLTAGE (VDD) = 15V 104 103 102 R2 = 1MΩ 10V 5V 15V 10V 5V 15V 10V 5V 10 R2 = 100kΩ 10 1 10-5 10-4 10-3 10-2 10-1 1 SUPPLY VOLTAGE (VDD) = 10V VCOIN = VSS INHIBIT = VSS R2 = 10kΩ FREQUENCY OFFSET (fMIN) (Hz) FREQUENCY OFFSET (fMIN) (Hz) 106 VCO TIMING CAPACITOR (CI) (µF) 106 AMBIENT TEMPERATURE (TA) = -55oC 105 +125oC 104 -55oC +125oC R2 = 1MΩ 103 R2 = 100kΩ -55oC 102 +125oC 10 TYPICAL fMIN UNIT-TO-UNIT VARIATION VDD (V) ∆fMIN/fMIN (%) 5 ±25 10 ±20 15 ±25 1 10-5 FIGURE 6. TYPICAL FREQUENCY OFFSET AS A FUNCTION OF C1 AND R2 FOR VDD = 5V, 10V, AND 15V 10-4 10-3 10-2 10-1 1 VCO TIMING CAPACITOR (CI) (µF) 10 FIGURE 7. FREQUENCY OFFSET AS A FUNCTION OF C1 AND R2 FOR AMBIENT TEMPERATURES OF -55oC to 125oC AMBIENT TEMPERATURE (TA) = +25oC fMAX WHEN VCOIN = VDD INHIBIT = VSS fMIN WHEN VCOIN = VSS 8 6 4 2 AMBIENT TEMPERATURE (TA) = +25oC VCOIN = VDD/2, R2 = ∞ INHIBIT = VSS CL = 50pF fMAX/fMIN 8 6 4 VCO POWER DISSIPATION (PD) (µW) 100 SUPPLY VOLTAGE (VDD) = 5V, 10V 2 15V 10 8 6 4 2 1 2 0.01 4 68 2 0.1 4 6 8 2 4 6 8 1 R2/R1 2 10 4 6 8 100 105 SUPPLY VOLTAGE (VDD) = 15V 104 CL = 50pF 1µF 10V 103 50pF 1µF 5V 102 50pF 1µF TYPICAL fMAX/fMIN UNIT-TO-UNIT VARIATION VDD (V) fMAX/fMIN (%) 5 ±12 10 ±8 15 ±12 10 2 10 4 6 8 2 4 6 102 8 2 103 4 6 8 104 R1 (kΩ) FIGURE 8. TYPICAL fMAX/fMIN AS A FUNCTION OF R2/R1 FIGURE 9. TYPICAL VCO POWER DISSIPATION AT CENTER FREQUENCY AS A FUNCTION OF R1 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 894 CD4046BMS (Continued) AMBIENT TEMPERATURE (TA) = +25oC VCOIN = VSS CL = 50pF 105 SUPPLY VOLTAGE (VDD) = 15V 104 10V CL = 50pF 1µF 5V 50pF 1µF 103 50pF 1µF 102 AMBIENT TEMPERATURE (TA) = +25oC VCOIN = VDD/2, R1 = R2 = ∞ VCO POWER DISSIPATION (PD) (µW) VCO POWER DISSIPATION (PD) (µW) Typical Performance Characteristics 104 SUPPLY VOLTAGE (VDD) = 15V 103 10V 102 101 10 2 4 6 8 2 4 6 8 102 10 2 4 6 1 8 103 5V 2 104 4 6 8 2 2kΩ 20kΩ 8 6 4 2kΩ 10V VSS OUTPUT CIRCUIT 103 8 6 4 2 5V 10 10 8 6 4 2 1 4 6 8 2 4 6 8 2 2 4 6 8 2 4 6 103 1 % LINEARITY = 2 4 6 8 10-1 8 104 FIGURE 12. AC-COUPLED SIGNAL INPUT VOLTAGE AS A FUNCTION OF SIGNAL INPUT FREQUENCY 8 6 4 f(4V) + f(6V) 2 1 f0 = 8 6 4 2 1 LINEARITY - PERCENT 2 10 CL = 50pF 2 1 8 6 4 2 % LINEARITY = f0 - f(7.5V) f0 10-1 2 10-1 0.1µF 100pF f(6V) + f(9V) 2 f0 = 4 6 8 2 1 4 6 8 0.01µF x 100 f0 2 10 R1 (kΩ) 4 0.1µF 6 8 102 2 4 6 8 103 FIGURE 13. TYPICAL VCO LINEARITY AS A FUNCTION OF R1 AND C1 AT VDD = 10V AMBIENT TEMPERATURE (TA) = +25oC VDD = 10V, VCOIN = 5V ± 1V, R2 = ∞ 8 6 4 f0 - f(5V) 10-1 10 10 SIGNAL INPUT FREQUENCY (fIN) (kHz) CL = 50pF 100pF 1000pF 2 2 AMBIENT TEMPERATURE (TA) = +25oC PHASE COMPARATOR II 2 104 2 13 VOUT 104 8 6 4 8 AMBIENT TEMPERATURE (TA) = +25oC VDD = 10V, VCOIN = 5V ± 1V, R2 = ∞ 8 6 4 LINEARITY - PERCENT AC-COUPLED SIGNAL INPUT VOLTAGE (mV) (PEAK-TO-PEAK, SINE WAVE) SUPPLY VOLTAGE (VDD) = 15V 102 4 6 FIGURE 11. TYPICAL SOURCE FOLLOWER POWER DISSIPATION AS A FUNCTION OF RS VDD 2 2 Rs (kΩ) FIGURE 10. TYPICAL VCO POWER DISSIPATION AT fMIN AS A FUNCTION OF R2 2 8 103 R2 (kΩ) 8 6 4 4 6 102 10 4 6 8 2 10 R1 (kΩ) 1000pF 0.01µF 0.1µF x 100 4 6 8 102 2 4 6 8 103 FIGURE 14. TYPICAL VCO LINEARITY AS A FUNCTION OF R1 AND C1 AT VDD = 15V 7-895 CD4046BMS I II III SIGNAL INPUT (TERM 14) VDD VCO OUTPUT (TERM 4) = COMPARATOR INPUT (TERM 3) PHASE COMPARATOR II OUTPUT (TERM 13) PHASE 13 COMPARATOR II OUTPUT -VDD -VSS VCO INPUT (TERM 9) = ∆ LOW-PASS FILTER OUTPUT -VDD -VSS 2KΩ 2KΩ VSS -VDD PHASE PULSE (TERM 1) 20KΩ -VSS NOTE: DASHED LINE IS AN OPEN CIRCUIT CONDITION (3RD STATE) FIGURE 15. TYPICAL WAVEFORMS FOR COS/MOS PHASE-LOCKED LOOP EMPLOYING PHASE COMPARATOR II IN LOCKED CONDICTION FIGURE 16. PHASE COMPARATOR II OUTPUT LOADING CIRCUIT Chip Dimensions and Pad Layout Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-896