Cypress CY6264-70SNC 8k x 8 static ram Datasheet

CY6264
8K x 8 Static RAM
Features
Functional Description
• Temperature Ranges
The CY6264 is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE1), an active
HIGH chip enable (CE2), and active LOW output enable (OE)
and three-state drivers. Both devices have an automatic
power-down feature (CE1), reducing the power consumption
by over 70% when deselected. The CY6264 is packaged in a
450-mil (300-mil body) SOIC.
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
• High Speed
— 55 ns
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2 and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 28-lead SNC
package
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE1 and WE
inputs are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins is present on
the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to ensure alpha immunity.
Logic Block Diagram
Pin Configuration
SOIC
Top View
I/O0
INPUT BUFFER
I/O2
SENSE AMPS
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
I/O1
8K x 8
ARRAY
I/O3
I/O4
NC
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A3
A2
A1
OE
A0
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
I/O5
I/O6
CE1
CE2
WE
COLUMN DECODER
POWER
DOWN
I/O7
Cypress Semiconductor Corporation
Document #: 001-02367 Rev. *A
A12
A10
A11
A0
A9
OE
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 8, 2006
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CY6264
Selection Guide
Range
Maximum Access Time
Maximum Operating Current
-55
-70
Unit
55
70
ns
Commercial
100
100
mA
Industrial
260
200
mA
Automotive-A
Maximum CMOS Standby Current
200
mA
Commercial
15
15
mA
Industrial
30
30
mA
30
mA
Automotive-A
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
DC Voltage Applied to Outputs
in High Z State[1] ............................................ –0.5V to +7.0V
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
DC Input Voltage[1] ......................................... –0.5V to +7.0V
Industrial
–40°C to +85°C
Automotive-A
–40°C to +85°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Electrical Characteristics Over the Operating Range
-55
Parameter
Description
Test Conditions
Min.
-70
Max.
Min.
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
2.4
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
2.2
VCC
VIL
Input LOW Voltage[1]
–0.5
0.8
IIX
Input Leakage Current
–5
+5
–5
IOZ
Output Leakage Current GND < VI < VCC, Output Disabled
+5
–5
ICC
VCC Operating
Supply Current
VCC = Max.,IOUT = 0 mA
Automatic CE1
Power–Down Current
Max. VCC, CE1 > VIH,
Min. Duty Cycle=100%
V
2.2
VCC
V
–0.5
0.8
V
+5
µA
+5
µA
Com’l
100
100
mA
Ind’l
260
200
–5
200
Com’l
20
20
Ind’l
50
40
Auto-A
ISB2
Automatic CE1
Power–Down Current
V
0.4
Auto-A
ISB1
Unit
2.4
0.4
GND < VI < VCC
Max.
Max. VCC, CE1 > VCC – 0.3V, Com’l
VIN > VCC – 0.3V or VIN < 0.3V
Ind’l
mA
40
15
15
30
30
Auto-A
mA
30
Capacitance[2]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
7
pF
7
pF
Notes:
1. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.
2. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-02367 Rev. *A
Page 2 of 9
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CY6264
AC Test Loads and Waveforms
R1 481Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R1 481Ω
5V
OUTPUT
ALL INPUT PULSES
3.0V
5 pF
R2
255Ω
INCLUDING
JIG AND
SCOPE
(a)
R2
255Ω
GND
90%
10%
90%
10%
< 5 ns
< 5 ns
(b)
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
Switching Characteristics Over the Operating Range[3]
-55
Parameter
Description
Min.
-70
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
55
tOHA
Data Hold from Address Change
tACE1
CE1 LOW to Data Valid
55
70
ns
tACE2
CE2 HIGH to Data Valid
40
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to Low Z
OE HIGH to High
tLZCE1
CE1 LOW to Low
Z[5]
tLZCE2
CE2 HIGH to Low Z
CE1 HIGH to High
CE2 LOW to High Z
tPU
CE1 LOW to Power-Up
tPD
ns
70
5
ns
ns
5
20
ns
30
ns
5
5
ns
3
5
ns
Z[4, 6]
tHZCE
WRITE
5
3
Z[4]
tHZOE
70
55
20
0
CE1 HIGH to Power-Down
30
0
25
ns
ns
30
ns
CYCLE[6]
tWC
Write Cycle Time
50
70
ns
tSCE1
CE1 LOW to Write End
40
60
ns
tSCE2
CE2 HIGH to Write End
30
50
ns
tAW
Address Set-Up to Write End
40
55
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
25
40
ns
tSD
Data Set-Up to Write End
25
35
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High Z[4]
tLZWE
WE HIGH to Low Z
0
20
5
ns
30
5
ns
ns
Notes:
3. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
4. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
6. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 001-02367 Rev. *A
Page 3 of 9
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CY6264
Switching Waveforms
Read Cycle No. 1[7, 8]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2[9, 10]
tRC
CE1
CE2
tACE
OE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tHZCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
Notes:
7. Device is continuously selected. OE, CE = VIL. CE2 = VIH.
8. Address valid prior to or coincident with CE transition LOW.
9. WE is HIGH for read cycle.
10. Data I/O is High Z if OE = VIH, CE1 = VIH, or WE = VIL.
Document #: 001-02367 Rev. *A
Page 4 of 9
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CY6264
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[8, 10]
tWC
ADDRESS
tSCE1
CE1
CE2
tSCE2
OE
tAW
WE
tHA
tSA
tPWE
tHD
tSD
DATAIN VALID
DATA IN
tHZWE
DATA I/O
tLZWE
HIGH IMPEDANCE
DATA UNDEFINED
Write Cycle No. 2 (CE Controlled)[8, 10, 11]
tWC
ADDRESS
CE1
tSCE1
tSA
tSCE2
CE2
tAW
tHA
tPWE
WE
tSD
tHD
DATAIN VALID
DATA IN
tHZWE
DATA I/O
HIGH IMPEDANCE
DATA UNDEFINED
Note:
11. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 001-02367 Rev. *A
Page 5 of 9
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CY6264
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
1.2
NORMALIZED ICC, ISB
ICC
0.8
0.6
0.4
ISB
0.2
0.0
4.0
4.5
5.0
5.5
ICC
0.8
0.6
0.4
VCC =5.0V
VIN =5.0V
0.2
ISB
0.0
−55
6.0
25
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.6
NORMALIZED tAA
NORMALIZED t AA
1.4
1.3
1.2
1.1
TA =25°C
1.0
1.4
1.2
1.0
VCC =5.0V
0.8
0.9
4.5
5.0
5.5
6.0
0.6
−55
3.0
30.0
2.5
25.0
2.0
1.5
1.0
25
3.0
4.0
SUPPLY VOLTAGE(V)
Document #: 001-02367 Rev. *A
20
0
0.0
1.0
5.0
3.0
4.0
OUTPUT SINK CURRENT
vs.OUTPUT VOLTAGE
140
120
100
VCC =5.0V
TA =25°C
80
60
40
20
0
0.0
125
20.0
15.0
10.0
0.0
2.0
OUTPUT VOLTAGE (V)
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NORMALIZED ICC vs. CYCLE TIME
1.25
VCC =4.5V
TA =25°C
5.0
0.5
2.0
40
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
DELTA tAA (ns)
NORMALIZED I PO
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
1.0
VCC =5.0V
TA =25°C
60
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
0.0
0.0
80
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
0.8
4.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
100
125
OUTPUT SINK CURRENT (mA)
1.0
1.0
120
0
200
400
600
800 1000
CAPACITANCE (pF)
NORMALIZED I CC
NORMALIZED ICC, ISB
1.4
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
VCC =5.0V
TA =25°C
VCC =0.5V
1.00
0.75
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Page 6 of 9
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CY6264
Truth Table
CE1
CE2
WE
OE
Input/Output
Mode
H
X
X
X
High Z
Deselect/Power-Down
X
L
X
X
High Z
Deselect
L
H
H
L
Data Out
Read
L
H
L
X
Data In
Write
L
H
H
H
High Z
Deselect
Address Designators
Address
Name
Address
Function
Pin
Number
A4
X3
2
A5
X4
3
A6
X5
4
A7
X6
5
A8
X7
6
A9
Y1
7
A10
Y4
8
A11
Y3
9
A12
Y0
10
A0
Y2
21
A1
X0
23
A2
X1
24
A3
X2
25
Document #: 001-02367 Rev. *A
Page 7 of 9
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CY6264
Ordering Information
Speed
(ns)
55
70
Ordering Code
CY6264-55SNXC
Package
Diagram
51-85092
Operating
Range
Package Type
28-lead (300-mil Narrow Body) SNC (Pb-Free)
Commercial
CY6264-55SNXI
28-lead (300-mil Narrow Body) SNC (Pb-Free)
Industrial
CY6264-70SNC
28-lead (300-mil Narrow Body) SNC
CY6264-70SNXC
28-lead (300-mil Narrow Body) SNC (Pb-Free)
CY6264-70SNI
28-lead (300-mil Narrow Body) SNC
CY6264-70SNXI
28-lead (300-mil Narrow Body) SNC (Pb-Free)
CY6264-70SNXA
28-lead (300-mil Narrow Body) SNC (Pb-Free)
Commercial
Industrial
Automotive-A
Please contact your local Cypress sales representative for availability of these parts
Package Diagram
28-lead (300 mil) SNC Package Outline (Narrow Body) (51-85092)
PIN 1 ID
MIN.
MAX.
DIMENSIONS IN INCHES
OMEDATA
CSPI
0.390
0.420
0.463
0.477
0.291
0.300
0.026
0.032
DETAIL "B"
0.015
0.020
0.014
0.020
DETAIL "A"
SEATING PLANE
0.702
0.710
0.390
0.420
B
0.094
0.110
0.004
A
0.050
TYP.
0.002
0.014
0.020
0.042
0.008
0.012
51-85092-*B
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-02367 Rev. *A
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY6264
Document History Page
Document Title: CY6264 8K x 8 Static RAM
Document Number: 001-02367
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
384870
See ECN
PCI
Spec # change from 38-00425 to 001-02367
*A
488954
See ECN
VKN
Added Automotive product
Added 55 ns Industrial spec
Removed SOIC package from the product offering
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated ordering Information table
Document #: 001-02367 Rev. *A
Page 9 of 9
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