Renesas BB301MAW-TL-E Built in biasing circuit mos fet ic vhf rf amplifier Datasheet

BB301M
Built in Biasing Circuit MOS FET IC
VHF RF Amplifier
REJ03G0824-0300
(Previous ADE-208-506A)
Rev.3.00
Aug.10.2005
Features
• Built in Biasing Circuit; To reduce using parts cost & PC board space.
• Low noise characteristics;
(NF = 1.3 dB typ. at f = 200 MHz)
• Withstanding to ESD;
Built in ESD absorbing diode. Withstand up to 200V at C=200pF, Rs=0 conditions.
• Provide mini mold packages; MPAK-4(SOT-143Rmod)
Outline
RENESAS Package code: PLSP0004ZA-A
(Package name: MPAK-4)
2
3
1
4
Notes:
1. Marking is “AW–”.
2. BB301M is individual type number of RENESAS BBFET.
Rev.3.00 Aug 10, 2005 page 1 of 7
1. Source
2. Gate1
3. Gate2
4. Drain
BB301M
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate1 to source voltage
Symbol
VDS
VG1S
Gate2 to source voltage
Drain current
Channel power dissipation
Channel temperature
Storage temperature
Ratings
6
+6
–0
±6
25
150
150
–55 to +150
VG2S
ID
Pch
Tch
Tstg
Unit
V
V
V
mA
mW
°C
°C
Electrical Characteristics
(Ta = 25°C)
Item
Drain to source breakdown voltage
Gate1 to source breakdown voltage
Symbol
V(BR)DSS
V(BR)G1SS
Min
6
+6
Typ
—
—
Max
—
—
Unit
V
V
Test conditions
ID = 200 µA, VG1S = VG2S = 0
IG1 = +10 µA, VG2S = VDS = 0
Gate2 to source breakdown voltage
Gate1 to source cutoff current
V(BR)G2SS
IG1SS
±6
—
—
—
—
+100
V
nA
IG2 = ±10 µA, VG1S = VDS = 0
VG1S = +5 V, VG2S = VDS = 0
Gate2 to source cutoff current
Gate1 to source cutoff voltage
IG2SS
VG1S(off)
—
0.4
—
—
±100
1.0
nA
V
VG2S = ±5 V, VG1S = VDS = 0
Gate2 to source cutoff voltage
VG2S(off)
0.4
—
1.0
V
Drain current
ID(op)
10
15
20
mA
VDS = 5 V, VG1 = 5 V
VG2S = 4 V, RG = 100 kΩ
Forward transfer admittance
|yfs|
15
20
—
mS
Input capacitance
Output capacitance
Reverse transfer capacitance
Power gain
Noise figure
Ciss
Coss
Crss
PG
NF
2.2
0.9
—
22
—
3.0
1.2
0.018
26
1.3
3.9
1.6
0.04
—
1.9
pF
pF
pF
dB
dB
VDS = 5 V, VG1 = 5 V, VG2S =4 V
RG = 100 kΩ, f = 1 kHz
VDS = 5 V, VG1 = 5 V
VG2S =4 V, RG = 100 kΩ
f = 1 MHz
VDS = 5 V, VG1 = 5 V, VG2S =4 V
RG = 100 kΩ, f = 200 MHz
Rev.3.00 Aug 10, 2005 page 2 of 7
VDS = 5 V, VG2S = 4 V
ID = 100 µA
VDS = 5 V, VG1S = 5 V
ID = 100 µA
BB301M
Main Characteristics
Test Circuit for Operating Items (ID(op) , |yfs|, Ciss, Coss, Crss, NF, PG)
VG2
VG1
RG
Gate 2
Gate 1
Drain
Source
A
ID
Equivalent Circuit
Gate 2
Drain
Gate 1
Source
Application Circuit
VDS = 5 V
VAGC = 4 to 0.3 V
BBFET
Input
RG
VGG = 5 V
Rev.3.00 Aug 10, 2005 page 3 of 7
RFC
Output
BB301M
Typical Output Characteristics
30
25
150
100
50
20
15
10
5
RG
50
100
150
0
200
1
2
Ω
k
82 k Ω
0
10 k Ω
0
2
1 0kΩ
15 k Ω
180
0 kΩ
= 22
3
4
5
Drain to Source Voltage VDS (V)
Drain Current vs.
Gate2 to Source Voltage
Drain Current vs. Gate1 Voltage
20
120 k Ω
150 k Ω
180 k Ω
R G = 220 k Ω
10
5
12
V
100 k Ω
15
16
3
82 k Ω
VDS = 5 V
RG = 82 kΩ
V
Ω
k
Ω
68 k
Drain Current ID (mA)
20
56
47
kΩ
25
4
0
Ambient Temperature Ta (°C)
Drain Current ID (mA)
VG2S = 4 V
VG1 = VDS
47
5 k
68 6 k Ω
k Ω
Ω
200
Drain Current ID (mA)
Channel Power Dissipation Pch (mW)
Maximum Channel Power
Dissipation Curve
2V
8
4
VG2S = 1 V
VDS = VG1 = 5 V
0
1
2
3
0
5
4
4
5
Drain Current vs. Gate1 Voltege
Drain Current vs. Gate1 Voltege
20
V
Drain Current ID (mA)
VDS = 5 V
RG = 100 kΩ
3
V
4
Drain Current ID (mA)
3
Gate1 Voltage VG1 (V)
12
8
2V
4
0
2
Gate2 to Source Voltage VG2S (V)
20
16
1
VG2S = 1 V
1
2
3
4
Gate1 Voltage VG1 (V)
Rev.3.00 Aug 10, 2005 page 4 of 7
16
VDS = 5 V
RG = 150 kΩ
12
3V
4V
8
2V
4
VG2S = 1 V
5
0
1
2
3
4
Gate1 Voltage VG1 (V)
5
BB301M
Forward Transfer Admittance
vs. Gate1 Voltage
30
VDS = 5 V
RG = 82 kΩ
f = 1 kHz
25
4V
3V
20
15
2V
10
5
VG2S = 1 V
0
1
2
3
4
5
Forward Transfer Admittance |yfs| (mS)
Forward Transfer Admittance |yfs| (mS)
Forward Transfer Admittance
vs. Gate1 Voltage
30
25
3V
15
2V
10
5
VG2S = 1 V
0
1
2
3
4
5
Gate1 Voltage VG1 (V)
Forward Transfer Admittance
vs. Gate1 Voltage
Power Gain vs. Gate Resistance
30
20
VDS = 5 V
RG = 150 kΩ
f = 1 kHz
16
4V
Power Gain PG (dB)
Forward Transfer Admittance |yfs| (mS)
4V
20
Gate1 Voltage VG1 (V)
3V
12
2V
8
4
25
20
15
10
5
VG2S = 1 V
0
1
2
3
4
0
10
5
Gate1 Voltage VG1 (V)
50
100 200
500 1000
30
VDS = 5 V
VG1= 5 V
VG2S = 4 V
f = 200 MHz
Power Gain PG (dB)
25
2
1
0
10
20
Power Gain vs. Drain Current
4
3
VDS = 5 V
VG1 = 5 V
VG2S = 4 V
f = 200 MHz
Gate Resistance RG (kΩ)
Noise Figure vs. Gate Resistance
Noise Figure NF (dB)
VDS = 5 V
RG = 100 kΩ
f = 1 kHz
20
50
100 200
500 1000
Gate Resistance RG (kΩ)
Rev.3.00 Aug 10, 2005 page 5 of 7
20
15
10
5
0
VDS = 5 V
VG1 = 5 V
VG2S = 4 V
RG = variable
f = 200 MHz
5
10
15
20
25
Drain Current ID (mA)
30
BB301M
Drain Current vs. Gate Resistance
Noise Figure vs. Drain Current
30
VDS = 5 V
VG1 = 5 V
VG2S = 4 V
RG = variable
f = 200 MHz
3
25
Drain Current ID (mA)
Noise Figure NF (dB)
4
2
1
0
5
10
15
20
25
20
15
10
5
0
10
30
Drain Current ID (mA)
50
100 200
500 1000
Input Capacitance vs.
Gate2 to Source Voltage
4
60
VDS = 5 V
VG1 = 5 V
VG2S = 4 V
RG = 100 kΩ
f = 200 MHz
50
40
Input Capacitance Ciss (pF)
Gain Reduction GR (dB)
20
Gate Resistance RG (kΩ)
Gain Reduction vs.
Gate2 to Source Voltage
30
20
10
0
VDS = 5 V
VG1 = 5 V
VG2S = 4 V
1
2
3
4
Gate2 to Source Voltage VG2S (V)
Rev.3.00 Aug 10, 2005 page 6 of 7
5
3
2
1
0
VDS = 5 V
VG1 = 5 V
RG = 100 kΩ
f = 1 MHz
1
2
3
4
5
Gate2 to Source Voltage VG2S (V)
BB301M
Package Dimensions
JEITA Package Code
RENESAS Code
SC-61AA
Package Name
PLSP0004ZA-A
MASS[Typ.]
MPAK-4 / MPAK-4V
D
0.013g
A
e
e2
b1
Q
c
B
B
E
HE
Reference
Symbol
L
A
LP
L1
A
A3
x M S
b
A
e2
A2
e
I1
A
b5
S
b
b2
e1
A1
y S
b1
b3
c1
c
c1
I1
c
b4
A-A Section
B-B Section
Pattern of terminal position areas
A
A1
A2
A3
b
b1
b2
b3
c
c1
D
E
e
e2
HE
L
L1
LP
x
y
b4
b5
e1
I1
Q
Dimension in Millimeters
Min
1.0
0
1.0
0.35
0.55
0.1
2.7
1.35
2.2
0.35
0.15
0.25
Nom
1.1
0.25
0.42
0.62
0.4
0.6
0.13
0.11
1.5
0.95
0.85
2.8
Max
1.3
0.1
1.2
0.5
0.7
0.15
3.1
1.65
3.0
0.75
0.55
0.65
0.05
0.05
0.55
0.75
1.95
1.05
0.3
Ordering Information
Part Name
BB301MAW-TL-E
Quantity
3000
Shipping Container
φ 178 mm Reel, 8 mm Emboss Taping
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.
Rev.3.00 Aug 10, 2005 page 7 of 7
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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