BCW70LT1 General Purpose Transistors PNP Silicon http://onsemi.com MAXIMUM RATINGS Rating Symbol Value Unit Collector–Emitter Voltage VCEO –45 Vdc Emitter–Base Voltage VEBO –5.0 Vdc IC –100 mAdc Collector Current — Continuous COLLECTOR 3 1 BASE 2 EMITTER THERMAL CHARACTERISTICS Characteristic Symbol Max Unit Total Device Dissipation FR-5 Board (1) TA = 25°C Derate above 25°C PD 225 mW 1.8 mW/°C RθJA 556 °C/W PD 300 mW 2.4 mW/°C RθJA 417 °C/W TJ, Tstg – 55 to +150 °C Thermal Resistance, Junction to Ambient Total Device Dissipation Alumina Substrate, (2) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Junction and Storage Temperature 3 1 2 SOT–23 (TO–236AB) CASE 318 STYLE 6 DEVICE MARKING 1. FR–5 = 1.0 x 0.75 x 0.062 in. 2. Alumina = 0.4 x 0.3 x 0.024 in. 99.5% alumina H2x x = Monthly Date Code ORDERING INFORMATION Device BCW70LT1 Package Shipping SOT–23 3000 Units/Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 0 1 Publication Order Number: BCW70LT1/D BCW70LT1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Min Max Unit Collector–Emitter Breakdown Voltage (IC = –2.0 mAdc, IB = 0) V(BR)CEO –45 — Vdc Collector–Emitter Breakdown Voltage (IC = –100 µAdc, VEB = 0) V(BR)CES –50 — Vdc Emitter–Base Breakdown Voltage (IE = –10 µAdc, IC = 0) V(BR)EBO –5.0 — Vdc — — –100 –10 nAdc µAdc hFE 215 500 — Collector–Emitter Saturation Voltage (IC = –10 mAdc, IB = –0.5 mAdc) VCE(sat) — –0.3 Vdc Base–Emitter On Voltage (IC = –2.0 mAdc, VCE = –5.0 Vdc) VBE(on) –0.6 –0.75 Vdc Cobo — 7.0 pF NF — 10 dB Characteristic OFF CHARACTERISTICS Collector Cutoff Current (VCB = –20 Vdc, IE = 0) (VCB = –20 Vdc, IE = 0, TA = 100°C) ICBO ON CHARACTERISTICS DC Current Gain (IC = –2.0 mAdc, VCE = –5.0 Vdc) SMALL–SIGNAL CHARACTERISTICS Output Capacitance (IE = 0, VCB = –10 Vdc, f = 1.0 MHz) Noise Figure (IC = –0.2 mAdc, VCE = –5.0 Vdc, RS = 2.0 kΩ, f = 1.0 kHz, BW = 200 Hz) http://onsemi.com 2 BCW70LT1 TYPICAL NOISE CHARACTERISTICS (VCE = – 5.0 Vdc, TA = 25°C) 10 7.0 IC = 10 µA 5.0 In, NOISE CURRENT (pA) en, NOISE VOLTAGE (nV) 1.0 7.0 5.0 BANDWIDTH = 1.0 Hz RS ≈ 0 30 µA 3.0 100 µA 300 µA 1.0 mA 2.0 BANDWIDTH = 1.0 Hz RS ≈ ∞ IC = 1.0 mA 3.0 2.0 300 µA 1.0 0.7 0.5 100 µA 30 µA 0.3 0.2 1.0 10 µA 0.1 10 20 50 100 200 500 1.0 k f, FREQUENCY (Hz) 2.0 k 5.0 k 10 10 k 20 50 Figure 1. Noise Voltage 100 200 500 1.0 k 2.0 k f, FREQUENCY (Hz) 5.0 k 10 k Figure 2. Noise Current NOISE FIGURE CONTOURS 1.0 M 500 k BANDWIDTH = 1.0 Hz 200 k 100 k 50 k 20 k 10 k 0.5 dB 5.0 k 1.0 dB 2.0 k 1.0 k 500 2.0 dB 3.0 dB 200 100 RS , SOURCE RESISTANCE (OHMS) RS , SOURCE RESISTANCE (OHMS) (VCE = – 5.0 Vdc, TA = 25°C) 20 30 50 70 100 200 300 IC, COLLECTOR CURRENT (µA) BANDWIDTH = 1.0 Hz 200 k 100 k 50 k 20 k 10 k 0.5 dB 5.0 k 1.0 dB 2.0 k 1.0 k 500 2.0 dB 3.0 dB 200 100 5.0 dB 10 1.0 M 500 k 500 700 1.0 k 5.0 dB 10 20 RS , SOURCE RESISTANCE (OHMS) Figure 3. Narrow Band, 100 Hz 1.0 M 500 k 30 50 70 100 200 300 IC, COLLECTOR CURRENT (µA) 500 700 1.0 k Figure 4. Narrow Band, 1.0 kHz 10 Hz to 15.7 kHz 200 k 100 k 50 k ƪ Noise Figure is Defined as: 20 k 10 k NF 0.5 dB 1.0 dB 2.0 dB 3.0 dB 5.0 dB 200 100 10 20 30 50 70 100 200 300 en2 ƫ ) 4KTRS ) In 2RS2 1ń2 4KTRS en = Noise Voltage of the Transistor referred to the input. (Figure 3) I = Noise Current of the Transistor referred to the input. n (Figure 4) K = Boltzman’s Constant (1.38 x 10–23 j/°K) T = Temperature of the Source Resistance (°K) R = Source Resistance (Ohms) S 5.0 k 2.0 k 1.0 k 500 + 20 log10 500 700 1.0 k IC, COLLECTOR CURRENT (µA) Figure 5. Wideband http://onsemi.com 3 BCW70LT1 100 1.0 TA = 25°C IC, COLLECTOR CURRENT (mA) VCE , COLLECTOR–EMITTER VOLTAGE (VOLTS) TYPICAL STATIC CHARACTERISTICS 0.8 IC = 1.0 mA 0.6 10 mA 50 mA 100 mA 0.4 0.2 0 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 IB, BASE CURRENT (mA) TA = 25°C PULSE WIDTH = 300 µs 80 DUTY CYCLE ≤ 2.0% 300 µA 150 µA 40 100 µA 50 µA 20 0 5.0 10 0 20 5.0 10 15 20 25 30 35 VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS) θV, TEMPERATURE COEFFICIENTS (mV/°C) TJ = 25°C V, VOLTAGE (VOLTS) 1.2 1.0 0.8 VBE(sat) @ IC/IB = 10 0.6 VBE(on) @ VCE = 1.0 V 0.4 0.2 VCE(sat) @ IC/IB = 10 0 0.5 1.0 2.0 5.0 10 20 IC, COLLECTOR CURRENT (mA) 40 Figure 7. Collector Characteristics 1.4 0.2 250 µA 200 µA 60 Figure 6. Collector Saturation Region 0.1 IB = 400 µA 350 µA 50 1.6 *APPLIES for IC/IB ≤ hFE/2 0.8 *qVC for VCE(sat) – 55°C to 25°C 0.8 25°C to 125°C 1.6 2.4 0.1 100 25°C to 125°C 0 Figure 8. “On” Voltages qVB for VBE 0.2 – 55°C to 25°C 0.5 1.0 2.0 5.0 10 20 IC, COLLECTOR CURRENT (mA) Figure 9. Temperature Coefficients http://onsemi.com 4 50 100 BCW70LT1 TYPICAL DYNAMIC CHARACTERISTICS 500 300 200 200 100 70 50 30 tr 20 10 7.0 5.0 1.0 100 70 50 tf 30 td @ VBE(off) = 0.5 V 20 2.0 3.0 50 70 20 30 5.0 7.0 10 IC, COLLECTOR CURRENT (mA) 10 –1.0 100 – 2.0 – 3.0 – 5.0 – 7.0 –10 – 20 – 30 IC, COLLECTOR CURRENT (mA) – 50 – 70 –100 Figure 11. Turn–Off Time 500 10 TJ = 25°C TJ = 25°C 7.0 VCE = 20 V 300 Cib C, CAPACITANCE (pF) f T, CURRENT–GAIN — BANDWIDTH PRODUCT (MHz) Figure 10. Turn–On Time 5.0 V 200 100 r(t) TRANSIENT THERMAL RESISTANCE (NORMALIZED) VCC = – 3.0 V IC/IB = 10 IB1 = IB2 TJ = 25°C ts 300 t, TIME (ns) t, TIME (ns) 1000 700 500 VCC = 3.0 V IC/IB = 10 TJ = 25°C 5.0 3.0 2.0 Cob 70 50 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 1.0 0.05 50 0.1 0.2 0.5 1.0 2.0 5.0 IC, COLLECTOR CURRENT (mA) VR, REVERSE VOLTAGE (VOLTS) Figure 12. Current–Gain — Bandwidth Product Figure 13. Capacitance 1.0 0.7 0.5 10 20 50 D = 0.5 0.3 0.2 0.2 0.1 0.1 0.07 0.05 FIGURE 16 0.05 P(pk) 0.02 0.03 0.02 t1 0.01 0.01 0.01 0.02 SINGLE PULSE 0.05 0.1 0.2 0.5 1.0 DUTY CYCLE, D = t1/t2 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 (SEE AN–569) ZθJA(t) = r(t) • RθJA TJ(pk) – TA = P(pk) ZθJA(t) t2 2.0 5.0 10 20 50 t, TIME (ms) 100 200 Figure 14. Thermal Response http://onsemi.com 5 500 1.0 k 2.0 k 5.0 k 10 k 20 k 50 k 100 BCW70LT1 104 DESIGN NOTE: USE OF THERMAL RESPONSE DATA IC, COLLECTOR CURRENT (nA) VCC = 30 V A train of periodical power pulses can be represented by the model as shown in Figure 16. Using the model and the device thermal response the normalized effective transient thermal resistance of Figure 14 was calculated for various duty cycles. To find ZθJA(t), multiply the value obtained from Figure 14 by the steady state value RθJA. Example: Dissipating 2.0 watts peak under the following conditions: t1 = 1.0 ms, t2 = 5.0 ms (D = 0.2) Using Figure 14 at a pulse width of 1.0 ms and D = 0.2, the reading of r(t) is 0.22. 103 ICEO 102 101 ICBO AND ICEX @ VBE(off) = 3.0 V 100 10–1 10–2 –4 0 –2 0 0 The peak rise in junction temperature is therefore ∆T = r(t) x P(pk) x RθJA = 0.22 x 2.0 x 200 = 88°C. For more information, see AN–569. + 20 + 40 + 60 + 80 + 100 + 120 + 140 + 160 TJ, JUNCTION TEMPERATURE (°C) Figure 15. Typical Collector Leakage Current http://onsemi.com 6 BCW70LT1 INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 inches mm SOT–23 SOT–23 POWER DISSIPATION SOLDERING PRECAUTIONS The power dissipation of the SOT–23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT–23 package, PD can be calculated as follows: PD = The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 225 milliwatts. PD = 150°C – 25°C 556°C/W = 225 milliwatts The 556°C/W for the SOT–23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 7 BCW70LT1 PACKAGE DIMENSIONS SOT–23 (TO–236AB) CASE 318–08 ISSUE AF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. A L 3 B S 1 V DIM A B C D G H J K L S V 2 G C D H J K INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0350 0.0440 0.0150 0.0200 0.0701 0.0807 0.0005 0.0040 0.0034 0.0070 0.0140 0.0285 0.0350 0.0401 0.0830 0.1039 0.0177 0.0236 MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.89 1.11 0.37 0.50 1.78 2.04 0.013 0.100 0.085 0.177 0.35 0.69 0.89 1.02 2.10 2.64 0.45 0.60 STYLE 6: PIN 1. BASE 2. EMITTER 3. COLLECTOR Thermal Clad is a trademark of the Bergquist Company ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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