NBSG16VS 2.5V/3.3VSiGe Differential Receiver/Driver with Variable Output Swing Description The NBSG16VS is a differential receiver/driver targeted for high frequency applications that require variable output swing. The device is functionally equivalent to the EP16VS device with much higher bandwidth and lower EMI capabilities. This device may be used for applications driving VCSEL lasers. Inputs incorporate internal 50 termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The output amplitude is varied by applying a voltage to the VCTRL input pin. Outputs are variable swing ECL from 100 mV to 750 mV amplitude, optimized for operation from VCC − VEE = 3.0 V to 3.465 V. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used as a reference voltage for single−ended NECL or PECL inputs and the VMM pin is used as a reference voltage for LVCMOS inputs. For single−ended input operation, the unused complementary differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC coupled inputs. When used, decouple VBB and VMM via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open. Features • • • • • • • • • • • Maximum Input Clock Frequency up to 12 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical 40 ps Typical Rise and Fall Times (VCTRL = VCC − 1 V) 120 ps Typical Propagation Delay (VCTRL = VCC − 1 V) Variable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Variable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V Output Level (100 mV to 750 mV Peak−to−Peak Output; VCC − VEE = 3.0 V to 3.465 V), Differential Output Only 50 Internal Input Termination Resistors Compatible with Existing 2.5 V/3.3 V EP Devices VBB and VMM Reference Voltage Output Pb−Free Packages are Available © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 7 1 http://onsemi.com MARKING DIAGRAMS* SG 11 ALYW FCBGA−16 BA SUFFIX CASE 489 ÇÇ ÇÇ 16 1 QFN−16 MN SUFFIX CASE 485G A L Y W G SG 16VS ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. Publication Order Number: NBSG16VS/D NBSG16VS 1 2 VEE NC 3 4 VEE 16 A B D VTD VCTRL VBB VMM VEE 15 13 14 Exposed Pad (EP) VEE VCC VTD 1 D 2 12 VCC 11 Q Q NBSG16VS C D VTD VCC Q D VEE VBB VMM VEE D 3 10 Q VTD 4 9 VCC 5 VEE Figure 1. BGA−16 Pinout (Top View) 6 7 8 NC VCTRL VEE Figure 2. QFN−16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin BGA QFN Name I/O C2 1 VTD − C1 2 D ECL, CML, LVCMOS, LVDS, LVTTL Input Inverted Differential Input. Internal 75 k to VEE and 36.5 k to VCC. B1 3 D ECL, CML, LVCMOS, LVDS, LVTTL Input Noninverted Differential Input. Internal 75 k to VEE. B2 4 VTD − Internal 50 Termination Pin. See Table 2. A1,D1,A4, D4 5,8,13,16 VEE − Negative Supply Voltage A2 6 NC − No Connect A3 7 VCTRL B3,C3 9,12 VCC − B4 10 Q RSECL Output Noninverted Differential Output. Typically Terminated with 50 to VTT = VCC − 2 V C4 11 Q RSECL Output Inverted Differential Output. Typically Terminated with 50 to VTT = VCC − 2 V D3 14 VMM − LVCMOS Reference Voltage Output. (VCC − VEE)/2 D2 15 VBB − ECL Reference Voltage Output N/A − EP − Exposed Pad. (Note 2) Description Internal 50 Termination Pin. See Table 2. Output Amplitude Swing Control. Bypass Pin to VCC through 0.1 F Capacitor. Positive Supply Voltage 1. The NC pin is electrically connected to the die and must be left open. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat−sinking conduit. 3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self−oscillation. http://onsemi.com 2 NBSG16VS +3.3 V VCC + 0.1 F VCTRL VCTRL VTD VCC 50 Q D D Q D D Q OUT Q OUT 75 K 75 K 50 Q OUT Q OUT 50 Q 50 VMM 36.5 K VTD VMM 36.5 K 50 VCTRL VCC RVAR 50 75 K 75 K Q VTD 140 140 VBB VBB VTD VCC − 2 V VEE VEE Figure 3. Logic Diagram/ Voltage Source Implementation Figure 4. Alternative Voltage Source Implementation Table 2. INTERFACING OPTIONS INTERFACING OPTIONS CONNECTIONS CML Connect VTD and VTD to VCC LVDS Connect VTD and VTD Together AC−COUPLED Bias VTD and VTD Inputs within Common Mode Range (VIHCMR) RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL An external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL. LVCMOS VMM should be connected to the unused complementary differential input. http://onsemi.com 3 NBSG16VS Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor (D, D) 75 k Internal Input Pullup Resistor (D) 36.5 k ESD Protection Human Body Model Machine Model Moisture Sensitivity (Note 4) FCBGA−16 QFN−16 Flammability Rating > 2 kV > 100 V Pb Pkg Pb−Free Pkg Level 3 Level 1 N/A Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 192 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 4. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Rating Unit VCC Symbol Positive Power Supply Parameter VEE = 0 V Condition 1 3.6 V VEE Negative Power Supply VCC = 0 V −3.6 V VI Positive Input Negative Input VEE = 0 V VCC = 0 V 3.6 −3.6 V V VINPP Differential Input Voltage 2.8 |VCC − VEE| V V IOUT Output Current Continuous Surge 25 50 mA mA IIN Input Current Through RT (50 Resistor) Static Surge 45 80 mA mA IBB VBB Sink/Source 1 mA IMM VMM Sink/Source 1 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction−to−Ambient) (Note 5) 0 lfpm 500 lfpm 0 lfpm 500 lfpm 16 FCBGA 16 FCBGA 16 QFN 16 QFN 108 86 41.6 35.2 °C/W °C/W °C/W °C/W JC Thermal Resistance (Junction−to−Case) 2S2P (Note 5) 2S2P (Note 6) 16 FCBGA 16 QFN 5.0 4.0 °C/W °C/W Tsol Wave Solder 225 225 °C |D − D| Condition 2 VI v VCC VI w VEE VCC − VEE w 2.8 V VCC − VEE t 2.8 V Pb Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 5. JEDEC standard 51−6 multilayer board − 2S2P (2 signal, 2 power). 6. JEDEC standards multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NBSG16VS Table 5. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 7) −40°C Symbol Characteristic IEE Negative Power Supply Current VOH Output HIGH Voltage (Note 8) VOL Output LOW Voltage (Note 8) (Max Swing) (VCTRL = VCC − 600 mV) 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 18 25 32 18 25 32 18 25 32 mA 1315 1440 1565 1305 1430 1555 1305 1430 1555 mV 645 1090 765 1210 885 1330 605 1035 725 1155 845 1275 600 1010 720 1130 840 1250 mV VIH Input HIGH Voltage (Single−Ended) (Notes 10 and 11) VTHR + 75 VCC − 1000* VCC VTHR + 75 VCC − 1000* VCC VTHR + 75 VCC − 1000* VCC mV VIL Input LOW Voltage (Single−Ended) (Notes 10 and 12) VIH − 2500 VCC − 1400* VTHR − 75 VIH − 2500 VCC − 1400* VTHR − 75 VIH − 2500 VCC − 1400* VTHR − 75 mV VBB PECL Output Voltage Reference 1080 1140 1200 1080 1140 1200 1080 1140 1200 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 9) (Differential Configuration) 2.5 1.2 2.5 1.2 2.5 V VMM CMOS Output Voltage Reference (VCC − VEE)/2 1.2 mV 1100 1250 1400 1100 1250 1400 1100 1250 1400 45 50 55 45 50 55 45 50 55 RTIN Internal Input Termination Resistor IIH Input HIGH Current (@ VIH) 30 100 30 100 30 100 A IIL Input LOW Current (@ VIL) 25 50 25 50 25 50 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *Typicals used for testing purposes. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V. 8. All loading with 50 to VCC − 2.0 V. VOH/VOL measured at VIH/VIL. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR − 75 mV. 11. VIH cannot exceed VCC. 12. VIL always w VEE. http://onsemi.com 5 NBSG16VS Table 6. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 18) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 20 27 34 20 27 34 20 27 34 mA VOH Output HIGH Voltage (Note 13) 2095 2220 2345 2085 2210 2335 2075 2200 2325 mV VOL Output LOW Voltage (Note 13) (Max Swing) (VCTRL = VCC − 600 mV) 1275 1750 1395 1870 1515 1990 1285 1730 1405 1850 1525 1970 1295 1715 1415 1835 1535 1955 VIH Input HIGH Voltage (Single−Ended) (Notes 15 and 16) VTHR + 75 VCC − 1000* VCC VTHR + 75 VCC − 1000* VCC VTHR + 75 VCC − 1000* VCC mV VIL Input LOW Voltage (Single−Ended) (Notes 15 and 17) VIH − 2500 VCC − 1400* VTHR − 75 VIH − 2500 VCC − 1400* VTHR − 75 VIH − 2500 VCC − 1400* VTHR − 75 mV VBB PECL Output Voltage Reference 1880 1940 2000 1880 1940 2000 1880 1940 2000 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 14) (Differential Configuration) 3.3 1.2 3.3 1.2 3.3 V VMM CMOS Output Voltage Reference (VCC − VEE)/2 mV 1.2 mV 1500 1650 1800 1500 1650 1800 1500 1650 1800 45 50 55 45 50 55 45 50 55 RTIN Internal Input Termination Resistor IIH Input HIGH Current (@ VIH) 30 100 30 100 30 100 A IIL Input LOW Current (@ VIL) 25 50 25 50 25 50 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *Typicals used for testing purposes. 13. All loading with 50 to VCC − 2.0 V. VOH/VOL measured at VIH/VIL. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 15. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR − 75 mV. 16. VIH cannot exceed VCC. 17. VIL always w VEE. 18. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V. http://onsemi.com 6 NBSG16VS Table 7. DC CHARACTERISTICS, NECL INPUT WITH VARIABLE NECL OUTPUT VCC = 0 V; VEE = −3.465 V to −2.375 V (Note 19) −40°C Symbol Characteristic IEE Negative Power Supply Current VOH Output HIGH Voltage (Note 20) −3.465 V v VEE v −3.0 V −3.0 V t VEE v −2.375 V VOL Output LOW Voltage (Note 20) −3.465 V v VEE v −3.0 V (Max Swing) (VCTRL = VCC − 600 mV) −3.0 V t VEE v −2.375 V (Max Swing) (VCTRL = VCC − 600 mV) 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 20 27 34 20 27 34 20 27 34 mA −1205 −1185 −1080 −1060 −955 −935 −1215 −1195 −1090 −1070 −965 −945 −1225 −1195 −1100 −1070 −975 −945 −2000 −1560 −1910 −1440 −1820 −1320 −1990 −1580 −1900 −1460 −1810 −1340 −1980 −1595 −1890 −1475 −1800 −1355 −1855 −1410 −1620 −1215 −1290 −1000 −1895 −1460 −1705 −1290 −1425 −1100 −1900 −1490 −1730 −1330 −1470 −1150 mV mV mV VIH Input HIGH Voltage (Single−Ended) (Notes 22 and 23) VTHR + 75 VCC − 1000* VCC VTHR + 75 VCC − 1000* VCC VTHR + 75 VCC − 1000* VCC mV VIL Input LOW Voltage (Single−Ended) (Notes 22 and 24) VIH − 2500 VCC − 1400* VTHR − 75 VIH − 2500 VCC − 1400* VTHR − 75 VIH − 2500 VCC − 1400* VTHR − 75 mV VBB NECL Output Voltage Reference −1420 −1360 −1300 −1420 −1360 −1300 −1420 −1360 −1300 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 21) (Differential Configuration) 0.0 V VMM CMOS Output Voltage Reference (Note 25) VMMT − 150 VMMT VMMT + 150 VMMT − 150 VMMT VMMT + 150 VMMT − 150 VMMT VMMT + 150 mV RTIN Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55 IIH Input HIGH Current (@ VIH) 30 100 30 100 30 100 A IIL Input LOW Current (@ VIL) 25 50 25 50 25 50 A VEE+1.2 0.0 VEE+1.2 0.0 VEE+1.2 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *Typicals used for testing purposes. 19. Input and output parameters vary 1:1 with VCC. 20. All loading with 50 to VCC − 2.0 V. VOH/VOL measured at VIH/VIL. 21. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 22. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR − 75 mV. 23. VIH cannot exceed VCC. 24. VIL always w VEE. 25. VMM typical = |VCC−VEE| / 2 + VEE = VMMT. http://onsemi.com 7 NBSG16VS Table 8. AC CHARACTERISTICS for FCBGA−16 VCC = 0 V; VEE = −3.465 V to −3.0 V or VCC = 3.0 V to 3.465 V; VEE = 0 V −40°C Symbol Characteristic fmax Maximum Frequency (See Figure 8) (Note 26) tPLH, tPHL Propagation Delay to Output Differential (VCTRL = VCC − 2 V) D → Q, Q (VCTRL = VCC − 1 V) D → Q, Q tSKEW Duty Cycle Skew (Note 27) tJITTER RMS Random Clock Jitter Min Typ 10.7 (Note 29) 12 Input Voltage Swing/Sensitivity (Differential Configuration) (Note 28) tr tf Output Rise/Fall Times (20% − 80%) @ 1 GHz (VCTRL = VCC − 2 V) Q, Q (VCTRL = VCC − 1 V) Q, Q Max Min Typ 10.7 (Note 29) 12 85°C Max Min Typ 10.7 (Note 29) 12 Max Unit GHz ps 100 100 125 120 145 140 3 0.8 100 100 125 120 145 140 10 3 2 0.8 100 100 125 120 145 140 10 3 10 2 0.8 2 ps ps fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s VINPP 25°C TBD 75 TBD 2600 75 TBD 2600 75 2600 mV ps 30 30 45 40 55 50 30 30 45 40 55 50 30 30 45 40 55 50 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 26. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 to VCC−2.0 V. Input edge rates 40 ps (20% − 80%). 27. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 10. 28. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE t 2600 mV). 29. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P Spec in Figure 8). Table 9. AC CHARACTERISTICS for FCBGA−16 VCC = 0 V; −3.0 V tVEE v −2.375 V or 2.375 V v VCC t 3.0 V; VEE = 0 V −40°C Symbol Characteristic fmax Maximum Frequency (See Figure 9) (Note 30) tPLH, tPHL Propagation Delay to Output Differential (VCTRL = VCC − 2 V) D → Q, Q (VCTRL = VCC − 1 V) D → Q, Q tSKEW Duty Cycle Skew (Note 31) tJITTER RMS Random Clock Jitter Typ 10.7 (Note 33) 12 Input Voltage Swing/Sensitivity (Differential Configuration) (Note 32) tr tf Output Rise/Fall Times (20% − 80%) @ 1 GHz (VCTRL = VCC − 2 V) Q, Q (VCTRL = VCC − 1 V) Q, Q Max Min Typ 10.7 (Note 33) 12 85°C Max Min Typ 10.7 (Note 33) 12 Max Unit GHz ps 100 100 125 120 145 140 3 0.9 100 100 125 120 145 140 10 3 3 0.9 100 100 125 120 145 140 10 3 10 3 0.9 3 ps ps fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s VINPP 25°C Min TBD 75 TBD 2600 75 TBD 2600 75 2600 mV ps 25 22 50 45 70 60 25 22 50 45 70 60 25 22 50 45 70 60 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 30. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 to VCC−2.0 V. Input edge rates 40 ps (20% − 80%). 31. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 10. 32. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE t 2600 mV). 33. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P Spec in Figure 9). http://onsemi.com 8 NBSG16VS Table 10. AC CHARACTERISTICS for QFN−16 VCC = 0 V; VEE = −3.465 V to −3.0 V or VCC = 3.0 V to 3.465 V; VEE = 0 V −40°C Symbol Characteristic fmax Maximum Frequency (See Figure 8) (Note 34) tPLH, tPHL Propagation Delay to Output Differential (VCTRL = VCC − 2 V) D → Q, Q (VCTRL = VCC − 1 V) D → Q, Q tSKEW Duty Cycle Skew (Note 35) tJITTER RMS Random Clock Jitter Min Typ 10 (Note 37) 12 Input Voltage Swing/Sensitivity (Differential Configuration) (Note 36) tr tf Output Rise/Fall Times (20% − 80%) @ 1 GHz (VCTRL = VCC − 2 V) Q, Q (VCTRL = VCC − 1 V) Q, Q Max Min Typ 10 (Note 37) 12 85°C Max Min Typ 10 (Note 37) 12 Max Unit GHz ps 100 100 140 135 180 180 3 0.5 100 100 140 135 180 180 20 3 2 0.5 100 80 140 135 180 220 15 3 10 2 0.5 2 ps ps fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s VINPP 25°C TBD 75 TBD 2600 75 TBD 2600 75 2600 mV ps 30 30 45 40 55 50 30 30 45 40 55 50 30 30 45 40 55 50 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 34. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 to VCC−2.0 V. Input edge rates 40 ps (20% − 80%). 35. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 10. 36. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE t 2600 mV). 37. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P Spec in Figure 8). Table 11. AC CHARACTERISTICS for QFN−16 VCC = 0 V; −3.0 V tVEE v −2.375 V or 2.375 V v VCC t 3.0 V; VEE = 0 V −40°C Symbol Characteristic fmax Maximum Frequency (See Figure 9) (Note 38) tPLH, tPHL Propagation Delay to Output Differential (VCTRL = VCC − 2 V) D → Q, Q (VCTRL = VCC − 1 V) D → Q, Q tSKEW Duty Cycle Skew (Note 39) tJITTER RMS Random Clock Jitter Typ 10 (Note 41) 12 Input Voltage Swing/Sensitivity (Differential Configuration) (Note 40) tr tf Output Rise/Fall Times (20% − 80%) @ 1 GHz (VCTRL = VCC − 2 V) Q, Q (VCTRL = VCC − 1 V) Q, Q Max Min Typ 10 (Note 41) 12 85°C Max Min Typ 10 (Note 41) 12 Max Unit GHz ps 100 100 140 135 180 180 3 0.5 100 100 140 135 180 180 20 3 3 0.5 80 100 140 135 180 220 15 3 10 3 0.5 3 ps ps fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s VINPP 25°C Min TBD 75 TBD 2600 75 TBD 2600 75 2600 mV ps 25 22 50 45 70 60 25 22 50 45 70 60 25 22 50 45 70 60 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 38. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 to VCC−2.0 V. Input edge rates 40 ps (20% − 80%). 39. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 10. 40. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE t 2600 mV). 41. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P Spec in Figure 9). http://onsemi.com 9 NBSG16VS 100 OUTPUT AMPLITUDE (%) 90 80 70 60 50 40 30 20 10 0 VCC − 0.0 VCC − 0.5 VCC − 1.0 VCC − 1.5 VCC − 2.0 VCTRL (V) Figure 5. Output Amplitude % vs. VCTRL (pin #A3) VOH AMPLITUDE DECREASES OUTPUT AMPLITUDE MIN. AMPLITUDE REGION MAX. AMPLITUDE REGION VOL 2.375 V v VCC − VEE < 3.0 V 3.0 V v VCC − VEE v 3.465 V VCC − 1.3 VCC − 0.0 VCC − 0.5 VCC − 1.0 VCC − 1.5 VCC − 2.0 VCTRL (V) Figure 6. Output Amplitude vs. VCTRL (pin #A3) 3.40 3.20 VOLTAGE (V) 3.00 VCTRL 2.80 2.60 2.40 2.20 2.00 Q/Q 1.80 1.60 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) Figure 7. Output Response Under Amplitude Modulation of VCTRL (Conditions Include VCC − VEE = 3.3 V at 255C, fIN (VCTRL) = 200 MHz, and fIN (D, D) = 2 GHz) http://onsemi.com 10 NBSG16VS 9 800 8 VCTRL = VCC − 2 V 700 7 600 JITTEROUT ps (RMS) OUTPUT VOLTAGE AMPLITUDE (mV) 900 6 VCTRL = VCC − 1 V 500 5 VCTRL = VCC − 0 V 400 4 OUTPUT P−P SPEC (AMPLITUDE GUARANTEE) 300 3 200 2 100 1 RMS JITTER 0 1 2 3 4 5 6 7 8 9 10 11 12 0 INPUT FREQUENCY (GHz) Figure 8. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical) 9 8 VCTRL = VCC − 2 V 700 7 600 VCTRL = VCC − 1 V 6 500 5 400 300 VCTRL = VCC − 0 V OUTPUT P−P SPEC (AMPLITUDE GUARANTEE) 3 200 2 100 1 RMS JITTER 0 4 JITTEROUT ps (RMS) OUTPUT VOLTAGE AMPLITUDE (mV) 800 1 2 3 4 5 6 7 8 9 10 11 12 0 INPUT FREQUENCY (GHz) Figure 9. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical) D VINPP = VIH(D) − VIL(D) D Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 10. AC Reference Measurement http://onsemi.com 11 NBSG16VS Q Zo = 50 D Receiver Device Driver Device Q Zo = 50 D 50 50 VTT VTT = VCC − 2.0 V Figure 11. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† NBSG16VSBA FCBGA−16 100 Units / Tray (Contact Sales Representative) NBSG16VSBAR2 FCBGA−16 100 / Tape & Reel QFN−16 123 Units / Rail NBSG16VSMNG QFN−16 (Pb−Free) 123 Units / Rail NBSG16VSMNR2 QFN−16 3000 / Tape & Reel QFN−16 (Pb−Free) 3000 / Tape & Reel Device NBSG16VSMN NBSG16VSMNR2G Board Description NBSG16VSBAEVB NBSG16VSBA Evaluation Board †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 12 NBSG16VS PACKAGE DIMENSIONS FCBGA−16 BA SUFFIX PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE CASE 489−01 ISSUE O LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA −X− D M −Y− K E M 0.20 3X e 4 3 2 FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA 1 A 3 B b 16 X C D S VIEW M−M 0.15 M Z X Y 0.08 M Z 5 0.15 Z A A2 A1 16 X 4 −Z− 0.10 Z DETAIL K ROTATED 90 _ CLOCKWISE http://onsemi.com 13 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. DIM A A1 A2 b D E e S MILLIMETERS MIN MAX 1.40 MAX 0.25 0.35 1.20 REF 0.30 0.50 4.00 BSC 4.00 BSC 1.00 BSC 0.50 BSC NBSG16VS PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE C D PIN 1 LOCATION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG A B ÇÇ ÇÇ E DIM A A1 A3 b D D2 E E2 e K L 0.15 C TOP VIEW 0.15 C (A3) 0.10 C A 16 X 0.08 C SIDE VIEW SEATING PLANE A1 SOLDERING FOOTPRINT* C D2 16X 0.575 0.022 e L 5 NOTE 5 K 12 1 16 16X 1.50 0.059 3.25 0.128 e 13 b 0.10 C A B 0.05 C EXPOSED PAD 9 E2 16X 3.25 0.128 0.30 0.012 EXPOSED PAD 8 4 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.50 0.02 BOTTOM VIEW NOTE 3 0.30 0.012 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and solderin details, please download the ON Semiconductor Soldering an Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 14 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NBSG16VS/D