MC14557B 1−to−64 Bit Variable Length Shift Register The MC14557B is a static clocked serial shift register whose length may be programmed to be any number of bits between 1 and 64. The number of bits selected is equal to the sum of the subscripts of the enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus one. Serial data may be selected from the A or B data inputs with the A/B select input. This feature is useful for recirculation purposes. A Clock Enable (CE) input is provided to allow gating of the clock or negative edge clocking capability. The device can be effectively used for variable digital delay lines or simply to implement odd length shift registers. • 1−64 Bit Programmable Length • Q and Q Serial Buffered Outputs • Asynchronous Master Reset • All Inputs Buffered • No Limit On Clock Rise and Fall Times • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low−power TTL Loads or one Low−power Schottky TTL Load Over the Rated Temperature Range • Pb−Free Packages are Available http://onsemi.com MARKING DIAGRAMS 16 MC14557BCP AWLYYWW 16 1 1 PDIP−16 P SUFFIX CASE 648 16 14557 MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter Symbol Value Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V VDD DC Supply Voltage Range Vin, Vout Input or Output Voltage Range (DC or Transient) Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 2) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. 2. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/°C From 65°C To 125°C *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2004 June, 2004 − Rev. 5 1 1 SO−16 WB DW SUFFIX CASE 751G AWLYYWW 1 16 MC14557B ALYW SOEIAJ−16 F SUFFIX CASE 966 A WL, L YY, Y WW, W 1 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Publication Order Number: MC14557B/D CE CLOCK RESET A 4 3 7 C R 32 BIT C R 16 BIT C 8 BIT R C 4 BIT R 6 A/B 9 SELECT 12 13 14 15 L32 L16 L8 L4 C 2 BIT R C 1 BIT R C 1 BIT R 10 11 1 2 L2 L1 Q Q VDD = PIN 16 VSS = PIN 8 MC14557B Figure 1. Logic Diagram 2 http://onsemi.com B 5 MC14557B L2 1 16 VDD L1 2 15 L4 RESET 3 14 L8 CLOCK 4 13 L16 CE 5 12 L32 B 6 11 Q A 7 10 Q VSS 8 9 3 4 5 6 7 9 2 1 15 14 13 12 A/B SEL RESET CLOCK CE B A A/B SELECT L1 L2 L4 L8 L16 L32 Q 10 Q 11 VDD = PIN 16 VSS = PIN 8 Figure 2. Pin Assignment Figure 3. Block Diagram TRUTH TABLE LENGTH SELECT TRUTH TABLE Inputs Clock Output L32 L16 L8 L4 L2 L1 Register Length CE Q 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 Bit 2 Bits 3 Bits 4 Bits 5 Bits 6 Bits 33 Bits 34 Bits 61 Bits 62 Bits 63 Bits 64 Bits Rst A/B 0 0 0 B 0 1 0 A 0 0 1 0 1 1 1 X X B A X 0 Q is the output of the first selected shift register stage. X = Don’t Care NOTE: http://onsemi.com 3 Length equals the sum of the binary length control subscripts plus one. MC14557B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) − 55°C Symbol VOL VOH VDD Vdc Min Max Min “0” Level 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − Source 5.0 5.0 10 15 –3.0 –0.64 –1.6 –4.2 − − − − –2.4 –0.51 –1.3 –3.4 –4.2 –0.88 –2.25 –8.8 − − − − –1.7 –0.36 –0.9 –2.4 − − − − Sink 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − Vin = 0 or VDD VIL Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIH Max Min Max Unit “0” Level Vdc “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) IOH 125°C Typ (Note 3) Characteristic Output Voltage Vin = VDD or 0 25°C Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Vdc mAdc IOL (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Iin Input Current 15 − ± 0.1 − ± 0.00001 ± 0.1 − ± 1.0 Adc Cin Input Capacitance (Vin = 0) − − − − 5.0 7.5 − − pF IDD Quiescent Current (Per Package) 5.0 10 15 − − − 5.0 10 20 − − − 0.010 0.020 0.030 5.0 10 20 − − − 150 300 600 Adc IT Total Supply Current (Notes 4, 5) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) 5.0 10 15 IT = (1.75 A/kHz) f + IDD IT = (3.50 A/kHz) f + IDD IT = (5.25 A/kHz) f + IDD Adc 3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 4. The formulas given are for the typical characteristics only at 25°C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001. http://onsemi.com 4 MC14557B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 6) (CL = 50 pF, TA = 25°C) Characteristic Symbol VDD Min Typ (Note 7) Max Unit tTLH, tTHL Rise and Fall Time, Q or Q Output tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 5 10 15 − − − 100 50 40 200 100 80 ns tPLH, tPHL Propagation Delay, Clock or CE to Q or Q tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 65 ns 5 10 15 − − − 300 130 90 600 260 180 tPLH, tPHL Propagation Delay, Reset to Q or Q tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 70 ns 5 10 15 − − − 300 130 95 600 260 190 tWH(cl) Pulse Width, Clock 5 10 15 200 100 75 95 45 35 − − − ns tWH(rst) Pulse Width, Reset 5 10 15 300 140 100 150 70 50 − − − ns fcl Clock Frequency (50% Duty Cycle) 5 10 15 − − − 3.0 7.5 13.0 1.7 5.0 6.7 MHz tsu Setup Time, A or B to Clock or CE Worst case condition: L1 = L2 = L4 = L8 = L16 = L32 = VSS (Register Length = 1) 5 10 15 700 290 145 350 130 85 − − − 5 10 15 400 165 60 45 5 0 − − − 5 10 15 200 100 10 –150 –60 –50 − − − 5 10 15 400 185 85 50 25 22 − − − ns ns ns Best case condition: L32 = VDD, L1 through L16 = Don’t Care (Any register length from 33 to 64) th ns Hold Time, Clock or CE to A or B Best case condition: L1 = L2 = L4 = L8 = L16 = L32 = VSS (Register Length = 1) Worst case condition: L32 = VDD, L1 through L16 = Don’t Care (Any register length from 33 to 64) tr, tf Rise and Fall Time, Clock 5 10 15 − tr, tf Rise and Fall Time, Reset or CE 5 10 15 − − − − − − 15 5 4 s trem Removal Time, Reset to Clock or CE 5 10 15 160 80 70 80 40 35 − − − ns No Limit 6. The formulas given are for the typical characteristics only at 25°C. 7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 5 MC14557B 50% CLOCK VDD tWH(cl) VSS 1/fcl VDD 50% A INPUT th RESET 1−bit length: CE = 0 Q A/B = 1 L1 = L2 = L4 = L8 = L16 = L32 = 0 VSS trem tsu tTLH tPLH VDD 50% tTHL 90% 50% 10% tPHL VSS PWR VOH tPHL VOL Figure 4. Timing Diagram ORDERING INFORMATION Package Shipping† SOEIAJ−16 (Pb−Free) 50 Units / Rail MC14557BCP PDIP−16 500 Units / Rail MC14557BFEL SOEIAJ−16 (Pb−Free) 2000 / Tape & Reel MC14557BDWR2 SO−16 (WB) 1000 / Tape & Reel MC14557BCPG PDIP−16 (Pb−Free) 500 Units / Rail MC14557BDW SO−16 (WB) 47 Units / Rail Device MC14557BF †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 MC14557B PACKAGE DIMENSIONS PDIP−16 P SUFFIX CASE 648−08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. −A− 16 9 1 8 B F C L S −T− SEATING PLANE K H G D M J 16 PL 0.25 (0.010) T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 SO−16 WB DW SUFFIX CASE 751G−03 ISSUE C A D 9 1 h X 45 MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0 7 8 16X M 14X e T A S B S L A 0.25 B B A1 H E 0.25 8X M B M 16 SEATING PLANE T NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C http://onsemi.com 7 MC14557B PACKAGE DIMENSIONS SOEIAJ−16 F SUFFIX CASE 966−01 ISSUE O 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 9 Q1 M E HE 1 8 L DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 −−− 0.78 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 −−− 0.031 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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