IDT IDT74FCT388915T100PYB 3.3v low skew pll-based cmos clock driver with (3-state) Datasheet

IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
Integrated Device Technology, Inc.
IDT54/74FCT388915T
70/100/133/150
PRELIMINARY
FEATURES:
is fed back to the PLL at the FEEDBACK input resulting in
essentially zero delay across the device. The PLL consists of
• 0.5 MICRON CMOS Technology
the phase/frequency detector, charge pump, loop filter and
• Input frequency range: 10MHz – f2Q Max. spec
VCO. The VCO is designed for a 2Q operating frequency
(FREQ_SEL = HIGH)
range of 40MHz to f2Q Max.
• Max. output frequency: 150MHz
The IDT54/74FCT388915T provides 8 outputs with 350ps
• Pin and function compatible with FCT88915T, MC88915T
skew.
The Q5 output is inverted from the Q outputs. The 2Q
• 5 non-inverting outputs, one inverting output, one 2x
runs
at
twice the Q frequency and Q/2 runs at half the Q
output, one ÷2 output; all outputs are TTL-compatible
frequency.
• 3-State outputs
The FREQ_SEL control provides an additional ÷ 2 option in
• Output skew < 350ps (max.)
the output path. PLL _EN allows bypassing of the PLL, which
• Duty cycle distortion < 500ps (max.)
is useful in static test modes. When PLL_EN is low, SYNC
• Part-to-part skew: 1ns (from tPD max. spec)
input may be used as a test clock. In this test mode, the input
• 32/–16mA drive at CMOS output voltage levels
frequency is not limited to the specified range and the polarity
• VCC = 3.3V ± 0.3V
of outputs is complementary to that in normal operation
• Inputs can be driven by 3.3V or 5V components
(PLL_EN = 1). The LOCK output attains logic HIGH when the
• Available in 28 pin PLCC, LCC and SSOP packages
PLL is in steady-state phase and frequency lock. When OE/
DESCRIPTION:
RST is low, all the outputs are put in high impedance state and
The IDT54/74FCT388915T uses phase-lock loop technol- registers at Q, Q and Q/2 outputs are reset.
ogy to lock the frequency and phase of outputs to the input
The IDT54/74FCT388915T requires one external loop filter
reference clock. It provides low skew clock distribution for component as recommended in Figure 3.
high performance PCs and workstations. One of the outputs
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
SYNC (0)
SYNC (1)
LOCK
0M
u
1x
Phase/Freq.
Detector
Voltage
Controlled
Oscilator
Charge Pump
LF
REF_SEL
PLL_EN
0
1
Mux
Divide
-By-2
2Q
(÷ 1)
1M
u
x
0
(÷ 2)
D
Q
D
FREQ_SEL
Q0
CP R Q
Q
Q1
Q
Q2
Q
Q3
Q
Q4
Q
Q5
Q
Q/2
CP R
OE/RST
D
CP R
D
CP
R
D
CP
R
D
CP
R
D
CP
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
3052 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1995 Integrated Device Technology, Inc.
R
9.8
9.8
AUGUST 1995
DSC-4243/1
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
VCC
Q5
GND
Q4
VCC
2Q
4
3
2
1
28
27
26
GND
1
28
Q4
Q5
2
27
VCC
VCC
3
26
2Q
OE/RST
4
25
Q/2
FEEDBACK
5
24
GND
REF_SEL
6
23
Q3
SYNC(0)
7
22
VCC
VCC(AN)
8
21
Q2
LF
9
20
GND
GND(AN)
10
19
LOCK
SYNC(1)
11
18
PLL_EN
FREQ_SEL
12
17
GND
18
GND
PLL_EN
OE/RST
PIN CONFIGURATIONS
Q0
13
14
16
15
Q1
VCC
FEEDBK
5
25
REF_SEL
6
24
GND
SYNC(0)
7
23
Q3
VCC(AN)
8
22
VCC
LF
9
21
Q2
10
20
GND
11
15
16
17
GND
14
Q1
13
Q0
12
VCC
19
GND
SYNC(1)
FREQ_SEL
GND(AN)
J28-1,
L28-1
Q/2
LOCK
SO28-7
SSOP
TOP VIEW
3052 drw 02
3052 drw 03
PLCC/LCC
TOP VIEW
PIN DESCRIPTION
Pin Name
I/O
Description
SYNC(0)
I
Reference clock input.
SYNC(1)
I
Reference clock input.
REF_SEL
I
Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram).
FREQ_SEL
I
Selects between ÷ 1 and ÷ 2 frequency options. (Refer to functional block diagram).
FEEDBACK
I
Feedback input to phase detector.
LF
I
Input for external loop filter connection.
Q0-Q4
O
Clock output.
Q5
O
Inverted clock output.
2Q
O
Clock output (2 x Q frequency).
Q/2
O
Clock output (Q frequency ÷ 2).
LOCK
O
Indicates phase lock has been achieved (HIGH when locked).
OE/RST
I
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are
enabled. When LOW, outputs are in HIGH impedance.
PLL_EN
I
Disables phase-lock for low frequency testing. (Refer to functional block diagram).
3052 tbl 01
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
VTERM(4) Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
TSTG
Storage
Temperature
IOUT
DC Output
Current
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Commercial
Military
–0.5 to +4.6 –0.5 to +4.6
–0.5 to +7.0
–0.5 to +7.0
Symbol
Parameter(1)
CIN
Input
Capacitance
COUT
Output
Capacitance
Unit
V
V
Conditions
VIN = 0V
Typ.
4.5
VOUT = 0V
5.5
Max. Unit
6.0
pF
8.0
NOTE:
1. This parameter is measured at characterization but not tested.
–0.5 to VCC
+0.5
–0.5 to VCC
+0.5
V
0 to +70
–55 to +125
°C
–55 to +125
–65 to +135
°C
–55 to +125
–65 to +150
°C
–60 to +60
–60 to +60
mA
pF
3052 lnk 03
3052 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to 70°C, VCC = 3.3V ±0.3V
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2.0
Typ.(2)
—
Max.
5.5
Unit
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
–0.5
—
0.8
V
II H
Input HIGH Current
VCC = Max.
VI = 5.5V
—
—
±1
µA
II L
Input LOW Current
VI = GND
—
—
±1
µA
I OZH
High Impedance Output Current
I OZL
(3-State Output Pins)
VIK
Clamp Diode Voltage
Symbol
VIH
VCC = Max.
VO = VCC
—
—
±1
µA
VO = GND
—
—
±1
µA
—
–0.7
–1.2
V
VCC = Min., IIN = –18mA
1.5V(3)
IODH
Output Drive Current
VCC = Max., VIN = VIH or VIL, VO =
IODL
Output Drive Current
VCC = Max., VIN = VIH or VIL, VO = 1.5V(3)
VOH
Output HIGH Voltage
VCC = Min.
VOL
Output LOW Voltage
VCC = Min.
VH
Input Hysteresis
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
IOH = –16mA
IOL = 32mA
—
VCC = Max., VIN = GND or VCC
(Test mode)
–36
—
—
mA
50
—
—
mA
2.4 (5)
3.0
—
V
—
0.3
0.5
V
—
100
—
mV
—
2.0
4.0
mA
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC - 0.6V at rated current.
9.8
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆ICC
Test Conditions(1)
Parameter
Quiescent Power Supply Current
VCC = Max.
VIN =
Min.
Typ.(2)
Max.
Unit
—
2.0
30
µA
—
0.2
0.3
mA/
MHz
VCC –0.6V(3)
VCC –2.1V(3)
TTL Inputs HIGH
VIN =
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
All Outputs Open
CPD
Power Dissipation Capacitance
50% Duty Cycle
—
15
25
pF
IC
Total Power Supply Current (6)
VCC = Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
—
30
60
mA
—
90
120
mA
VIN = VCC
VIN = GND
SYNC frequency = 50MHz. All bits loaded with
15pF
VCC = Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. All bits loaded with
50Ω Thevenin termination and 20pF
3052 tbl 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input. All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (f) + ILOAD
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f =2Q Frequency
ILOAD = Dynamic Current due to load.
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
TRISE/FALL Rise/Fall Times,
SYNC inputs
(0.8V to 2.0V)
Frequency Input Frequency,
SYNC Inputs
Duty Cycle Input Duty Cycle,
SYNC Inputs
Min.
—
Max.
3.0
Unit
ns
10.0 (1)
2Q fmax
MHz
25%
75%
—
3052 tbl 06
OUTPUT FREQUENCY SPECIFICATIONS
Max.
Symbol
f2Q
Parameter
Operating frequency 2Q Output
(2)
Min.
40
70
70
100
100
133
133
150
150
Unit
MHz
fQ
Operating frequency Q0-Q4, Q5 Outputs
20
35
50
66.7
75
MHz
fQ/2
Operating frequency Q/2 Output
10
17.5
25
33.3
37.5
MHz
3052 tbl 07
NOTES:
1. Note 7 in "General AC Specification Notes" and Figure 3 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded.
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Condition(1)
Min.*
Max.*
Unit
0.2 (2)
1.5
ns
tRISE/FALL
All Outputs
Rise/Fall Time
(between 0.8V and 2.0V)
Load = 50Ω to
VCC/2, CL = 20pF
tPULSE WIDTH (3)
Q, Q, Q/2 outputs (3)
Output Pulse Width
Q0-Q4, Q5, Q/2, @ 1.5V
Load = 50Ω to
0.5tCYCLE – 0.5(5)
VCC/2, CL = 20pF
0.5tCYCLE + 0.5(5)
ns
tPULSE WIDTH
2Q Output (3)
Output Pulse Width
2Q @ 1.5V
0.5tCYCLE – 0.7(5)
0.5tCYCLE + 0.7(5)
ns
Load = 50Ω to
VCC/2, CL = 20pF
0.1µF from LF to
Analog GND (5)
–0.5
+0.5
ns
Load = 50Ω to
VCC/2, CL = 20pF
—
250
ps
SYNC input to FEEDBACK delay
tPD
(3)
SYNC-FEEDBACK
(measured at SYNC0 or 1 and FEEDBACK
input pins)
tSKEWr
(rising)(3,4)
Output to Output Skew
between outputs 2Q, Q0-Q4,
Q/2 (rising edges only)
tSKEWf
(falling)(3,4)
Output to Output Skew
between outputs Q0-Q4 (falling edges only)
—
250
ps
Output to Output Skew
2Q, Q/2, Q0-Q4 rising, Q5 falling
—
350
ps
tLOCK (6)
Time required to acquire
Phase-Lock from time
SYNC input signal is received
1(2)
10
ms
tPZH
tPZL
Output Enable Time
OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q
3(2)
14
ns
tPHZ
tPLZ
Output Disable Time
OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q
3(2)
14
ns
tSKEWall
(3,4)
3052 tbl 08
GENERAL AC SPECIFICATION NOTES:
* PRELIMINARY.
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.
5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF. (Where
C1 is loop filter capacitor shown in Figure 2).
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOTES:
7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback
configurations. The allowable SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges,
depending on whether FREQ_SEL is HIGH or LOW. Also it is possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC
input and the Q outputs. The table below summarizes the allowable SYNC frequency range for each possible configuration.
FREQ_SEL
Level
Feedback
Output
Allowable SYNC Input
Frequency Range (MHZ)
Corresponding 2Q Output
Frequency Range
Phase Relationship
of the Q Outputs
to Rising SYNC Edge
HIGH
Q/2
10 to (2x _Q fMAX Spec)/4
40 to (2Q fMAX Spec)
0°
HIGH
Any Q (Q0-Q4)
20 to (2x_Q fMAX Spec)/2
40 to (2Q fMAX Spec)
0°
HIGH
Q5
20 to (2x_Q fMAX Spec)/2
40 to (2Q fMAX Spec)
180°
HIGH
2X_Q
LOW
Q/2
LOW
40 to (2x_Q fMAX Spec)
40 to (2Q fMAX Spec)
0°
5 to (2x_Q fMAX Spec)/8
20 to (2Q fMAX Spec)/2
0°
Any Q (Q0-Q4)
10 to (2x_Q fMAX Spec)/4
20 to (2Q fMAX Spec)/2
0°
LOW
Q5
10 to (2x_Q fMAX Spec)/4
20 to (2Q fMAX Spec)/2
180°
LOW
2X_Q
20 to (2x_Q fMAX Spec)/2
20 to (2Q fMAX Spec)/2
0°
3052 tbl 09
8. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input, varies with process, temperature
and voltage. Measurements were made with a 10MHz SYNC input and Q/2 output as feedback. The phase measurements were made at 1.5V. The Q/
2 output was terminated at the FEEDBACK input with 100Ω to VCC and 100Ω to ground. tPD measurements were made with the loop filter connection
shown below:
External Loop
Filter
0.1µF
LF
C1
Analog GND
3052 drw 04
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BOARD VCC
ANALOG VCC
10µF
Low
Freq.
Bypass
0.1µF
High
Freq.
Bypass
LF
Analog loop filter
section of the
FCT388915T
0.1µF (Loop
Filter Cap)
ANALOG GND
BOARD GND
A separate Analog power supply
is not necessary and should not
be used. Following these
prescribed guidelines is all that is
necessary to use the FCT388915
in a normal digital environment.
3052 drw 12
Figure 2. Recommended Loop Filter and Analog Isolation Scheme for the FCT388915T
NOTES:
1. Figure 2 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure
stable and jitter-free operation:
a.
All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of
long traces can cause undesirable voltage transients at the LF pin.
b.
The 10µF low frequency bypass capacitor and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the
388915T's sensitivity to voltage transients from the system digital VCC supply and ground planes.
If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should
not occur at the 388915T's digital VCC supply. The purpose of the bypass filtering scheme shown in figure 2 is to give the 388915T additional
protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system.
c.
The loop filter capacitor (0.1µF) can be a ceramic chip capacitor, the same as a standard bypass capacitor.
2. In addition to the bypass capacitors used in the analog filter of figure 2 there should be a 0.1µF bypass capacitor between each of the other (digital) four
VCC pins and the board ground plane. This will reduce output switching noise caused by the 388915T outputs, in addition to reducing potential for noise
in the "analog" section of the chip. These bypass capacitors should also be tied as close to the 388915T package as possible.
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The frequency relationship shown here is applicable to all Q
outputs (Q0, Q1, Q2, Q3 and Q4).
50 MHz signal
25 MHz feedback signal
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
HIGH
In this application, the Q/2 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q/2 and SYNC, thus the Q/2 frequency will equal the
SYNC frequency. The Q outputs (Q0-Q4, Q5) will always run
at 2X the Q/2 frequency, and the 2Q output will run at 4X the
Q/2 frequency.
OE/RST Q5
FEEDBACK
LOW
25 MHz
input
2Q
Q/2
SYNC(0)
25 MHz
"Q"
Clock
Outputs
Q3
FCT388915T
Q2
LF
12.5 MHz feedback signal
12.5 MHz
signal
REF_SEL
VCC(AN)
50 MHz signal
Q4
GND(AN)
FQ_SEL
HIGH
Q0
OE/RST Q5
FEEDBACK
LOW
12.5 MHz
input
Q4
Q1
PLL_EN
2Q
HIGH
HIGH
Q/2
REF_SEL
3052 drw 10
Q3
SYNC(0)
VCC(AN)
FCT388915T
25 MHz
"Q"
Clock
Outputs
Figure 3b. Wiring Diagram and Frequency Relationships With Q4
Q2
LF
Allowable Input Frequency Range:
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
Output Feedback
GND(AN)
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
FQ_SEL
Q0
HIGH
Q1
PLL_EN
In this application, the 2Q output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of 2Q and SYNC, thus the 2Q frequency will equal the
SYNC frequency. The Q/2 output will always run at 1/4 the
2Q frequency, and the Q output will run at 1/2 the 2Q
frequency.
HIGH
3052 drw 09
Allowable Input Frequency Range:
10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
50 MHz feedback signal
HIGH
Figure 3a. Wiring Diagram and Frequency Relationships With Q/2
Output Feedback
OE/RST Q5
FEEDBACK
LOW
50 MHz
input
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
In this application, the Q4 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q4 and SYNC, thus the Q4 frequency (and the rest
of the "Q" outputs) will equal the SYNC frequency. The Q/2
output will always run at 1/2 the Q frequency, and the 2Q
output will run at 2X the Q frequency.
Q4
2Q
Q/2
12.5 MHz
input
REF_SEL
SYNC(0)
VCC(AN)
Q3
FCT388915T
25 MHz
"Q"
Clock
Outputs
Q2
LF
GND(AN)
FQ_SEL
Q0
HIGH
Q1
PLL_EN
HIGH
3052 drw 11
Allowable Input Frequency Range:
40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
Figure 3c. Wiring Diagram and Frequency Relationships With 2Q
Output Feedback
9.8
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
CLOCK
@f
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CMMU
CMMU
CPU
CMMU
CMMU
CMMU
CMMU
CMMU
CPU
CMMU
CMMU
CMMU
FCT388915T
PLL
2f
SYSTEM
CLOCK
SOURCE
FCT388915T
PLL
2f
DISTRIBUTE
CLOCK @f
CPU
CARD
CPU
CARD
CLOCK @2f
at point of use
FCT388915T
PLL
2f
MEMORY
CONTROL
MEMORY
CARDS
CLOCK @2f
at point of use
3052 drw 13
Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication
and Low Board-to-Board skew
FCT388915T System Level Testing Functionality
When the PLL_EN pin is LOW, the PLL is bypassed and the
FCT388915T is in low frequency "test mode". In test mode
(with FREQ_SEL HIGH), the 2Q output is inverted from the
selected SYNC input, and the Q outputs are divide-by-2
(negative edge triggered) of the SYNC input, and the Q/2
output is divide-by-4 (negative edge triggered). With
FREQ_SEL LOW the 2Q output is divide-by-2 of the SYNC,
the Q outputs divide-by-4, and the Q/2 output divide-by-8.
These relationships can be seen in the block diagram. A
recommended test configuration would be to use SYNC0 or
SYNC1 as the test clock input, and tie PLL_EN and REF_SEL
together and connect them to the test select logic.
This functionality is needed since most board-level testers
run at 1 MHz or below, and theFCT 388915T cannot lock onto
that low of an input frequency. In the test mode described
above, any test frequency test can be used.
9.8
9
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
50Ω TO VCC/2, CL = 20PF
ENABLE AND DISABLE TEST CIRCUIT
VCC
VCC
6.0V
VCC
100Ω
500Ω
VOUT
VIN
Pulse
Generator
VOUT
VIN
D.U.T.
20pF
100Ω
RT
GND
Pulse
Generator
D.U.T.
CL
RT
500Ω
3052 drw 05
3052 drw 06
PROPAGATION DELAY, OUTPUT SKEW
1.5V
SYNC INPUT
(SYNC (1) or
SYNC (0))
t CYCLE SYNC INPUT
tPD
VCC/2
FEEDBACK
INPUT
VCC/2
Q/2 OUTPUT
t SKEWf
t SKEWALL
t SKEWr
t SKEWf
t SKEWr
VCC/2
Q0-Q4
OUTPUTS
tCYCLE "Q" OUTPUTS
1.5V
Q5 OUTPUT
VCC/2
2Q OUTPUT
3052 drw 08
(These waveforms represent the configuration of Figure 3a)
NOTES:
1. The FCT388915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as ± deviation
around a center point.
3. If a Q ouput is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q
output would run at twice the SYNC frequency and the Q/2 output would run at half the SYNC frequency.
ENABLE AND DISABLE TIMES
ENABLE
SWITCH POSITION
DISABLE
Test
Disable Low
Enable Low
Disable High
Enable High
3V
CONTROL
INPUT
tPZL
OUTPUT
NORMALLY
LOW
SWITCH
6V
tPLZ
SWITCH
GND
3V
3V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
1.5V
0V
0.3V
0.3V
GND
3052 tbl 10
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
VOL
tPHZ
1.5V
0V
Switch
6V
VOH
0V
3052 drw 07
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: tF ≤ 2.5ns; tR ≤ 2.5ns
9.8
10
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
XXXX
IDT
XX
FCT
Temp. Range
Device Type
X
Speed
X
Package
X
Process
9.8
Blank
B
Commercial
MIL-STD-883, Class B
J
L
PY
PLCC
LCC
SSOP
70
100
133
150
70MHz Max. Frequency
100MHz Max. Frequency
133MHz Max. Frequency
150MHz Max. Frequency
388915T
3.3V Low skew PLL-based CMOS clock driver
54
74
–55°C to +125°C
0°C to +70°C
3052 drw 14
11
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