AD AD9022 12-bit 20 msps monolithic a/d converter Datasheet

a
FEATURES
Monolithic
12-Bit 20 MSPS A/D Converter
Low Power Dissipation: 1.4 Watts
On-Chip T/H and Reference
High Spurious-Free Dynamic Range
TTL Logic
APPLICATIONS
Radar Receivers
Digital Communications
Digital Instrumentation
Electro-Optics
PRODUCT DESCRIPTION
The AD9022 is a high speed, high performance, monolithic
12-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference, are included
on-chip to provide a complete conversion solution. It is a
companion unit to the AD9023; the primary difference between
the two is that all logic for the AD9022 is TTL-compatible,
while the AD9023 utilizes ECL logic for digital inputs and outputs. Pinouts for the two parts are nearly identical.
Operating from +5 V and –5.2 V supplies, the AD9022 provides excellent dynamic performance. Sampling at 20 MSPS
with AIN = 1 MHz, the spurious-free dynamic range (SFDR) is
typically 76 dB; with AIN = 9.6 MHz, SFDR is 74 dB. SNR is
typically 65 dB.
The onboard T/H has a 110 MHz bandwidth and, more importantly, is designed to provide excellent dynamic performance for
analog input frequencies above Nyquist. This feature is necessary in many undersampling signal processing applications, such
as in direct IF-to-digital conversion.
12-Bit 20 MSPS
Monolithic A/D Converter
AD9022
FUNCTIONAL BLOCK DIAGRAM
ANALOG
INPUT
T/H
5-BIT
ADC
DIGITAL
12
ERROR
CORRECTION TTL
AD9022
5-BIT
ADC
DAC
ENCODE
+5V
T/H
+2V
REF
16
–5.2V
DAC
GND
8
4-BIT
ADC
With DNL typically less than 0.5 LSB and 20 ns transient response settling time, the AD9022 provides excellent results
when low-frequency analog inputs must be oversampled (such
as CCD digitization). The full scale analog input is ± 1 V with a
300 Ω input impedance. The analog input can be driven directly
from the signal source, or can be buffered by the AD96xx series
of low noise, low distortion buffer amplifiers.
All timing is internal to the AD9022; the clock signal initiates
the conversion cycle. For best results, the encode command
should contain as little jitter as possible. High speed layout
practices must be followed to ensure optimum A/D performance.
The AD9022 is built on a trench isolated bipolar process and
utilizes an innovative multipass architecture (see the block
diagram). The unit is packaged in 28-lead ceramic DIPs and
gullwing surface mount packages. The AD9022 is specified to
operate over the industrial (–25°C to +85°C) and military
(–55°C to +125°C) temperature ranges.
To maintain dynamic performance at higher IFs, monolithic
RF track-and-holds (such as the AD9100 and AD9101
Samplifier™) can be used with the AD9022 to process signals
up to and beyond 70 MHz.
Samplifier is a trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
AD9022–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(+VS = +5 V; –VS = –5.2 V; Encode = 20 MSPS, unless otherwise noted)
Parameter (Conditions)
Test
Level
Temp
RESOLUTION
DC ACCURACY
Differential Nonlinearity
AD9022AQ/AZ
Min Typ Max
AD9022BQ/BZ
Min Typ Max
AD9022SQ/SZ
Min Typ Max
Units
12
12
12
Bits
+25°C
Full
+25°C
Full
Full
+25°C
Full
+25°C
Full
+25°C
I
VI
I
VI
VI
I
VI
I
VI
V
ANALOG INPUT
Input Voltage Range
Input Resistance
Input Capacitance
Analog Bandwidth
Full
+25°C
+25°C
IV
V
V
240
SWITCHING PERFORMANCE 1
Minimum Conversion Rate
Maximum Conversion Rate
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Delay (tOD)
+25°C
Full
+25°C
+25°C
Full
IV
VI
IV
V
VI
4
20
0.55 0.71 0.85
6
15
27.5
ENCODE INPUT
Logic Compatibility
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Pulsewidth (High)
Pulsewidth (Low)
Full
Full
Full
Full
+25°C
+25°C
+25°C
VI
VI
VI
VI
V
IV
IV
2.0
+25°C
+25°C
V
V
+25°C
Full
+25°C
+25°C
Full
I
V
V
I
V
65
+25°C
Full
+25°C
+25°C
Full
I
V
V
I
V
62
+25°C
Full
+25°C
+25°C
Full
I
V
V
I
V
63
Integral Nonlinearity
No Missing Codes
Offset Error
Gain Error
Thermal Noise
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Harmonic Distortion
Analog Input @ 1.2 MHz
@ 1.2 MHz
@ 4.3 MHz
@ 9.6 MHz
@ 9.6 MHz
Signal-to-Noise Ratio 2
Analog Input @ 1.2 MHz
@ 1.2 MHz
@ 4.3 MHz
@ 9.6 MHz
@ 9.6 MHz
Signal-to-Noise Ratio 2
(Without Harmonics)
Analog Input @ 1.2 MHz
@ 1.2 MHz
@ 4.3 MHz
@ 9.6 MHz
@ 9.6 MHz
0.6
0.75
1.0
1.3 2.5
1.6 3.0
Guaranteed
5
25
15
35
0.5 2.5
0.6 3.5
0.57
± 1.024
300 360
5
110
0.4
0.5
1.0
1.3 2.0
1.6 3.0
Guaranteed
5
25
15
35
0.5 2.5
0.6 3.5
0.57
240
4
20
0.55 0.71 0.85
6
15
27.5
TTL
22.5
20
0.8
20
20
62
125
125
22.5
20
70
64
63
64
63
62
64
66
64
66
65
63
65
69
63
64
± 1.024
300 360
5
110
4
20
0.55 0.71 0.85
6
15
27.5
LSB
LSB
LSB
LSB
mV
mV
% FS
% FS
LSB, rms
V
Ω
pF
MHz
MSPS
MSPS
ns
ps, rms
ns
TTL
0.8
20
20
125
125
8
8
6
22.5
20
20
20
73
70
73
72
68
–2–
240
2.0
8
8
6
20
20
61
0.75
1.0
1.3 2.5
1.6 3.0
Guaranteed
5
25
15
35
0.5 2.5
0.6 3.5
0.57
TTL
2.0
8
8
6
63
± 1.024
300 360
5
110
0.6
75
72
75
74
72
65
66
65
66
65
63
62
67
66
66
66
65
63
63
61
62
0.8
20
20
125
125
V
V
µA
µA
pF
ns
ns
20
20
ns
ns
73
70
73
72
68
dBc
dBc
dBc
dBc
dBc
64
63
64
63
62
dB
dB
dB
dB
dB
66
64
66
65
63
dB
dB
dB
dB
dB
REV. B
AD9022
Parameter (Conditions)
Two-Tone Intermodulation
Distortion Rejection3
DIGITAL OUTPUTS1
Logic Compatibility
Logic “1” Voltage
Logic “0” Voltage
Output Coding
POWER SUPPLY
+VS Supply Voltage
+VS Supply Current
–VS Supply Voltage
–VS Supply Current
Power Dissipation
Power Supply
Rejection Ratio (PSRR) 4
Temp
Test
Level
AD9022AQ/AZ
Min Typ Max
+25°C
V
Full
Full
VI
VI
2.4
Full
Full
Full
Full
Full
VI
VI
VI
VI
VI
4.75 5.0
100
–5.45 –5.2
180
1.4
Full
V
AD9022BQ/BZ
Min Typ Max
74
AD9022SQ/SZ
Min Typ Max
74
TTL
74
TTL
2.4
0.5
Offset Binary
5.25 4.75 5.0
120
100
–4.95 –5.45 –5.2
220
180
1.9
1.4
32
dBc
TTL
2.4
0.5
Offset Binary
Units
0.5
Offset Binary
5.25
120
–4.95
220
1.9
4.75 5.0
100
–5.45 –5.2
180
1.4
32
5.25
120
–4.95
220
1.9
32
V
V
mA
mA
mA
mA
W
mV/V
NOTES
1
AD9022 load is a single LS latch.
2
RMS signal-to-rms noise with analog input signal 1 dB below full scale at specified frequency. Tested at 55% duty cycle.
3
Intermodulation measured with analog input frequencies of 8.9 MHz and 9.8 MHz at 7 dB below full scale.
4
PSRR is sensitivity of offset error to power supply variations within the 5% limits shown.
Specifications subject to change without notice.
N
ANALOG
IN
ta
N+1
t a = 0.7 TYPICAL
N+2
tOD
ENCODE
tOD = 15–27.5 TYPICAL
DATA
OUTPUT
N–3
N–2
N–1
N
AD9022 Timing Diagram
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS 1
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V to +1.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS to 0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature Range
AD9022AQ/AZ/BQ/BZ . . . . . . . . . . . . . . . –25°C to +85°C
AD9022SQ/SZ . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Maximum Junction Temperature2 . . . . . . . . . . . . . . . . +175°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Model
Package
Description
Q-28
Z-28
AD9022SQ
AD9022SZ
Q-28
Z-28
–3–
28-Lead Ceramic DIP
28-Pin Ceramic
Leaded Chip Carrier
–55°C to +125°C 28-Lead Ceramic DIP
–55°C to +125°C 28-Pin Ceramic
Leaded Chip Carrier
Package
Option
AD9022AQ/BQ –25°C to +85°C
AD9022AZ/BZ –25°C to +85°C
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances: “Q” Package (Ceramic DIP): θJC = 10°C/W; θJA =
35°C/W. “Z” Package (Gullwing Surface Mount): θJC = 13°C/W; θJA = 45°C/W.
REV. B
Temperature
Range
AD9022
PIN FUNCTION DESCRIPTIONS
EXPLANATION OF TEST LEVELS
Test Level
Pin No.
Name
Function
II – 100% production tested at +25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
1–3
D3–D1
Digital output bits of ADC; TTL
compatible.
III – Sample tested only.
4
D0 (LSB)
IV – Parameter is guaranteed by design and characterization
testing.
Least significant bit of ADC output;
TTL compatible.
5
NC
No Connection Internally
V – Parameter is a typical value only.
6
+VS
+5 V Power Supply
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; guaranteed by design and characterization testing for industrial devices.
7
GND
Ground
8
ENCODE
Encode clock input to ADC. Internal
T/H is placed in hold mode (ADC is
encoding) on rising edge of encode
signal.
9
GND
Ground
10
+VS
+5 V Power Supply
11
GND
Ground
12
AIN
Noninverting input to T/H amplifier.
13
–VS
–5.2 V Power Supply
14
+VS
+5 V Power Supply
15
–VS
–5.2 V Power Supply
16
GND
Ground
17
COMP
Should be connected to –V S through
0.1 µF capacitor.
18
D11 (MSB) Most significant bit of ADC output;
TTL compatible.
19–25
D10–D4
Digital output bits of ADC; TTL
compatible.
26
+VS
+5 V Power Supply
I
– 100% production tested.
DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . . . . 205 × 228 × 21 (± 1) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4,080
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride
Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
27
–VS
–5.2 V Power Supply
28
GND
Ground
PIN DESIGNATIONS
D3 1
28 GND
D2 2
27 –VS
D1 3
26 +VS
D0 (LSB) 4
25 D4
NC 5
24 D5
+VS
6
AD9022
23 D6
TOP VIEW 22 D7
ENCODE 8 (Not to Scale) 21 D8
GND 7
GND 9
20 D9
+VS 10
19 D10
GND 11
18 D11(MSB)
AIN 12
17 COMP
–VS 13
16 GND
+VS 14
15 –VS
NC = NO CONNECT
COMPENSATION (PIN 17) SHOULD BE
CONNECTED TO –VS THROUGH 0.01mF
–4–
REV. B
AD9022
+VS
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by FFT analysis) is
reduced by 3 dB.
+VS
Aperture Delay
180V
ANALOG
INPUT
The delay between the rising edge of the ENCODE command
and the instant at which the analog input is sampled.
10pF
120V
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
–VS
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Analog Input
Harmonic Distortion
The rms value of the fundamental divided by the rms value of
the worst harmonic component.
+VS
100V
Integral Nonlinearity
ENCODE
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit.
900V
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency tested drops by no more than 3 dB below the guaranteed limit.
–VS
Encode Input
Maximum Conversion Rate
COMPENSATION
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% point of the rising edge of the ENCODE command and the time when all output data bits are
within valid logic levels.
50V
–VS
Overvoltage Recovery Time
The amount of time required for the converter to recover to
12-bit accuracy after an analog input signal 150% of full scale is
reduced to the full-scale range of the converter.
20pF
–VS
Power Supply Rejection Ratio (PSRR)
Compensation
The ratio of a change in input offset voltage to a change in
power supply voltage.
+VS
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude to the rms value of
“noise,” which is defined as the sum of all other spectral components, including harmonics but excluding dc, with an analog
input signal 1 dB below full scale.
11kV
12kV
DIGITAL
OUTPUT
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude to the rms value of
“noise,” which is defined as the sum of all other spectral components, excluding the first five harmonics and dc, with an analog
input signal 1 dB below full scale.
–VS
Transient Response
Output Stage
The time required for the converter to achieve 12-bit accuracy
when a step function is applied to the analog input.
Figure 1. Equivalent Circuits
Two-Tone Intermodulation Distortion (IMD) Rejection
The ratio of the power of either of two input signals to the
power of the strongest third-order IMD signal.
REV. B
–5–
AD9022–Typical Performance Characteristics
70
–75
+258C
ROOM
–74
65
+258C
60
–558C
–73
SNR – dB
WORST CASE HARMONIC DISTORTION – dBc
–76
–558C
–72
55
50
–71
45
+1258C
40
–69
35
1.24 2.3
–68
0
1
2
3
4
5
6
7
8
ANALOG INPUT FREQUENCY – MHz
9
10
5.3
7.3
9.6
11.3
13.3
15.3
17.3
19.3
ANALOG INPUT FREQUENCY – MHz
Figure 2. Harmonic Distortion vs. Analog Input
Frequency
Figure 5. Signal-to-Noise Ratio vs. Analog Input
Frequency
85
90
AIN = 1.2MHz
80
80
AIN = 1.2MHz
ENCODE = 20MHz
70
WORST HARMONICS
SFDR AND SNR – dB
HARMONICS AND SNR – dB
+1258C
–70
75
70
SNR
65
SFDR
60
50
SNR
40
30
20
60
10
55
5.0
7.5
10.0
12.5
15.0
17.5
20.0
ENCODE RATE – MSPS
22.5
0
–50
25.0
–40
–35
–30
–25
–20
–15
–10
–5
–1
INPUT LEVEL – dB
Figure 3. SNR and Harmonics vs. Encode Rate
Figure 6. SFDR and SNR vs. Analog Input Level
2.0
80
AIN = 1.2MHz
FS = 20MSPS
1.5
70
1.0
AIN = 9.6MHz
ENCODE = 20MHz
SFDR
60
SFDR AND SNR – dB
DIFFERENTIAL NONLINEARITY – LSBs
–45
0.5
0
–0.5
50
SNR
40
30
–1.0
20
–1.5
10
–2.0
1024
2048
3072
0
–50
4096
OUTPUT CODE
–45
–40
–35
–30
–25
–20
–15
–10
–5
–1
INPUT LEVEL – dB
Figure 4. Differential Nonlinearity vs. Output Code
Figure 7. SFDR and SNR vs. Analog Input Level
–6–
REV. B
AD9022
is present when the unit is strobed with an ENCODE command. The conversion process begins on the rising edge of this
pulse, which should conform to the minimum and maximum
pulsewidth requirements shown in the specifications. Operation
below the recommended encode rate (4 MSPS) may result in
excessive droop in the internal T/H devices–leading to large dc
and ac errors.
0
–10
AIN = 1.2MHz
AIN = –1.0dBFS
SNR = 66.7dB
THD = 77.51dB
SFDR = 79.49dBFS
FULL SCALE – dB
–20
–30
–40
–50
The held analog value of the first track-and-hold is applied to a
5-bit flash converter and a second T/H. The 5-bit flash converter resolves the most significant bits (MSBs) of the held
analog voltage. These five bits are reconstructed via a 5-bit
DAC and subtracted from the original T/H output signal to
form a residue signal.
–60
–70
–80
–90
–100
0
A second T/H holds the amplified residue signal while it is encoded with a second 5-bit flash ADC. Again the five bits are
reconstructed and subtracted from the second T/H output to
form a residue signal. This residue is amplified and encoded
with a 4-bit flash ADC to provide the three least significant bits
(LSBs) of the digital output and one bit of error correction.
10
FREQUENCY – MHz
Figure 8. FFT Plot
0
AIN = 9.6MHz
AIN = –1.0dBFS
SNR = 66.05dB
THD = 74.28dB
SFDR = 75.32dBFS
–10
FULL SCALE – dB
–20
–30
Digital Error Correction logic aligns the data from the three
flash converters and presents the result as a 12-bit parallel digital word. The output stage of the AD9022 is TTL. Output data
may be strobed on the rising edge of the ENCODE command.
–40
–50
AD9022 IN RECEIVER APPLICATIONS
–60
Advances in semiconductor processes have resulted in low cost
digital signal processing (DSP) and analog signal processing
which can help create cost effective alternative receiver designs.
Today, an all-digital receiver allows tuning, demodulation, and
detection of receiver signals in the digital domain. By digitizing
IF signals directly, and utilizing digital techniques, it becomes
possible to make significant improvements in receiver design.
For high frequency IFs, the ADC is the key to the receiver’s
performance. Unfortunately, the specifications frequently used
by receiver designers and analog-to-digital (ADC) manufacturers are often very different. Noise Figure and Intercept Point are
common measures of noise and linearity in analog RF system
design. ADCs are more frequently specified in terms of SNR
and harmonic distortion.
–70
–80
–90
–100
0
10
FREQUENCY – MHz
Figure 9. FFT Plot
0
FULL SCALE – dB
20
AIN1 = 8.9MHz
AIN2 = 9.8MHz
AIN1 = 7.0dBFS
AIN2 = 7.0dBFS
SFDR = 80.62dBFS
40
Noise
Noise figure (NF) is a measure of receiver sensitivity and is
defined as the degradation of signal-to-noise ratio (SNR) as a
signal passes through a device. In equation form:
60
80
NF = SNR (in) – SNR (out)
Noise figure is a bandwidth invariant parameter for reasonably
narrow bandwidths in most devices. The system noise figure for
a combination of amplifiers and mixers, for instance, can be
analyzed without regard to the information bandwidth.
100
120
0.0
2.0
4.0
6.0
FREQUENCY – MHz
8.0
10.0
Refer to the block diagram.
Thermal noise contribution from the ADC behaves in a similar
fashion; however, the spectral density of quantization noise is a
function of the sample rate. In addition, the spectral density of
the quantization noise is flat only in an ADC with perfect linearity, i.e., perfect 1 LSB step sizes.
The AD9022 employs a three-pass subranging architecture and
digital error correction. This combination of design techniques
ensures 12-bit accuracy at relatively low power.
To analyze the system noise performance, ADC noise figure is
calculated by normalizing the SNR of the ADC output to a 1 Hz
bandwidth. This result is given by:
Analog input signals are immediately attenuated through a
resistor divider and applied directly to the sampling bridge of
the track-and-hold (T/H). The T/H holds whatever analog value
SNR (/Hz) = SNR + 10 log10 (FS/2)
where FS is the sample rate.
Figure 10. Two-Tone FFT
THEORY OF OPERATION
REV. B
–7–
AD9022
This will be true only for converters in which perfect quantization noise dominates. There may be an upper sample rate,
above which the thermal noise of the converter is the dominant
source of noise. In this case, normalization would be based on
the noise bandwidth of the ADC. For an AD9022 with a typical
SNR of 64 dB and a sample rate of 20 MSPS, the normalized
SNR is equal to 134 dB (64 + 70). Both thermal and quantization noise contribute to this number.
The SNR of the input is assumed to be limited by the thermal
noise of the input resistance, or –174 dBm/Hz. The input signal
level is +10 dBm (2 V p-p into 50 Ω). Noise figure of the ADC
can be calculated by:
AD9022 NOISE PERFORMANCE
High speed, wide bandwidth ADCs such as the AD9022 are
optimized for dynamic performance over a wide range of analog
input frequencies. However, there are many applications (Imaging, Instrumentation, etc.) where dc precision is also important.
Due to the wide input bandwidth of the AD9022 for a given
input voltage, there will be a range of output codes which may
occur. This is caused by unavoidable circuit noise within the
wideband circuits in the ADC. If a dc signal is applied to the
ADC and several thousand outputs are recorded, a distribution
of codes such as that shown in the histogram below may result.
2.0
RELATIVE FREQUENCY OF OCCURRENCE
NF = SNR (in) – SNR (out) = [+10 – (174)] – 134 = 50 dB
Most ADCs detect input voltage levels, not power. Consequently, the input SNR can be determined more accurately by
determining the ratio of the signal voltage to the noise voltage of
the terminating resistor. However, both the input signal and
noise voltage delivered to the ADC are also a function of the
source impedance. The dependence of NF on sample rate,
linearity, source and terminating impedances, and the number
of assumptions required, highlight the weakness of using NF as
a figure of merit for an ADC. The rather large number that
results bolsters this belief by indicating the ADC is often the
weakest link in the signal processing path.
For signals near full scale, the intercept point is calculated the
same as any device:
Intercept Point = [Harmonic Suppression/(N –1)] + Input Power
where N = the order of the IMD (3 in this case)
AD9022 Intercept Point = 80/2 + 3 dBm (7 dBm below full scale)
= 43 dBm
For signals below this level, the spurious free dynamic range
(SFDR) curves shown in the data sheet are a more accurate
predictor of dynamic range. The SFDR curve is generated by
measuring the ratio of the signal (either tone in the two-tone
measurement) to the worst spurious signal, which is observed as
the analog input signal amplitude is swept.
The worst spurious signal is usually the second harmonic or 3rd
order IMD. Actual results are shown on several plots. The
straightline with a slope of one is constructed at the point where
the worst SFDR touches the line. This line, extrapolated to full
scale, gives the SFDR of the ADC. This value can then be used
to predict the dynamic range by simply subtracting the input
level from the SFDR.
It should be noted that all SFDR lines are constructed to be
valid only below a certain level below full scale. Above these
points, the linearity of the device is dominated by the nonlinearities
of the front end and best predicted by the intercept point.
ONE STANDARD
DEVIATION = RMS
NOISE LEVEL
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
Linearity
The Third Order intercept point for a linear device (with some
nonlinearity) is a good way to predict 3rd order spurious signals
as a function of input signal level. For an ADC, however, this in
an invalid concept except with signals near full scale. As the
input signal is reduced, the performance burden shifts from the
input track-and-hold (T/H) to the encoder. This creates a nonlinear function, as contrasted with the third order intercept
behavior, which predicts an improvement in dynamic range as
the signal level is decreased.
1.5
x–3
x–2
x–1
x
x+1
x+2
x+3
OUTPUT CODE
Figure 11. ADC Equivalent Input Noise
The correct code appears most of the time, but adjacent codes
also appear with reduced probability. If a normal probability
density curve is fitted to this Gaussian distribution of codes, the
standard deviation will be equal to the equivalent input rms
noise of the ADC. The rms noise may also be approximated by
converting the SNR, as measured by a low frequency FFT, to
an equivalent input noise. This method is accurate only if the
SNR performance is dominated by random thermal noise (the
low frequency SNR without harmonics is the best measure).
Sixty-three dB equates to 1 LSB rms for a 2 V p-p (0.707 V
rms) input signal. The AD9022 has approximately 0.5 LSB of
rms noise or a noise limited SNR of 69 dB, indicating that noise
alone does not limit the SNR performance of the device (quantization noise and linearity are also major contributors).
This thermal noise may come from several sources. The drive
source impedance should be kept low to minimize resistor
thermal noise. Some of the internal ADC noise is generated in
the wideband T/H. Sampling ADCs generally have input bandwidths which exceed the Nyquist frequency of one-half the
sampling rate. (The AD9022 has an input bandwidth of over
100 MHz, even though the sampling rate is limited to 20 MSPS.)
Wide bandwidth is required to minimize gain and phase distortion and to permit adequate settling times in the internal amplifiers and T/Hs. But a certain amount of unavoidable noise is
generated in the T/H and other wideband circuits within the
ADC; this causes variation in output codes for dc inputs. Good
layout, grounding and decoupling techniques are essential to
prevent external noise from coupling into the ADC and further
corrupting performance.
–8–
REV. B
AD9022
The duty cycle of the encode clock for the AD9022 is critical for
obtaining rated performance of the ADC. Internal pulsewidths
within the track-and-hold are established by the encode command pulsewidth; to ensure rated performance, minimum and
maximum pulsewidth restrictions should be observed. Operation at
20 MSPS is optimized when the duty cycle is held at 55%.
USING THE AD9022
Layout Information
Preserving the accuracy and dynamic performance of the
AD9022 requires that designers pay special attention to the
layout of the printed circuit board.
Analog paths should be kept as short as possible and be properly
terminated to avoid reflections. The analog input connection
should be kept away from digital signal paths; this reduces the
amount of digital switching noise, which is capacitively coupled
into the analog section. Digital signal paths should also be kept
short, and run lengths should be matched to avoid propagation
delay mismatch. The AD9022 digital outputs should be buffered or latched close to the device (<2 cm). This prevents load
transients that may feed back into the device.
Analog Input
The analog input (Pin 12) voltage range is nominally ± 1.024
volts. The range is set with an internal voltage reference and
cannot be adjusted by the user. The input resistance is 300 Ω
and the analog bandwidth is 110 MHz, making the AD9022
useful in undersampling applications.
The AD9022 should be driven from a low impedance source.
The noise and distortion of the amplifier should be considered
to preserve the dynamic range of the AD9022.
In high speed circuits, layout of the ground is critical. A single,
low impedance ground plane on the component side of the
board is recommended. Power supplies should be capacitively
coupled to the ground plane with high quality 0.1 µF chip capacitors to reduce noise in the circuit. All power pins of the
AD9022 should be bypassed individually. The compensation
pin (COMP Pin 17) should be bypassed directly to the –VS
supply (Pin 15) as close to the part as possible using a 0.1 µF
chip capacitor.
Power Supplies
The power supplies of the AD9022 should be isolated from the
supplies used for noisy devices (digital logic especially) to reduce the amount of noise coupled into the ADC. For optimum
performance, linear supplies ensure that switching noise from
the supplies does not introduce distortion products during
the encoding process. If switching supplies must be used,
decoupling recommendations above are critically important.
The PSRR of the AD9022 is a function of the ripple frequency
present on the supplies. Clearly, power supplies with the lowest
possible frequency should be selected.
Multilayer boards allow designers to lay out signal traces without interrupting the ground plane, and provide low impedance
ground planes. In systems with dedicated analog and digital
grounds, all grounds for the AD9022 should be connected to
the analog ground plane.
AD9022 EVALUATION BOARD
The evaluation board for the AD9022 (AD9022/PCB) provides
an easy and flexible method for evaluating the ADC’s performance without (or prior to) developing a user-specific printed
circuit board. The two-sided board includes a reconstruction
DAC and digital output interface, and uses the layout and applications suggestions outlined above. It is available at nominal
cost from Analog Devices, Inc.
In systems using multilayer boards, dedicated power planes are
recommended to provide low impedance connections for device
power. Sockets limit dynamic performance and are not recommended for use with the AD9022.
Timing
Conversion by the AD9022 is initiated by the rising edge of the
ENCODE clock (Pin 8). All required timing is generated internal to the ADC. Care should be taken to ensure that the encode
clock to the AD9022 is free from jitter that can degrade dynamic performance. The clock driver should be compatible with
TTL LS logic series devices. Drivers with excessive slew rate or
overdrive will degrade the dynamic performance of the AD9022.
Input/Output/Supply Information
Power supply, analog input, clock connections and reconstructed output (RC OUTPUT) are identified by labels on the
evaluation board.
Operation of the evaluation board will conform to the following
characteristics:
Pulsewidth of the ADC encode clock must be controlled to
ensure the best possible performance. Dynamic performance is
guaranteed with a clock pulse HIGH minimum of 25 ns. Operation with narrower pulses will degrade SNR and dynamic performance. From a system perspective, this is generally not a
problem, because a simple inverter can be used to generate a
suitable clock if the system clock is less than 25 ns wide.
Parameter
Supply Current
+5 V
–5 V
AIN
Impedance
Voltage Range
CLOCK
Impedance
Frequency
RC OUTPUT
Impedance
Voltage Range
The AD9022 provides latched data outputs. Data outputs are
available two pipeline delays and one propagation delay after the
rising edge of the encode clock (refer to the AD9022 Timing
Diagram). The length of the output data lines and the loads
placed on them should be minimized to reduce transients within
the AD9022; these transients can detract from the converter’s
dynamic performance.
Operation at encode rates less than 4 MSPS is not recommended. The internal track-and-hold saturates, causing erroneous conversions. This T/H saturation precludes clocking the
AD9022 in a burst mode.
REV. B
–9–
Typical
Units
150
300
mA
mA
51
± 1.024
Ω
V
51
20
Ω
MSPS
51
0 to –1
Ω
V
AD9022
signal. The AD9713B is terminated into 51 Ω to provide a
1 V p-p signal at the output (RC Output).
Analog Input
Analog input signals can be directly fed into the device under
test input (AIN). The AIN input is terminated at the device with
a 62 Ω resistor to give a parallel equivalent of 51 Ω (62 Ωi300 Ω).
Output Data
The output data bits are latched with two 74LS574 latches
which drive a 40-pin connector (AMP p/n 102153-09). The
data and clock signals are available at the connector per the pin
assignments shown on the schematic of the evaluation board.
Data is latched on the rising edge of the encode clock.
DAC Reconstruction
The AD9022 evaluation board provides an onboard AD9713B
reconstruction DAC for observing the digitized analog input
U3
74LS574
U2
AD9698R
BNC
J1
5
CLOCK
R1
51V
2
3
4
5
6
7
8
9
11
6
CLK
9 12
E2 E1
1Q
1D
2Q
2D
3Q
3D
4Q
4D
5Q
5D
6Q
6D
7Q
7D
8Q
8D
CK OE
11
3
16
D8
D9
13
C1
0.1mF
D10
D7
D11
D6
D12 LSB
D5
1
CR1
AD589H
2
D4
R21
100V
BNC
J2
U5
AD9713P
R8
R9
D11
D10
R10
2
R11
3
D9
1
4
9
10
8
8
12
U6
74AS32
D3
ENCODE
AIN
D2
MSB D1
COMP
25
24
23
22
21
20
19
18
17
AIN
2
3
4
5
6
7
8
9
1Q
1D
2Q
2D
3Q
3D
4Q
4D
5Q
5D
6Q
6D
7Q
7D
8Q
8D
CK OE
11
R7
62V
D8
U4
74LS574
U1
AD9022Q
14
4
R2
5.1kV
D12
5
U2
AD9698R
+5V
19
18
17
16
15
14
13
12
D7
19
18
D6
D5
D4
17
D3
D2
16
15
14
R12
6
R14
7
R15
8
R16
9
R17
10
R18
11
R19
14
R20
28
26
13
12
D12 (LSB)
D11
RSET
D10
REFOUT
D9
D8
D7
D6
D5
D4
IOUT
D3
IOUT
D2
R3
20V
C5
0.1mF
–5.2V
16
R5
51V
14
D1 (MSB)
BNC
J4
LE
RC
OUT
D1
R6
51V
1
C4
0.1mF
H40DMC
J3
U6
74AS32
1
2
+5V
C6
0.1mF
C7
0.1mF
C8
0.1mF
C9
0.1mF
C10
0.1mF
C11
0.1mF
C12
0.1mF
C13
0.1mF
C22
0.1mF
J5
J6
J7
C14
0.1mF
C15
0.1mF
C16
0.1mF
C17
0.1mF
C18
0.1mF
C19
0.1mF
C20
0.1mF
3
–5.2V
+5V
U6
74AS32
GND
4
5
–5.2V
C3
10mF
20%
35V
20
19
CIN
18
COUT
17
REFIN
–5.2V
C2
10mF
20%
35V
R4
24 7.5kV
C21
0.1mF
6
CLK
D1
D2
D3
D4
D5
D6
D7
D8
U6
74AS32
12
13
11
D9
D10
D11
D12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Figure 12. AD9022/PCB Evaluation Board Schematic
–10–
REV. B
AD9022
Figure 13. Top of Board, Viewed From Top
Figure 14. Center of Board, Viewed From Top
REV. B
–11–
C1964a–0–1/98
AD9022
Figure 15. Bottom of Board, Viewed from Bottom
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Cerdip
(Q-28)
0.005 (0.13) MIN
28-Pin Ceramic Leaded Chip Carrier
(Z-28)
0.165 (4.191)
MAX
0.100 (2.54) MAX
28
0.73 (18.544)
0.71 (18.036)
0.012 (0.305)
0.009 (0.229)
15
0.610 (15.49)
0.500 (12.70)
28
PIN 1
1.490 (37.85) MAX
0.225
(5.72)
MAX
0.620 (15.75)
0.590 (14.99)
0.015
(0.38)
MIN
0.150
(3.81)
MIN
0.200 (5.08) 0.026 (0.66) 0.110 (2.79) 0.070 (1.78) SEATING
0.125 (3.18) 0.014 (0.36) 0.090 (2.29) 0.030 (0.76) PLANE
15
0.025
(0.635)
MIN
14
0.765 (19.431)
0.745 (18.923)
0.018 (0.46)
0.008 (0.20)
0.060 (1.524)
0.040 (1.016)
15
0
0.115 (2.921)
MAX
–12–
0.51 (12.954)
0.49 (12.446)
TOP VIEW
1
PRINTED IN U.S.A.
1
14
0.050 (1.27)
TYP
0.015 (0.381)
MIN
REV. B
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