ONSEMI MC74VHC1G05DTT1G

MC74VHC1G05
Single Inverter with Open
Drain Output
The MC74VHC1G05 is an advanced high speed CMOS inverter with
open drain output fabricated with silicon gate CMOS technology.
The internal circuit is composed of three stages, including an open
drain output which provides the capability to set output switching level.
This allows the MC74VHC1G05 to be used to interface 5 V circuits to
circuits of any voltage between VCC and 7 V using an external resistor
and power supply.
The MC74VHC1G05 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage.
•
•
•
•
•
•
High Speed: tPD = 3.8 ns (Typ) at VCC = 5 V
Low Internal Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FET = 105
Pb−Free Packages are Available
NC
1
5
SC−88A / SOT−353 / SC−70
DF SUFFIX
CASE 419A
5
VF M G
G
1
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
CASE 483
5
VF M G
G
1
VF
= Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
VCC
OVT
IN A
MARKING
DIAGRAMS
M
Features
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2
PIN ASSIGNMENT
GND
3
4
OUT Y
Figure 1. Pinout (Top View)
1
NC
2
IN A
3
GND
4
OUT Y
5
VCC
FUNCTION TABLE
1
IN A
OUT Y
Figure 2. Logic Symbol
A Input
Y Output
L
H
Z
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
February, 2007 − Rev. 14
1
Publication Order Number:
MC74VHC1G05/D
MC74VHC1G05
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Characteristics
−0.5 to +7.0
V
VIN
DC Input Voltage
−0.5 to +7.0
V
VOUT
DC Output Voltage
−0.5 to 7.0
V
IIK
Input Diode Current
IOK
Output Diode Current
IOUT
ICC
TSTG
−20
mA
+20
mA
DC Output Current, per Pin
+25
mA
DC Supply Current, VCC and GND
+50
mA
*65 to )150
°C
260
°C
)150
°C
SC70−5/SC−88A/SOT−353 (Note 1)
SOT23−5/TSOP−5/SC59−5
350
230
°C/W
SC70−5/SC−88A/SOT−353
SOT23−5/TSOP−5/SC59−5
150
200
mW
VOUT < GND; VOUT > VCC
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance
PD
Power Dissipation in Still Air at 85°C
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
Level 1
Oxygen Index: 28 to 34
ILATCHUP
Latchup Performance
UL 94 V−0 @ 0.125 in
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
N/A
V
Above VCC and Below GND at 125°C (Note 5)
$500
mA
ESD Withstand Voltage
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Max
Unit
VCC
DC Supply Voltage
2.0
5.5
V
VIN
DC Input Voltage
0.0
5.5
V
DC Output Voltage
0.0
7.0
V
TA
Operating Temperature Range
−55
+125
°C
tr, tf
Input Rise and Fall Time
0
0
100
20
ns/V
VOUT
Characteristics
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
TJ = 80°C
117.8
TJ = 90°C
1,032,200
TJ = 100°C
80
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 110°C
Time, Years
TJ = 120°C
Time, Hours
TJ = 130°C
Junction
Temperature °C
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
1
1
10
100
1000
TIME, YEARS
1.0
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1G05
DC ELECTRICAL CHARACTERISTICS
VCC
Symbol
Parameter
Test Conditions
Min
1.5
2.1
3.15
3.85
VIH
Minimum High−Level
Input Voltage
2.0
3.0
4.5
5.5
VIL
Maximum Low−Level
Input Voltage
2.0
3.0
4.5
5.5
VOL
Maximum Low−Level
Output Voltage
VIN = VIH or VIL
TA ≤ 85°C
TA = 25°C
(V)
Typ
Max
Min
Max
1.5
2.1
3.15
3.85
−55 ≤ TA ≤ 125°C
Min
Max
1.5
2.1
3.15
3.85
Unit
V
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN = VIH
IOL = 50 mA
2.0
3.0
4.5
0.0
0.0
0.0
VIN = VIH
IOL = 4 mA
IOL = 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
Z−State Output Leakage
Current
VIN = VIL
VOUT = VCC or GND
5.5
$0.25
$2.5
$5.0
mA
IIN
Maximum Input
Leakage Current
VIN = 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
1.0
20
40
mA
IOFF
Power Off−Output
Leakage Current
VOUT = 5.5 V
VIN = 5.5 V
0
0.25
2.5
5
mA
ILKG
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AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns
TA ≤ 85°C
TA = 25°C
Typ
Max
CL = 15 pF
CL = 50 pF
5.0
7.5
7.1
10.6
VCC = 5.0 ± 0.5 V
RL = RI = 500 W
CL = 15 pF
CL = 50 pF
3.8
5.3
VCC = 3.3 ± 0.3 V
RL = RI = 500 W
CL = 50 pF
VCC = 5.0 ± 0.5 V
RL = RI = 500 W
CL = 50 pF
Symbol
Parameter
tPZL
Maximum Output
Enable Time,
Input A to Y
VCC = 3.3 ± 0.3 V
RL = RI = 500 W
Maximum Output
Disable Time
tPLZ
CIN
Min
Test Conditions
Maximum Input
Capacitance
Min
Max
−55 ≤ TA ≤ 125°C
Min
Max
Unit
8.5
12.0
10.0
14.5
ns
5.5
7.5
6.5
8.5
8.0
10.0
7.5
10.6
12.0
14.5
5.3
7.5
8.5
10.0
4
10
10
10
ns
pF
Typical @ 25°C, VCC = 5.0 V
CPD
18
Power Dissipation Capacitance (Note 6)
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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3
MC74VHC1G05
VCC
VCC − 7 V
OVT
RL
VCC
A
50%
GND
A
tPLZ
tPZL
Y
Figure 4. Output Voltage Mismatch Application
HIGH
IMPEDANCE
50% VCC
VOL +0.3 V
Figure 5. Switching Waveforms
VCC
VCC x 2
R1
PULSE
GENERATOR
DUT
RT
CL
RL
CL = 50 pF equivalent (Includes jig and probe capacitance)
RL = R1 = 500 W or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 6. Test Circuit
VCC
MC74VHC1G01
A
2.2 kW
B
VCC
VCC
MC74VHC1G03
1
C
D
F = (A • B) + (C+D) + E
MC74VHC1G05
A
5
2
3
MC74VHC1G05
RLED
1.5 V
3.3 V
220 W
4
A
E
GTL
Figure 7. Complex Boolean Functions
Figure 8. LED Driver
Figure 9. GTL Driver
ORDERING INFORMATION
Device
Package
MC74VHC1G05DFT1
SC70−5 / SC−88A / SOT−353
MC74VHC1G05DFT1G
SC70−5 / SC−88A / SOT−353
(Pb−Free)
MC74VHC1G05DFT2
SC70−5 / SC−88A / SOT−353
MC74VHC1G05DFT2G
SC70−5 / SC−88A / SOT−353
(Pb−Free)
MC74VHC1G05DTT1
SOT23−5 / TSSOP−5 / SC59−5
MC74VHC1G05DTT1G
SOT23−5 / TSSOP−5 / SC59−5
(Pb−Free)
Shipping †
3000/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1G05
PACKAGE DIMENSIONS
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE J
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
M
B
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
−−−
0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
−−−
0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
MC74VHC1G05
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE F
NOTE 5
2X
0.10 T
2X
0.20 T
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
5X
0.20 C A B
5
1
4
2
3
M
B
S
K
L
DETAIL Z
G
A
DIM
A
B
C
D
G
H
J
K
L
M
S
DETAIL Z
J
C
0.05
SEATING
PLANE
H
T
MILLIMETERS
MIN
MAX
3.00 BSC
1.50 BSC
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
1.25
1.55
0_
10 _
2.50
3.00
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
MC74VHC1G05/D