Cypress CY26200 T1/e1 clock generator Datasheet

CY26200
PRELIMINARY
T1/E1 Clock Generator
Features
Benefits
• Integrated phase-locked loop (PLL)
High-performance PLL tailored for T1/E1 clock generation
• Low-jitter, high-accuracy outputs
Meets critical timing requirements in complex system designs
• 3.3V operation
Enables application compatibility
Part Number
Outputs
Input Frequency Range
Output Frequencies
CY26200
1
19.44 MHz
1.544 MHz/2.048 MHz (selectable)
Logic Block Diagram
19.44 XIN
OSC
Q
XOUT
Φ
VCO
OUTPUT
DIVIDERS
CLK1
P
PLL
AVDD
AVSS
VDD
VSS
Pin Configuration
CY26200
8-pin SOIC
Table 1: CY26200 Frequency Select Option
8
XOUT
2
7
3
6
VSS
CLK1
4
5
VDD
XIN
1
AVDD
FS
AVSS
Cypress Semiconductor Corporation
Document #: 38-07335 Rev. *A
•
Frequency Select
CLK1
Unit
0
1.544
MHz
1
2.048
MHz
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 14, 2002
CY26200
PRELIMINARY
Pin Summary
Pin Name
Pin Number Pin Description
XIN
1
19.44-MHz Reference Input
AVDD
2
Analog Voltage Supply
FS
3
Frequency Select – see Table 1
AVSS
4
Analog Ground
VDD
5
Voltage Supply
CLK1
6
1.544-MHz/2.048-MHz Clock Output
VSS
7
Ground
XOUT[1]
8
Reference Output
Absolute Maximum Conditions
Parameter
Description
Min.
Max.
Unit
VDD
Supply Voltage
–0.5
7.0
V
TS
Storage Temperature[2]
–65
125
°C
TJ
Junction Temperature
125
°C
Digital Inputs
VSS – 0.3
VDD + 0.3
V
Digital Outputs Referred to VDD
VSS – 0.3
VDD + 0.3
V
Electrostatic Discharge
Recommended Operating Conditions
Parameter
2000
Description
VDD/AVDD
Operating Voltage
TA
Ambient Temperature (Commercial)
TA
Ambient Temperature (Industrial)
CLOAD
Max. Load Capacitance
fREF
Reference Frequency
Typ.
Max.
Unit
3.3
3.465
V
0
70
°C
–40
+85
°C
15
Power-up time for all VDD's to reach
minimum specified voltage (power
ramps must be monotonic)
DC Electrical Characteristics (Commercial)
Description
Min.
3.135
MHz
0.05
Min.
Typ.
Output High Current
VOH = VDD – 0.5, VDD = 3.3V
12
24
VOL = 0.5, VDD = 3.3V
12
24
IOL
Output Low Current
Input Capacitance
IIZ
Input Leakage Current
Conditions
500
IOH
CIN
Description
mA
Min.
Typ.
11
24
VOL = 0.5, VDD = 3.3V
11
24
Input Capacitance
IIZ
Input Leakage Current
Conditions
DC
t3
Description
20
mA
Max.
Unit
mA
mA
7
pF
25
mA
Typ.
Max.
Unit
55
µA
5
Supply Current
Sum of Core and Output Current
IDD
AC Electrical Characteristics (VDD = 3.3V, Commercial)
Parameter[3]
pF
µA
VOH = VDD – 0.5, VDD = 3.3V
Output Low Current
7
5
Output High Current
IOL
Unit
mA
IOH
CIN
ms
Max.
Supply Current
Sum of Core and Output Current
IDD
DC Electrical Characteristics (Industrial)
Parameter
pF
19.44
tPU
Parameter
V
Conditions
Min.
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of VDD
45
50
Rising Edge Slew Rate
Output Clock Rise Time, 20% - 80% of VDD
0.8
1.4
%
V/ns
Notes:
1. Float XOUT if XIN is externally driven
2. Rated for 10 years
3. Not 100% tested
Document #: 38-07335 Rev. *A
Page 2 of 5
CY26200
PRELIMINARY
AC Electrical Characteristics (VDD = 3.3V, Commercial) (continued)
Parameter[3]
Description
Conditions
t4
Falling Edge Slew Rate
Output Clock Fall Time, 80% - 20% of VDD
t9
Clock Jitter
Peak to Peak period jitter
Min.
Typ.
0.8
1.4
DC
Name
Description
Min.
Unit
V/ns
200
t10
PLL Lock Time
AC Electrical Characteristics (VDD = 3.3V, Industrial)
Parameter[3]
Max.
ps
3
ms
Typ.
Max.
Unit
55
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of VDD
45
50
t3
Rising Edge Slew Rate
Output Clock Rise Time, 20% – 80% of VDD
0.8
1.4
V/ns
t4
Falling Edge Slew Rate
Output Clock Fall Time, 80% – 20% of VDD
0.8
1.4
V/ns
t9
Clock Jitter
Peak to Peak period jitter
200
ps
t10
PLL Lock Time
%
3
ms
Test Circuit
V DD
CLK out
0.1 mF
C LOAD
OUTPUTS
GND
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY26200SC
S8
8-lead SOIC
Commercial
3.3V
CY26200SI
S8
8-lead SOIC
Industrial
3.3V
t3
t1
t2
CLK
50%
t4
80%
50%
CLK
20%
Figure 2. Rise and Fall Time Definitions
Figure 1. Duty Cycle Definition; DC = t2/t1
Document #: 38-07335 Rev. *A
Page 3 of 5
PRELIMINARY
CY26200
Package Diagram
8-lead (150-mil) SOIC S8
51-85066-A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07335 Rev. *A
Page 4 of 5
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY26200
Document Title: CY26200 T1/E1 Clock Generator
Document Number: 38-07335
ECN No.
Issue
Date
Orig. of
Change
**
111745
05/06/02
CKN
New Data Sheet
*A
121890
12/14/02
RBI
Power up requirements added to Operating Conditions Information
REV.
Document #: 38-07335 Rev. *A
Description of Change
Page 5 of 5
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