TI CY54FCT273TQSOP 8-bit register Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT273T
8-Bit Register
SCCS020 - March 1995 - Revised February 2000
Features
Functional Description
• Function, pinout, and drive compatible with FCT and
F logic
• FCT-C speed at 5.8 ns max. (Com’l)
FCT-A speed at 7.2 ns max. (Com’l)
• Reduced VOH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• ESD > 2000V
• Fully compatible with TTL input and output logic levels
• Extended commercial range of −40˚C to +85˚C
• Sink current
64 mA (Com’l), 32 mA (Mil)
Source current
32 mA (Com’l), 12 mA (Mil)
The FCT273T consists of eight edge-triggered D-type
flip-flops with individual D inputs and Q outputs. The common
buffered clock (CP) and master reset (MR) load and reset all
flip-flops simultaneously. The FCT273T is an edge-triggered
register. The state of each D input (one set-up time before the
LOW-to-HIGH clock transition) is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW by
a low voltage level on the MR input.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
D0
D1
D2
D3
D4
D5
D6
D7
CP
Q
D
Q
D
CP
CP
RD
Q
D
CP
RD
Q
D
CP
RD
Q
D
CP
RD
Q
D
CP
RD
Q
D
CP
RD
Q
D
CP
RD
RD
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FCT273T–1
Pin Configurations
Logic Symbol
LCC
Top View
D3
D2
Q2
Q1
D1
Q3
GND
CP
Q4
D4
DIP/SOIC/QSOP
Top View
MR
1
20
8 7 6 5 4
Q0
2
3
19
18
VCC
Q7
D7
4
17
16
D6
Q6
Q5
9
10
11
12
13
3
2
1
20
19
D0
Q0
MR
VCC
Q7
D0
D1
D5
Q5
Q6
D6
D7
14 1516 17 18
FCT273T–2
Q1
5
Q2
6
D2
7
15
14
D3
8
13
Q3
GND
9
10
12
11
D5
D4
D0
CP
MR
Q0
D1
D2
D3
D4
D5
D6
D7
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q4
FCT273T–4
CP
FCT273T–3
Function Table[1]
Operating Mode
Reset (clear)
Load ‘1’
Load ‘0’
Note:
1. H
h
L
l
X
MR
L
H
H
Inputs
CP
X
D
X
h
l
Output
Q
L
H
L
= HIGH Voltage Level steady state
= HIGH Voltage Level one set-up time prior to LOW-to-HIGH clock transition
= LOW Voltage Level steady state
= LOW Voltage Level one set-up time prior to the LOW-to-HIGH transition
= Don’t Care
= LOW-to-HIGH clock transition
Copyright
© 2000, Texas Instruments Incorporated
CY54/74FCT273T
Maximum Ratings[2, 3]
Operating Range
(Above which the useful life may be impaired. For user guidelines, not tested.)
Range
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied .................................................. −65°C to +135°C
Range
Ambient
Temperature
VCC
Commercial
All
–40°C to +85°C
5V ± 5%
Military[4]
All
–55°C to +125°C
5V ± 10%
Supply Voltage to Ground Potential..................−0.5V to +7.0V
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin).......120 mA
Power Dissipation ..........................................................0.5W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Electrical Characteristics Over the Operating Range
Parameter
VOH
Description
Output HIGH Voltage
VOL
Output LOW Voltage
Test Conditions
Min.
Typ.[5]
Max.
Unit
VCC=Min., IOH=–32 mA
Com’l
2.0
V
VCC=Min., IOH=–15 mA
Com’l
2.4
3.3
V
VCC=Min., IOH=–12 mA
Mil
2.4
3.3
V
VCC=Min., IOL=64 mA
Com’l
0.3
0.55
V
VCC=Min., IOL=32mA
Mil
0.3
0.55
V
VIH
Input HIGH Voltage
2.0
V
VIL
Input LOW Voltage
VH
Hysteresis[6]
All inputs
0.2
VIK
Input Clamp Diode Voltage
VCC=Min., IIN=–18 mA
–0.7
–1.2
V
II
Input HIGH Current
VCC=Max., VIN=VCC
5
µA
IIH
Input HIGH Current
VCC=Max., VIN=2.7V
±1
µA
IIL
Input LOW Current
VCC=Max., VIN=0.5V
IOS
Output Short Circuit Current[7]
VCC=Max., VOUT=0.0V
IOFF
Power-Off Disable
VCC=0V, VOUT=4.5V
0.8
–60
–120
V
V
±1
µA
–225
mA
±1
µA
Capacitance[6]
Parameter
Description
Typ.[5]
Max.
Unit
CIN
Input Capacitance
5
10
pF
COUT
Output Capacitance
9
12
pF
Notes:
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
4. TA is the “instant on” case temperature
5. Typical values are at VCC=5.0V, TA=+25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
2
CY54/74FCT273T
Power Supply Characteristics
Parameter
ICC
Description
Quiescent Power Supply Current
Test Conditions
VCC=Max., VIN ≤ 0.2V, VIN ≥ VCC-0.2V
Typ.[5]
Max.
Unit
0.1
0.2
mA
0.5
2.0
mA
∆ICC
Quiescent Power Supply Current
(TTL inputs HIGH)
ICCD
Dynamic Power Supply Current[9] VCC=Max., One Bit Toggling, 50% Duty Cycle,
Outputs Open, MR=VCC,
VIN ≤ 0.2V or VIN ≥ VCC-0.2V
0.06
0.12
mA/MHz
IC
Total Power Supply Current[10]
VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, One Bit Toggling at f1=5 MHz,
MR=VCC, VIN ≤ 0.2V or VIN ≥ VCC-0.2V
0.7
1.4
mA
VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, One Bit Toggling at f1=5 MHz,
MR=VCC, VIN=3.4V or VIN=GND
1.2
3.4
mA
VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, Eight Bits Toggling
at f1=2.5MHz, MR=VCC,
VIN ≤ 0.2V or VIN ≥ VCC-0.2V
1.6
3.2[11]
mA
VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, Eight Bits Toggling
at f1=2.5 MHz, MR=VCC,
VIN=3.4V or VIN=GND
3.9
12.2[11]
mA
VCC=Max., VIN=3.4V, f1=0, Outputs Open
Notes:
8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH = Duty Cycle for TTL inputs HIGH
NT = Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0 = Clock frequency for registered devices, otherwise zero
f1 = Input signal frequency
N1 = Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
3
[8]
CY54/74FCT273T
Switching Characteristics Over the Operating Range[12]
FCT273T
Commercial
Parameter
Description
FCT273AT
Military
Commercial
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Fig. No.[13]
tPLH
tPHL
Propagation Delay Clock to Output
2.0
13.0
2.0
8.3
2.0
7.2
ns
1, 5
tPLH
tPHL
Propagation Delay MR to Output
2.0
13.0
2.0
8.3
2.0
7.2
ns
1, 6
tS
Set-Up Time HIGH or LOW D to Clock
2.0
2.0
2.0
ns
4
tH
Hold Time HIGH or LOW D to Clock
1.5
1.5
1.5
ns
4
tW
Clock Pulse Width HIGH or LOW
6.0
6.0
6.0
ns
5
tW
MR Pulse Width LOW
6.0
6.0
6.0
ns
6
tREC
Recovery Time MR to Clock
2.0
2.5
2.0
ns
6
FCT273CT
Commercial
Parameter
Description
Min.
Max.
Unit
Fig. No.[13]
tPLH
tPHL
Propagation Delay Clock to Output
2.0
5.8
ns
1, 5
tPLH
tPHL
Propagation Delay MR to Output
2.0
6.1
ns
1, 6
tS
Set-Up Time HIGH or LOW D to Clock
2.0
ns
4
tH
Hold Time HIGH or LOW D to Clock
1.5
ns
4
tW
Clock Pulse Width HIGH or LOW
6.0
ns
5
tW
MR Pulse Width LOW
6.0
ns
6
tREC
Recovery Time MR to Clock
2.0
ns
6
Ordering Information
Speed
(ns)
5.8
7.2
8.3
13.0
Ordering Code
Package
Name
Package Type
CY74FCT273CTQCT
Q5
20-Lead (150-Mil) QSOP
CY74FCT273CTSOC/SOCT
S5
20-Lead (300-Mil) Molded SOIC
CY74FCT273ATQCT
Q5
20-Lead (150-Mil) QSOP
CY74FCT273ATSOC/SOCT
S5
20-Lead (300-Mil) Molded SOIC
CY54FCT273ATLMB
L61
20-Square Leadless Chip Carrier
CY54FCT273ATDMB
D6
20-Lead (300-Mil) CerDIP
CY74FCT273TQCT
Q5
20-Lead (150-Mil) QSOP
CY74FCT273TSOC/SOCT
S5
20-Lead (300-Mil) Molded SOIC
Notes:
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
Document #: 38-00380-A
4
Operating
Range
Commercial
Commercial
Military
Commercial
CY54/74FCT273T
Package Diagrams
20-Pin Square Leadless Chip Carrier L61
20-Lead (300-Mil) CerDIP D6
MIL-STD-1835 C-2A
MIL-STD-1835 D- 8 Config.A
20-Lead Quarter Size Outline Q5
5
CY54/74FCT273T
Package Diagrams (continued)
20-Lead (300-Mil) Molded SOIC S5
6
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