ICSI IC61S25636D-200TQ 8mb syncburst pipelined sram Datasheet

IC61S25632T/D IC61S25636T/D
IC61S51218T/D
Document Title
8Mb SyncBurst Pipelined SRAM
Revision History
Revision No
History
Draft Date
Remark
0A
0B
Initial Draft
1. Move the FT pin for user-configurable Flow
throught or pipelineed operation, That pin can be
NC or connected to VCC for pipelined operation.
Refer to Pin configuration.
2. Revise the power supply charaetoristics at page 12
3. Resive the tKQ of 250 MHZ from 2.5ns to 3ns.
4. Move the 100 MHZ speed grade.
September 24,2001
August 13,2002
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
1
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
256K x 32, 256K x 36, 512K x 18
8Mb S/DCD SYNCBURST Pipelined SRAMs
FEATURES
•
•
•
•
•
•
•
Pipeline Mode operation
Single/Dual Cycl Deselect
User-selectable Output Drive Strength with XQ Mode
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and control
Pentium™ or linear burst sequence control using
MODE input
Common data inputs and data outputs
JEDEC 100-Pin TQFP and 119-pin PBGA package
Single +3.3V, +10%, –5% core power supply
Power-down snooze mode
2.5V or 3.3V I/O Supply
Snooze MODE for reduced-power standby
T version (three chip selects)
D version (two chip selects)
•
•
•
•
•
•
•
•
DESCRIPTION
ICSI's 8Mb SyncBurst Pipelined SRAMs integrate a 512k
x 18, 256k x 32, or 256k x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst counter.
Applications
The ICSI SyncBurst Pipelined SRAM family employs
high-speed ,low-power CMOS designs that are fabricated
using an advanced CMOS process to provide Level 2
Cache applications supporting Pentium and PowerPC
microprocessors originally, the device now finds application ranging from DSP main store to networking chip set
support.
FAST ACCESS TIME
Pipeline
3-1-1-1
Symbol
tKQ
tKC
ICC1
-250
3
4
390
-200
3.1
5
360
-166
3.5
6
330
-133
4
7.5
300
Units
ns
ns
mA
Controls
All synchronous inputs pass through registers controlled by a
positive-edge-triggered single clock input.Bursts can be initiated
with either ADSP (Address Status Processor) or ADSC (Address
Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV
(burst address advance) input pin. The mode pin is used to select
the burst sequence order, Linear burst is achieved when this pin
is tied LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating.
SCD and DCD Pipelined Reads
The device is a SCD (Single Cycle Deselect) and DCD(Dual
Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs
pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input on Bump 4L.
Byte Write and Global Write
Write cycles are internally self-timed and are initiated by the rising
edge of the clock input. Write cycles can be from one to four bytes
wide as controlled by the write control inputs.Separate byte
enables allow individual bytes to be written. Byte write operation
is performed by using byte write enable (BWE).input combined
with one or more individualbyte write signals (BWx). In addition,
Global Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
IOL/IOH Drive strength Options
The XQ pin allows selection between high drive strength (XQ
low) for multi-drop bus applications and normal drive strength
(XQ floating or high) point-to-point applications. See the Output
Driver Characteristics chart for details.
Snooze Mode
Low power (Snooze mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK). Memory
data is retained during Snooze mode.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
BLOCK DIAGRAM
MODE
CLK
Q0
CLK
A0
A0'
BINARY
COUNTER
Q1
ADV
A1'
A1
256Kx32; 256Kx36;
512Kx18
MEMORY ARRAY
ADSC
ADSP
18/19
An-A0
16/17
D
18/19
Q
ADDRESS
REGISTER
CLK
32, 36,
or 18
GW
BWE
BWd
(x32/x36)
D
32, 36,
or 18
Q
DQd
BYTE WRITE
REGISTERS
CLK
BWb
(x32/x36)
D
DQc Q
BYTE WRITE
REGISTERS
CLK
D
BWa
(x32/x36/x18)
Q
DQb
BYTE WRITE
REGISTERS
CLK
BWa
(x32/x36/x18)
D
DQa Q
BYTE WRITE
REGISTERS
CLK
(T, D)CE
(T, D) CE2
(T) CE2
32, 36,
or 18
4
D
Q
ENABLE
REGISTER
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
DQa - DQd
OE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
3
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
100-Pin TQFP (D Version)
1
2
3
4
5
6
7
VCCQ
SA
SA
ADSP
SA
SA
VCCQ
NC
CE2
SA
ADSC
SA
SA
NC
NC
SA
SA
VCC
SA
SA
NC
DQc1
NC
GND
XQ
GND
NC
DQb8
DQc2
DQc3
GND
CE
GND
DQb6
DQb7
VCCQ
DQc4
GND
OE
GND
DQb5
VCCQ
DQc5
DQc6
BWc
ADV
BWb
DQb4
DQb3
DQc7
DQc8
GND
GW
GND
DQb2
DQb1
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
DQd1
DQd2
GND
CLK
GND
DQa7
DQa8
DQd4
DQd3
BWd
SCD
BWa
DQa5
DQa6
VCCQ
DQd5
GND
BWE
GND
DQa4
VCCQ
DQd6
DQd7
GND
A1
GND
DQa3
DQa2
DQd8
NC
GND
A0
GND
NC
DQa1
NC
SA
MODE
VCC
NC
SA
NC
NC
NC
SA
SA
SA
NC
ZZ
VCCQ
NC
NC
NC
NC
NC
VCCQ
SA
SA
CE
CE2
BWd
BWc
BWb
BWa
SA
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
SA
SA
119-pin PBGA (Top View)
A
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
SA
SA
SA
SA
A1
A0
NC
NC
GND
VCC
NC
NC
A10
SA
SA
SA
SA
SA
SA
U
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
SCD
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
256K x 32
Note:Ball R5 connecting to VCC is acceptable
Note:pin 14 connecting to VCC is acceptable
PIN DESCRIPTIONS
A0, A1
A2-A17
CLK
ADSP
ADSC
ADV
BWa -BWd
BWE
GW
CE , CE2
OE
4
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
DQa-DQd
MODE
SCD
XQ
VCC
GND
VCCQ
ZZ
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
+3.3V Power Supply
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
Snooze Enable
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
SA
SA
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
SA
SA
100-Pin TQFP (T Version)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
SCD
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
MODE
SA
SA
SA
SA
A1
A0
NC
NC
GND
VCC
NC
SA
SA
SA
SA
SA
SA
SA
SA
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
256K x 32
Note:Pin 14 connecting to Vcc is acceptable
PIN DESCRIPTIONS
A0, A1
A2-A17
CLK
ADSP
ADSC
ADV
BWa -BWd
BWE
GW
CE,CE2,CE2
OE
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
DQa-DQd
MODE
SCD
XQ
VCC
GND
VCCQ
ZZ
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
+3.3V Power Supply
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
Snooze Enable
5
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
100-Pin TQFP (D Version)
SA
SA
CE
CE2
BWd
BWc
BWb
BWa
A17
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
SA
SA
119-pin PBGA (Top View)
1
2
3
4
5
6
7
VCCQ
SA
SA
ADSP
SA
SA
VCCQ
NC
CE2
SA
ADSC
SA
SA
NC
NC
SA
SA
VCC
SA
SA
NC
DQc1
DQPc
GND
XQ
GND
DQPb
DQb8
DQc2
DQc3
GND
CE
GND
DQb6
DQb7
VCCQ
DQc4
GND
OE
GND
DQb5
VCCQ
DQc5
DQc6
BWc
ADV
BWb
DQb4
DQb3
DQc7
DQc8
GND
GW
GND
DQb2
DQb1
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
DQd1
DQd2
GND
CLK
GND
DQa7
DQa8
DQd4
DQd3
BWd
SCD
BWa
DQa5
DQa6
VCCQ
DQd5
GND
BWE
GND
DQa4
VCCQ
DQd6
DQd7
GND
A1
GND
DQa3
DQa2
DQd8
DQPd
GND
A0
GND
DQPa
DQa1
NC
SA
MODE
VCC
NC
SA
NC
NC
NC
SA
SA
SA
NC
ZZ
VCCQ
NC
NC
NC
NC
NC
VCCQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
SCD
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
MODE
SA
SA
SA
SA
A1
A0
NC
NC
GND
VCC
NC
NC
SA
SA
SA
SA
SA
SA
SA
U
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 36
Note:Ball R5 connecting to VCC is acceptable
Note:pin 14 connecting to VCC is acceptable
PIN DESCRIPTIONS
A0, A1
A2-A17
CLK
ADSP
ADSC
ADV
BWa -BWd
BWE
GW
CE , CE2
OE
6
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
DQa-DQd
MODE
SCD
XQ
VCC
GND
VCCQ
ZZ
DQPa-DQPd
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
+3.3V Power Supply
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
Snooze Enable
Parity Data I/O
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
SA
SA
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
SA
SA
100-Pin TQFP (T Version)
DQPc
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
SCD
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
MODE
SA
SA
SA
SA
A1
A0
NC
NC
GND
VCC
NC
SA
SA
SA
SA
SA
SA
SA
SA
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 36
Note:Pin 14 connecting to Vcc is acceptable
PIN DESCRIPTIONS
A0, A1
A2-A17
CLK
ADSP
ADSC
ADV
BWa -BWd
BWE
GW
CE,CE2,CE2
OE
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
DQa-DQd
MODE
SCD
XQ
VCC
GND
VCCQ
ZZ
DQPa-DQPd
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
+3.3V Power Supply
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
Snooze Enable
Parity Data I/O
7
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
100-Pin TQFP (D Version)
1
2
3
4
5
6
7
VCCQ
SA
SA
ADSP
SA
SA
VCCQ
NC
CE2
SA
ADSC
SA
SA
NC
NC
SA
SA
VCC
SA
SA
NC
DQc1
DQb2
GND
XQ
GND
DQPa
NC
NC
NC
GND
CE
GND
NC
DQb8
VCCQ
DQc4
GND
OE
GND
DQb7
VCCQ
NC
DQc3
BWb
ADV
GND
NC
DQb6
DQc4
NC
GND
GW
GND
DQb5
NC
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
Nc
DQd5
GND
CLK
GND
NC
DQa4
DQd6
NC
GND
SCD
BWa
DQa3
NC
VCCQ
DQd7
GND
BWE
GND
NC
VCCQ
DQd8
NC
GND
A1
GND
DQa2
NC
NC
DQPd
GND
A0
GND
NC
DQa1
NC
SA
MODE
VCC
NC
SA
NC
NC
SA
SA
NC
SA
SA
ZZ
VCCQ
NC
NC
NC
NC
NC
VCCQ
SA
SA
CE
CE2
NC
NC
BWb
BWa
A18
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
SA
SA
119-pin PBGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
NC
NC
NC
VCCQ
GND
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
NC
VCC
XQ
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
SA
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
SCD
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
GND
VCCQ
NC
NC
NC
MODE
SA
SA
SA
SA
A1
A0
NC
NC
GND
VCC
NC
NC
SA
SA
SA
SA
SA
SA
SA
U
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
512K x18
Note:Ball R5 connecting to VCC is acceptable
Note:pin 14 connecting to VCC is acceptable
PIN DESCRIPTIONS
A0, A1
A2-A18
CLK
ADSP
ADSC
ADV
BWa -BWb
BWE
GW
CE , CE2
OE
8
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
DQa-DQb
MODE
SCD
XQ
VCC
GND
VCCQ
ZZ
DQPa-DQPb
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
+3.3V Power Supply
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
Snooze Enable
Parity Data I/O DQPa is parity for
DQa1-8;DQPb is parity for DQb1-8
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
SA
SA
CE
CE2
NC
NC
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
SA
SA
100-Pin TQFP (T Version)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SA
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
SCD
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
GND
VCCQ
NC
NC
NC
MODE
SA
SA
SA
SA
A1
A0
NC
NC
GND
VCC
NC
SA
SA
SA
SA
SA
SA
SA
SA
NC
NC
NC
VCCQ
GND
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
NC
VCC
XQ
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
512K x18
Note:Pin 14 connecting to Vcc is acceptable
PIN DESCRIPTIONS
A0, A1
A2-A18
CLK
ADSP
ADSC
ADV
BWa -BWb
BWE
GW
CE,CE2,CE2
OE
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
DQa-DQb
MODE
SCD
XQ
VCC
GND
VCCQ
ZZ
DQPa-DQPb
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
+3.3V Power Supply
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
Snooze Enable
Parity Data I/O DQPa is parity for
DQa1-8;DQPb is parity for DQb1-8
9
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
Mode Pin Functions
Mode Name
Burst Order Control
Pin Name
MODE
Power Down Control
ZZ
Single/DualCycleDeselectControl
SCD
Output Drive Control
XQ
State
L
H or NC
L or NC
H
L
H or NC
L
H
Function
Linear Burst
Interleaved Burst
Active
Standby
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
Note:
There are pull-up devices on the MODE, XQ, and SCD pins and a pull down device on the ZZ pin, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above table.
TRUTH TABLE
Operation
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Address
Used
None
None
None
None
None
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
H
L
L
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE2
X
X
L
X
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
H
X
H
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
ADSP
X
L
L
H
H
L
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC
L
X
X
L
L
X
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WRITE
X
X
X
X
X
X
Read
Write
Read
Read
Read
Read
Write
Write
Read
Read
Read
Read
Write
Write
OE
X
X
X
X
X
X
X
X
L
H
L
H
X
X
L
H
L
H
X
X
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Q
D
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
10
GW
H
H
H
H
L
BWE BWa BW
b BWc BWd
BWb
H
X
X
X
X
L
H
H
H
H
L
L
H
H
H
L
L
L
L
L
X
X
X
X
X
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
INTERLEAVED BURST ADDRESS TABLE (MODE =
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
VCC or
No Connect)
3rd Burst Address
A1 A0
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS
Symbol
TBIAS
TSTG
PD
IOUT
VIN, VOUT
VIN
VCC
(1)
Parameter
Temperature Under Bias
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to GND for I/O Pins
Voltage Relative to GND for
for Address and Control Inputs
Voltage on Vcc Supply Relatiive to GND
Value
–40 to +85
–55 to +150
1.6
100
–0.5 to VCCQ + 0.5
–0.5 to VCC + 0.5
Unit
°C
°C
W
mA
V
V
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-nent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
11
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
OPERATING RANGE
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
V CC
3.3V, +10%, –5%
3.3V, +10%, –5%
VCCQ
2.375–3.6V
2.375–3.6V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
ILI
ILO
Input Leakage Current
Output Leakage Current
Test Conditions
IOH = –2.0 mA, VCCQ = 2.5V
IOH = –4.0 mA, VCCQ = 3.3V
IOL = 2.0 mA, VCCQ = 2.5V
IOL = 8.0 mA, VCCQ = 3.3V
VCCQ = 2.5V
VCCQ = 3.3V
VCCQ = 2.5V
VCCQ = 3.3V
GND ≤ VIN ≤ VCC (1)
GND ≤ VOUT ≤ VCCQ, OE = VIH
Min.
Max.
1.7
—
2.4
—
—
0.7
—
0.4
1.7 VCCQ+ 0.3
2.0 VCCQ + 0.3
–0.3
0.7
–0.3
0.8
–2
2
–2
2
Unit
V
V
V
V
V
V
V
V
µA
µA
Notes:
1. The MODE, ZZ, SCD, XQ, pin has an internal pullup. and input leakage = ±10 µA .
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Parameter
AC Operating
Supply Current
Test Conditions
Symbol
Device Selected,
ICC1
All Inputs ≤ VIL or ≥VIH
f = 1/tKC
Clock Running
Device Deselected,
Icc2
VCC = Max.,
All Inputs ≤ VIL or ≥VIH
f = 1/tKC
COMS Standby
Device Deselected,
ISB
VCC = Max.,
All Inputs ≤ 0.2V or ≥VCC -0.2V
f=0
IZZ
Power Dowin Mode VCC = Max
ZZ ≥VCC - 0.2V
f=0
All input ≤ 0.2V or ≥VCC -0.2V
12
Com.
Ind.
-250
Max.
390
410
-200
Max.
360
380
-166
Max.
330
350
-133
Max. Unit
300 mA
320
Com.
Ind.
110
130
100
120
90
110
85
105
mA
mA
Com.
Ind.
90
100
90
100
90
100
90
100
mA
mA
Com.
Ind.
80
90
80
90
80
90
80
90
mA
mA
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
CAPACITANCE
Symbol
CIN
COUT
(1,2)
Parameter Conditions
Input Capacitance
Input/Output Capacitance
Max.
VIN = 0V
VOUT = 0V
Unit
6
8
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V for 3.3V I/O
VCCQ/2V for 2.5V I/O
See Figures 1 and 2
AC TEST LOADS
ZO = 50Ω
317Ω /1667Ω
3.3V for 3.3V I/O
/2.5V for 2.5v I/O
Output
Buffer
50Ω
1.5V for 3,3V I/O
VCCQ/2V for 2.5V I/O
Figure 1
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
OUTPUT
5 pF
Including
jig and
scope
351Ω /1538Ω
Figure 2
13
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
Symbol
tKC
Pipeline tKQ
tKQX(1)
tKQLZ(1,2)
tKH
tKL
tKQHZ(1,2)
tOEQ
tOELZ(1,2)
tOEHZ(1,2)
tAS
tSS
tWS
tCES
tAVS
tDS
tDH
tAH
tSH
tWH
tCEH
tAVH
tZZS
tZZREC
Parameter
Cycle Time
Clock Access Time
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High Pulse Width
Clock Low Pulse Width
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup Time
Address Status Setup Time
Write Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Data Setup time
Data Hold time
Address Hold Time
Address Status Hold Time
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
ZZ Setup Time
ZZ Recovery Time
-250
Min. Max.
4
—
—
3
1.0 —
0
—
1.6 —
1.6 —
— 3.1
— 3.1
0
—
— 3.0
1.5 —
1.5 —
1.5 —
1.5 —
1.5 —
1.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
2
—
2
—
(Over Operating Range)
-200
-166
-133
Min. Max. Min. Max. Min. Max. Unit
5
—
6
—
7.5 — ns
— 3.1
—
3.5
—
4 ns
1.0 —
1.5
—
1.5 — ns
0
—
0
—
0
— ns
2
—
2.3
—
2.8 — ns
2
—
2.3
—
2.8 — ns
— 3.1
—
3.5
—
4 ns
— 3.1
—
3.5
—
4 ns
0
—
0
—
0
— ns
— 3.0
—
3.5
—
4 ns
1.5 —
1.5
—
1.5 — ns
1.5 —
1.5
—
1.5 — ns
1.5 —
1.5
—
1.5 — ns
1.5 —
1.5
—
1.5 — ns
1.5 —
1.5
—
1.5 — ns
1.5 —
1.5
—
1.5 — ns
0.5 —
0.5
—
0.5 — ns
0.5 —
0.5
—
0.5 — ns
0.5 —
0.5
—
0.5 — ns
0.5 —
0.5
—
0.5 — ns
0.5 —
0.5
—
0.5 — ns
0.5 —
0.5
—
0.5 — ns
2
—
2
—
2
— cyc
2
—
2
—
2
— cyc
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
14
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIPELINED SCD READ
CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
tSS
tSH
ADSC initiate read
ADSC
tAVH
tAVS
Suspend Burst
ADV
tAS
Address
tAH
RD1
RD2
tWS
tWH
tWS
tWH
RD3
GW
BWE
BW4-BW1
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE Masks ADSP
CE
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
CE2
CE2
tOEHZ
tOEQ
OE
DATAOUT
tKQX
tOEQX
tOELZ
High-Z
1a
2a
2b
tKQLZ
2c
2d
3a
tKQHZ
tKQ
DATAIN
High-Z
Single Read
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
Burst Read
Unselected
15
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIPELINED DCD READ CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
tSS
tSH
ADSC initiate read
ADSC
tAVH
tAVS
Suspend Burst
ADV
tAS
Address
tAH
RD1
RD2
tWS
tWH
tWS
tWH
RD3
GW
BWE
BW4-BW1
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE Masks ADSP
CE
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
CE2
CE2
tOEHZ
tOEQ
OE
DATAOUT
tKQX
tOEQX
tOELZ
High-Z
1a
2a
2b
tKQLZ
3a
3b
High-Z
Single Read
16
2d
tKQHZ
tKQ
DATAIN
2c
Burst Read
Unselected
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
ADSC initiate Write
ADSC
ADV must be inactive for ADSP Write tAVS
tAVH
ADV
tAS
Address
tAH
WR1
WR2
tWS
tWH
tWS
tWH
tWS
tWH
WR3
GW
BWE
BW4-BW1
WR1
tCES
tCEH
tCES
tCEH
tCES
tCEH
tWS
tWH
WR2
WR3
CE Masks ADSP
CE
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
CE2
CE2
OE
DATAOUT
High-Z
tDS
DATAIN
High-Z
tDH
1a
Single Write
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
BW4-BW1 only are applied to first cycle of WR2
2a
2b
2c
2d
Burst Write
3a
Write
Unselected
17
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
READ/WRITE CYCLE TIMING: PIPELINED
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE1 inactive
ADSP
tSS
tSH
ADSC
ADV
tAS
Addresses
tAH
RD1
WR1
tWS
tWH
tWS
tWH
RD2
RD3
GW
BWE
tWS
tWH
WR1
BW4-BW1
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE1 Masks ADSP
CE
CE2 and CE3 only sampled with ADSP or ADSC
CE2
Unselected with CE3
CE2
tOEHZ
tOEQ
OE
DATAOUT
High-Z
2a
1a
tKQLZ
tKQ
DATAIN
tKQX
tOEQX
tOELZ
2c
2d
tKQHZ
tKQX
tKQHZ
High-Z
1a
tDS
Single Read
18
2b
tDH
Single Write
Burst Read
Unselected
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
SNOOZE AND RECOVERY CYCLE TIMING
tKC
CLK
tSS
tSH
tAS
tAH
tKH
tKL
ADSP
ADSC
ADV
Address
RD1
RD2
GW
BWE
BW4-BW1
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE
CE2
CE2
tOEHZ
tOEQ
OE
tOEQX
tOELZ
DATAOUT
High-Z
1a
tKQLZ
tKQ
DATAIN
tKQX
tKQHZ
High-Z
tZZS
tZZREC
ZZ
Single Read
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
Snooze with Data Retention
Read
19
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
250 MHz
200 MHz
166 MHz
133 MHz
Speed
250 MHz
200 MHz
166 MHz
133 MHz
20
Order Part Number
IC61S25632T-250TQ
IC61S25632D-250TQ
IC61S25632D-250B
IC61S25632T-200TQ
IC61S25632D-200TQ
IC61S25632D-200B
IC61S25632T-166TQ
IC61S25632D-166TQ
IC61S25632D-166B
IC61S25632T-133TQ
IC61S25632D-133TQ
IC61S25632D-133B
Package
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14x20x1.4mm LQFP
14x20x1.4mm LQFP
14*22mm PBGA
14x20x1.4mm TQFP
14x20x1.4mm TQFP
14*22mm PBGA
Order Part Number
IC61S25636T-250TQ
IC61S25636D-250TQ
IC61S25636D-250B
IC61S25636T-200TQ
IC61S25636D-200TQ
IC61S25636D-200B
IC61S25636T-166TQ
IC61S25636D-166TQ
IC61S25636D-166B
IC61S25636T-133TQ
IC61S25636D-133TQ
IC61S25636D-133B
Package
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14x20x1.4mm LQFP
14x20x1.4mm LQFP
14*22mm PBGA
14x20x1.4mm TQFP
14x20x1.4mm TQFP
14*22mm PBGA
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
Speed
250 MHz
200 MHz
166 MHz
133 MHz
Order Part Number
IC61S51218T-250TQ
IC61S51218D-250TQ
IC61S51218D-250B
IC61S51218T-200TQ
IC61S51218D-200TQ
IC61S51218D-200B
IC61S51218T-166TQ
IC61S51218D-166TQ
IC61S51218D-166B
IC61S51218T-133TQ
IC61S51218D-133TQ
IC61S51218D-133B
Package
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14x20x1.4mm LQFP
14x20x1.4mm LQFP
14*22mm PBGA
14x20x1.4mm TQFP
14x20x1.4mm TQFP
14*22mm PBGA
Industrial Range: -40°C to 85°C
Speed
250 MHz
200 MHz
166 MHz
133 MHz
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
Order Part Number
IC61S25632T-250TQI
IC61S25632D-250TQI
IC61S25632D-250B
IC61S25632T-200TQI
IC61S25632D-200TQI
IC61S25632D-200B
IC61S25632T-166TQI
IC61S25632D-166TQI
IC61S25632D-166B
IC61S25632T-133TQI
IC61S25632D-133TQI
IC61S25632D-133B
Package
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14x20x1.4mm LQFP
14x20x1.4mm LQFP
14*22mm PBGA
14x20x1.4mm TQFP
14x20x1.4mm TQFP
14*22mm PBGA
21
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
Speed
250 MHz
200 MHz
166 MHz
133 MHz
Speed
250 MHz
200 MHz
166 MHz
133 MHz
Order Part Number
IC61S25636T-250TQI
IC61S25636D-250TQI
IC61S25636D-250B
IC61S25636T-200TQI
IC61S25636D-200TQI
IC61S25636D-200B
IC61S25636T-166TQI
IC61S25636D-166TQI
IC61S25636D-166B
IC61S25636T-133TQI
IC61S25636D-133TQI
IC61S25636D-133B
Package
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14x20x1.4mm LQFP
14x20x1.4mm LQFP
14*22mm PBGA
14x20x1.4mm TQFP
14x20x1.4mm TQFP
14*22mm PBGA
Order Part Number
IC61S51218T-250TQI
IC61S51218D-250TQI
IC61S51218D-250B
IC61S51218T-200TQI
IC61S51218D-200TQI
IC61S51218D-200B
IC61S51218T-166TQI
IC61S51218D-166TQI
IC61S51218D-166B
IC61S51218T-133TQI
IC61S51218D-133TQI
IC61S51218D-133B
Package
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14*20*1.4mm LQFP
14*20*1.4mm LQFP
14*22mm PBGA
14x20x1.4mm LQFP
14x20x1.4mm LQFP
14*22mm PBGA
14x20x1.4mm TQFP
14x20x1.4mm TQFP
14*22mm PBGA
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
22
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
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