GENESYS GL824 Usb 2.0 on-the-go controller Datasheet

Genesys Logic, Inc.
GL824/GL824C
USB 2.0
On-The-Go Controller
Datasheet
Revision 1.06
Nov. 07, 2006
GL824/GL824C USB 2.0 On-The-Go Controller
Copyright:
Copyright © 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be
reproduced in any form or by any means without prior written consent of Genesys Logic Inc.
Disclaimer:
ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY
KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF
GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND
CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR
EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND
NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC
BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING
FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS
MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE
MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE.
Trademarks:
is a registeredd trademark of Genesys Logic, Inc.
All trademarks are the properties of their respective owners.
Office:
Genesys Logic, Inc.
12F, No. 205, Sec. 3, Beishin Rd., Shindian City,
Taipei, Taiwan
Tel: (886-2) 8913-1888
Fax: (886-2) 6629-6168
http://www.genesyslogic.com
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 2
GL824/GL824C USB 2.0 On-The-Go Controller
Revision History
Revision
Date
Description
1.00
10/24/2005
1.01
02/24/2006
1.02
04/19/2006
1.Modify External Memory Flash Interface to ATA/ATAPI Interface
2.Change DRVVBUS pin’s description.
3.Change SDRAM Interface to SDRAM/HOST Interface
Change flash ROM to reprogrammable flash memory in page10.
1.03
06/02/2006
Modified the timing diagram of host interface
1.04
07/10/2006
Modified the timing diagram and parameter of host interface
1.05
08/15/2006
Modified the timing diagram of host interface
1.06
11/07/2006
Modified the timing diagram of host interface
First Formal Release
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 3
GL824/GL824C USB 2.0 On-The-Go Controller
TABLE OF CONTENTS
CHAPTER 1
GENERAL DESCRIPTION................................................. 9
CHAPTER 2
FEATURES ......................................................................... 10
CHAPTER 3
PIN ASSIGNMENT ............................................................ 12
3.1 PINOUT .................................................................................................. 12
3.2 PIN LIST ................................................................................................ 14
3.3 PIN DESCRIPTIONS ................................................................................ 16
CHAPTER 4
BLOCK DIAGRAM............................................................ 24
CHAPTER 5
FUNCTION DESCRIPTION ............................................. 25
5.1 OTG (ON-THE-GO) .............................................................................. 25
5.2 SIE (SERIAL INTERFACE ENGINE) ........................................................ 25
5.3 EPFIFO (ENDPOINT FIFO).................................................................. 25
5.4 SSI (SYNCHRONOUS SERIAL INTERFACE) ............................................. 25
5.4.1 One Byte Receive/Transmit Mode ............................................... 25
5.4.2 Continues Receive/Transmit Data Mode .................................... 26
5.5 UART (UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER) ........ 27
5.6 HOST INTERFACE .................................................................................. 27
CHAPTER 6
ELECTRICAL CHARACTERISTICS.............................. 31
6.1 ABSOLUTE MAXIMUM RATINGS ............................................................ 31
6.2 OPERATING CONDITIONS ...................................................................... 31
6.3 DC CHARACTERISTICS.......................................................................... 31
6.4 PMOS CHARACTERISTICS .................................................................... 32
6.5 AC CHARACTERISTICS.......................................................................... 34
6.5.1 External Flash............................................................................... 34
6.5.2 SmartMedia .................................................................................. 35
6.5.3 xD-Picture ..................................................................................... 36
6.5.4 Memory Stick ............................................................................... 37
6.5.5 Memory Stick PRO ...................................................................... 37
6.5.6 Secure Digital / MultiMedia Card ............................................... 37
6.5.7 CompactFlash Card ..................................................................... 38
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 4
GL824/GL824C USB 2.0 On-The-Go Controller
6.5.8 Reset Timing ................................................................................. 39
6.5.9 ATA/ ATAPI................................................................................. 39
6.5.10 Register Transfers ...................................................................... 41
6.5.11 Multiword DMA data transfer .................................................. 42
6.5.12 Ultra DMA data transfer ........................................................... 46
CHAPTER 7
PACKAGE DIMENSION................................................... 54
CHAPTER 8
ORDERING INFORMATION........................................... 56
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 5
GL824/GL824C USB 2.0 On-The-Go Controller
LIST OF FIGURES
FIGURE 3.1 - 208 PIN LQFP PINOUT DIAGRAM .............................................................12
FIGURE 3.2 – 128 PIN LQFP PINOUT DIAGRAM.............................................................13
FIGURE 4.1 - GL824 BLOCK DIAGRAM ..........................................................................24
FIGURE 5.1 - ONE BYTE RECEIVE/TRANSMIT TIMING DIAGRAM (CLOCK OPPOSITE)...26
FIGURE 5.2 - ONE BYTE RECEIVE/TRANSMIT TIMING DIAGRAM (CLOCK NORMAL).......26
FIGURE 5.3 - CONTINUES RECEIVE/TRANSMIT DATA TIMING DIAGRAM (CLOCK
OPPOSITE) ......................................................................................................................26
FIGURE 5.4 - CONTINUES RECEIVE/TRANSMIT DATA TIMING DIAGRAM (CLOCK
NORMAL)........................................................................................................................26
FIGURE 5.5 - DATA FRAME.............................................................................................27
FIGURE 5.6 - COMMAND WRITE TIMING DIAGRAM .......................................................28
FIGURE 5.7 - STATUS READ TIMING DIAGRAM ..............................................................28
FIGURE 5.8 - DATA WRITE TIMING DIAGRAM ...............................................................29
FIGURE 5.9 - DATA READ TIMING DIAGRAM .................................................................29
FIGURE 6.1 – EMBEDDED PMOS SWITCH ARCHITECTURE............................................32
FIGURE 6.2 – I-V CURVE OF PMOS SWTICH .................................................................33
FIGURE 6.3 – TRANSIENT ANALYSIS OF PMOS SWITCH ................................................34
FIGURE 6.4 – TIMING DIAGRAM OF EXTERNAL FLASH ..................................................34
FIGURE 6.5 - TIMING DIAGRAM OF SMARTMEDIA .........................................................35
FIGURE 6.6 - TIMING DIAGRAM OF XD-PICTURE ...........................................................36
FIGURE 6.7 - TIMING DIAGRAM OF MEMORYSTICK ......................................................37
FIGURE 6.8 - TIMING DIAGRAM OF MEMORYSTICK PRO..............................................37
FIGURE 6.9 - TIMING DIAGRAM OF SD / MMC ..............................................................37
FIGURE 6.10 - TIMING DIAGRAM OF COMPACTFLASH ...................................................38
FIGURE 6.11 - TIMING DIAGRAM OF RESET ...................................................................39
FIGURE 6.12 – REGISTER TRANSFERS TIMING ...............................................................41
FIGURE 6.13 - INITIATING A MULTIWORD DMA DATA BURST ......................................43
FIGURE 6.14 - SUSTAINING A MULTIWORD DMA DATA BURST .....................................44
FIGURE 6.15 - DEVICE TERMINATING A MULTIWORD DMA DATA BURST ....................44
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 6
GL824/GL824C USB 2.0 On-The-Go Controller
FIGURE 6.16 - HOST TERMINATING A MULTIWORD DMA DATA BURST ........................45
FIGURE 6.17 - INITIATING AN ULTRA DMA DATA-IN BURST .........................................47
FIGURE 6.18 - SUSTAINED ULTRA DMA DATA-IN BURST ..............................................47
FIGURE 6.19 - HOST PAUSING AN ULTRA DMA DATA-IN BURST ...................................48
FIGURE 6.20 - DEVICE TERMINATING AN ULTRA DMA DATA-IN BURST.......................48
FIGURE 6.21 - HOST TERMINATING AN ULTRA DMA DATA-IN BURST ..........................49
FIGURE 6.22 - INITIATING AN ULTRA DMA DATA-OUT BURST .....................................50
FIGURE 6.23 - SUSTAINED ULTRA DMA DATA-OUT BURST...........................................50
FIGURE 6.24 - DEVICE PAUSING AN ULTRA DMA DATA-OUT BURST ............................51
FIGURE 6.25 - HOST TERMINATING AN ULTRA DMA DATA-OUT BURST.........................52
FIGURE 6.26 - DEVICE TERMINATING AN ULTRA DMA DATA-OUT BURST ...................53
FIGURE 7.1 - GL824 208 PIN LQFP PACKAGE ..............................................................54
FIGURE 7.2 - GL824C 128 PIN LQFP PACKAGE............................................................55
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 7
GL824/GL824C USB 2.0 On-The-Go Controller
LIST OF TABLES
TABLE 3.1 -GL824 208 PIN LQFP PIN LIST ..................................................................14
TABLE 3.2 – GL824C 128-PIN LQFP PIN LIST ..............................................................15
TABLE 3.3 – GL824 208 PIN DESCRIPTIONS...................................................................16
TABLE 3.4 – GL824C 128 PIN DESCRIPTIONS ................................................................20
TABLE 5.1 - AC CHARACTERISTICS ...............................................................................27
TABLE 5.2 - HOST INTERFACE AC CHARACTERISTICS ..................................................29
TABLE 6.1 - ABSOLUTE MAXIMUM RATINGS .................................................................31
TABLE 6.2 - OPERATING CONDITIONS ............................................................................31
TABLE 6.3 - DC CHARACTERISTICS ...............................................................................31
TABLE 6.4 – PMOS CHARACTERISTICS .........................................................................32
TABLE 6.5 - ULTRA DMA DATA BURST TIMING REQUIREMENTS ....................................46
TABLE 8.1 - ORDERING INFORMATION...........................................................................56
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 8
GL824/GL824C USB 2.0 On-The-Go Controller
CHAPTER 1
GENERAL DESCRIPTION
The GL824/824C USB On-The-Go (OTG) Dual-Role-Device controller which include Milti-I/F and
ATA/ATAPI interface is a highly integral microprocessor, which optimized and specially designed for
embedded system, portable device, multi-function peripheral and consumer products with External uP
interface, SSI, I2C and Flash cards interface.Using the GL824, developers can create OTG-compliant
dual-role products capable of point-to-point communication. Its focus on power efficiency makes the GL824
ideal for set top box, DVD player, PDA, PMP, Digital TV and home entertainment with USB OTG and Flash
card reader.
The GL824/GL824C had USB 2.0 Multi-I/F and SD/MMC/MS/MSPro Interface Flash Card Reader
Controller. It supports USB 2.0 high-speed transmission to:
CompactFlash TM (CF) Type I/II, Micro Drive, Secure DigitalTM (SD), Mini SDTM, MultiMediaCardTM (MMC),
RS MultiMediaCardTM (RS MMC), HS-MMC, MMC-Mobile, Memory StickTM (MS), Memory Stick DuoTM
(MS Duo), High Speed Memory StickTM (HS MS), Memory Stick ProTM (MS Pro), Memory Stick ProTM Duo
(MS Pro Duo) Memory Stick ROM, SmartMediaTM (SM) 5V/3.3V, and xD-Picture Card TM (xD) on one chip
(GL824C are SD/MMC/MS/MSPro I/F only).
The GL824/GL824C also embeds a powerful 8-bit MCU engine to handle the operations among the USB host,
peripheral, OTG and ATA/ATAPI controllers. Provide flexibility Card-to-HDD, HDD-to-Card, USB-to-HDD,
HDD-to-USB, USB-to-Card and Card-to-USB multi-path copy back bridge.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 9
GL824/GL824C USB 2.0 On-The-Go Controller
CHAPTER 2
•
•
FEATURES
USB OTG Controller
-
Compliant with USB specification Rev. 2.0 at high-speed and full-speed data transfer rate
-
Compliant with On-The-Go (OTG) supplement Rev. 1.0
-
Complies with USB Storage Class specification rev. 1.0
-
Support Suspend, Resume, HNP and SRP
-
External source to drive Vbus signal
-
Supports 1 device address and up to 4 endpoints: Control (0)/ Bulk Read (1)/ Bulk Write (2)/Interrupt (3).
Integrated USB building blocks
-
USB2.0 transceiver macro (UTM), Serial Interface Engine (SIE), Build-in power-on reset (POR) and
low-voltage detector (LVD)
•
•
•
•
•
Embedded 8051 micro-controller
-
Operate @ 60 MHz clock, 1 clocks per instruction cycle
-
Embedded 64K*2 Byte reprogrammable flash memory and internal 256 byte SRAM
-
Embedded 8K Byte external SRAM
Support power saving mode
Support firmware upgrade via USB and external serial flash memory
On-Chip power MOSFETs for supplying flash media card power except Compact Flash. (GL824 only)
Interface
-
Support external SDRAM interface (option)
-
Support 16bit host interface (Support external uP Read/Write Status/Command and Read/Write FIFO)
(option)
-
Supports ATA/ATAPI interface
-
Support serial MP3 decoder interface
-
Support serial LCD Panel interface
-
Support memory cards interface
-
Support SSI interface for master and slave mode up to 15MHz
-
Support I2C interface
- Support UART interface
•
•
ATA/ATAPI interface
-
Complies with ATA/ATAPI-6 specification rev 1.0
-
Support 16-bit Multiword DMA mode and Ultra DMA mode interface (Ultra 33/66)
CompactFlashTM interface ( GL824 only )
-
Support CFA specification v2.1 / v3.0
-
Support True IDE mode
-
Support 8 / 16 bit data mode and different timing
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 10
GL824/GL824C USB 2.0 On-The-Go Controller
•
•
•
•
xD-Picture Interface (GL824 only)
-
xD-Picture specification v1.2B
-
xD-Picture Type M card support
SmartMediaTM interface ( GL824 only )
-
8 bit data width and different speed
-
Support different page size, and automatic append redundant area data (8 / 16 bytes)
MemoryStickTM / MemoryStick Pro interface
-
Compliant with MemoryStick interface specification
-
Support INS signal
-
Support automatic CRC16 generation and verification
Secure DigitalTM and MultiMediaCardTM
-
Compliant with Secure Digital / MMC interface specification
-
Supports both SD / MMC mode access CLK/CMD/DAT0/DAT1/DAT2/DAT3/DAT4/DAT5/DAT6/DAT7
- Supports SD specification v1.0 / v1.1
-
Supports MMC specification v4.0 / v4.1 x1 / x4 / x8 data transmission
-
Automatic CRC7 generation for command and CRC7 verification for response on CMD
-
Support automatic CRC16 generation and verification on DAT0:7
-
In addition to full packet transaction, optional single byte / bit operation on both CMD and DAT line / lines
- Process data in block or byte
•
•
•
High efficient hardware engine
-
Automatic data read / write with card by hardware engine
-
Easier firmware development
On board 24Mhz Crystal driver circuit
Available in 208-pin LQFP 24x24 mm package, support all card interface with external Flash/Serial
Interface for MP3 Decoder/2Pins Serial Interface LCD panel/ATA(ATAPI)/SDRAM(Host Interface)
( GL824 )
•
Available in 128-pin LQFP 14x14 mm package, Support SD/MMC/MS/MSPro card interface/Serial
Interface for MP3 Dcecoder (Only support Serial Data/Control interface in the same
pins)/ATA(ATAPI)/SDRAM(Host Interface) ( GL824C )
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 11
GPIO5
GPIO6
GPIO7
BSYNC
DREQ
DCLK
SDATA
SSICLK
SSIDI
SSIDO
CVCC
CGND
PGND
PVCC
SD_CDZ
SD_WPZ
SD_D1
SD_D0
SD_CLK
SD_CMD
SD_D3
SD_D2
GPIO1/SD_D4
GPIO2/SD_D5
GPIO3/SD_D6
GPIO4/SD_D7
MS_BS
MS_D1
MS_D0
MS_D2
MS_INS
MS_D3
MS_CLK
DRVVBUS
VDD
ID
VSS
AVSS1A
VBUS
RREF
AGND3
AVDD3
DVDD1
DGND1
GNDS
AGND1
AGND1
DP
DM
AVDD1
RVO
RVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
DQM
XD_CDZ
CAS_CS_
SM_CLE
CKO
SM_WPDZ
RAS_/RE_
SM_CDZ
CKE
CFSM_D3
SA12
CFSM_D11
SA11
CFSM_D4
BA0/WSTS
CFSM_D12
SA9
BA1/RSTS
SA8
SA10
SA0/A0
SA7
SA6
SA1
SA5
SA2
SA4
SA3
PVCC
PGND
CGND
CVCC
CFSM_D5
CFSM_D13
ARESET_
CFSM_D6
DD7
CFSM_14
DD8
CFSM_D7
DD6
CFSM_D15
DD9
CF_CS0Z
DD5
CF_CS1Z
DD10
CF_IORZ
DD4
CF_IOWZ
DD11
INTRQ
GL824/GL824C USB 2.0 On-The-Go Controller
CHAPTER 3
PIN ASSIGNMENT
3.1 Pinout
Figure 3.1 - 208 Pin LQFP Pinout Diagram
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 12
DCLK
SDATA
SSIDI
CVCC
CGND
PVCC
SD_D1
SD_D0
SD_CLK
SD_CMD
SD_D3
SD_D2
MS_BS
MS_D1
MS_D0
MS_D2
MS_INS
MS_D3
MS_CLK
DRVVBU
VDD
ID
VSS
VBUS
RREF
AGND3
AVDD3
DGND1
GNDS
DP
DM
AVDD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
DQM
CAS_/CS_
CKO
RAS_/RE_
CKE
SA12
SA11
BA0/WSTS
SA9
BA1/RSTS
SA8
SA10
SA0/A0
SA7
SA6
SA1
SA5
SA2
SA4
SA3
PVCC
CGND
CVCC
ARESET_
DD7
DD8
DD6
DD9
DD5
DD10
DD4
DD11
GL824/GL824C USB 2.0 On-The-Go Controller
Figure 3.2 – 128 Pin LQFP Pinout Diagram
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 13
GL824/GL824C USB 2.0 On-The-Go Controller
3.2 Pin List
Table 3.1 -GL824 208 Pin LQFP Pin List
Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type
1 GPIO5(ISP)
B 53 RVSS
P 105 INTRQ
I 157 NC
2 GPIO6
B 54 PGND
P 106 DD11
B 158 SM_ALE
O
3
GPIO7
B
55 X2
O
107 C_IOWZ
O
159 WE_/WE_
O/I
4
BSYNC
B
56 X1
I
108 DD4
B
160 SM_REZ
O
5
DREQ
B
57 PVCC
P
109 CF_IORZ
O
161 DQ8
B
6
DCLK
O
58 PIO1
B
110 DD10
B
162 SM_WEZ
O
7
SDATA
B
59 PIO2
B
111 CF_CS1Z
O
163 DQ7
B
8
SSICLK
B
60 PIO3
B
112 DD5
B
164 SM_RBZ
B
9
SSIDI
B
61 PIO4
B
113 CF_CS0Z
O
165 DQ9
B
10 SSIDO
B
62 TEST
I
114 DD9
B
166 SM_WPZ
B
11 CVCC
P
63 EXTRST_
I
115 CFSM_D15
B
167 DQ6
B
12 CGND
P
64 CF_CDZ
B
116 DD6
B
168 SM_D0
B
13 PGND
P
65 CS0_
O
117 CFSM_D7
B
169 DQ10
B
14 PVCC
P
66 CFSM_D10
B
118 DD8
B
170 SM_D1
B
15 SD_CDZ
B
67 DA0
O
119 CFSM_D14
B
171 DQ5
B
16 SD_WPZ
B
68 CFSM_D9
B
120 DD7
B
172 SM_D7
B
17 SD_D1
B
69 DA2
O
121 CFSM_D6
B
173 DQ11
B
18 SD_D0
B
70 CFSM_D2
B
122 ARESET_
B
174 SM_D2
B
19 SD_CLK
O
71 DA1
O
123 CFSM_D13
B
175 DQ4
B
20 SD_CMD
B
72 PMOSI1
I
124 CFSM_D5
B
176 SM_D6
B
21 SD_D3
B
73 PMOSO1
O
125 CVCC
P
177 DQ12
B
22 SD_D2
GPIO1/
23
MMC_D4
GPIO2/
24
MMC_D5
GPIO3/
25
MMC_D6
GPIO4/
26
MMC_D7
27 MS_BS
B
74 PMOSI2
I
126 CGND
P
178 SM_D3
B
B
75 PMOSO2
O
127 PGND
P
179 DQ3
B
B
76 PVCC
P
128 PVCC
P
180 SM_D5
B
B
77 PGND
P
129 SA3
O
181 DQ13
B
B
78 CGND
P
130 SA4
O
182 SM_D4
B
O
79 CVCC
P
131 SA2
O
183 DQ2
B
28 MS_D1
B
80 AINTRQ
I
132 SA5
O
184 DQ14
B
29 MS_D0
B
81 DMACK_
O
133 SA1
O
185 DQ1
B
30 MS_D2
B
82 AIORDY
I
134 SA6
O
186 DQ15
B
31 MS_INS
B
83 DIOR_
O
135 SA7
O
187 DQ0
B
32 MS_D3
B
84 DIOW_
O
136 SA0/A0
33 MS_CLK
O
85 DMARQ
I
137 SA10
O
189 CGND
P
34 DRVVBUS
O
86 CS1_
O
138 SA8
O
190 PGND
P
35 VDD
P
87 CFSM_D8
B
139 BA1/RSTS
O
191 PVCC
P
36 ID
I
88 DD15
B
140 SA9
O
192 PMOSI3
I
©2000-2006 Genesys Logic Inc. - All rights reserved.
O/I 188 CVCC
P
Page 14
GL824/GL824C USB 2.0 On-The-Go Controller
37 VSS
P
89 CFSM_D1
B
141 CFSM_D12
B
193 PMOSO3
O
38 AVSSA
P
90 DD0
B
142 BA0/WSTS
O
194 PMOSI4
I
39 VBUS
I
91 CFSM_D0
B
143 CFSM_D4
B
195 PMOSO4
O
40 RREF
B
92 DD14
B
144 SA11
O
196 RXD
B
41 AGND
P
93 CF_A0
O
145 CFSM_D11
B
197 TXD
O
42 AVDD
P
94 DD1
B
146 SA12
O
198 PIO5
B
43 DVDD
P
95 CF_A1
O
147 CFSM_D3
B
B
44 DGND
P
96 DD13
B
148 CKE
O
199 PIO6
200 PIO7
45 GNDS
P
97 CF_A2
O
149 SM_CDZ
B
B
46 AGND1
P
98 DD2
B
150 RAS_/RE_
201 PIO8
O/I 202 I2CK
B
O
47 AGND1
P
99 IORDY
I
151 SM_WPDZ
B
203 I2CD
B
48 DP
A
100 DD12
B
152 CKO
O
204 GPIO8
B
49 DM
A
101 CF_RST
B
153 SM_CLE
O
205 VSSA
P
50 AVDD
P
102 DD3
B
154 CAS_/CS_
O/I 206 VSEL
I
51 RVO
O
103 NC
-
155 XD_CDZ
B
207 VBAT
I
52 RVDD
I
104 NC
-
156 DQM
O
208 VDDA
P
Table 3.2 – GL824C 128-Pin LQFP Pin List
Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type
1 DCLK
O 33 RVO
O 65 DD11
B 97 WE
O/I
2
SDATA
B
34 RVDD
I
66 DD4
B
3
SSIDI
B
35 RVSS
P
67 DD10
B
4
CVCC
P
36 X2
O
68 DD5
B
5
CGND
P
37 X1
I
69 DD9
B
6
PVCC
P
38 PVCC
P
70 DD6
B
7
SD_D1
B
39 PIO1
B
71 DD8
B
8
SD_D0
B
40 PIO2
B
72 DD7
B
9
SD_CLK
O
41 TEST
I
73 ARESET_
O
98 DQ8
99 DQ7
B
100 DQ9
101 DQ6
B
102 DQ10
103 DQ5
B
104 DQ11
105 DQ4
B
B
B
B
B
B
10 SD_CMD
B
42 EXTRST_
I
74 CVCC
P
11 SD_D3
B
43 CS0
O
75 CGND
P
106 DQ12
107 DQ3
12 SD_D2
B
44 DA0
O
76 PVCC
P
108 DQ13
B
13 MS_BS
O
45 DA2
O
77 SA3
O
109 DQ2
B
14 MS_D1
B
46 DA1
O
78 SA4
O
110 DQ14
B
15 MS_D0
B
47 PVCC
P
79 SA2
O
111 DQ1
B
16 MS_D2
B
48 PGND
P
80 SA5
O
112 DQ15
B
17 MS_INS
B
49 CVCC
P
81 SA1
O
113 DQ0
B
18 MS_D3
B
50 AINTRQ
I
82 SA6
O
114 CVCC
P
19 MS_CLK
O
51 DMACK_
O
83 SA7
O
115 CGND
P
20 DRVVBUS
O
52 AIORDY
I
84 SA0/A0
21 VDD
P
53 DIOR_
O
85 SA10
©2000-2006 Genesys Logic Inc. - All rights reserved.
O/I 116 PVCC
O
117 RXD
B
P
B
Page 15
GL824/GL824C USB 2.0 On-The-Go Controller
22 ID
I
54 DIOW_
O
86 SA8
O
118 TXD
O
23 VSS
P
55 DMARQ
I
87 BA1/RSTS
O
119 PIO5
B
24 VBUS
I
56 CS1
O
88 SA9
O
120 I2CK
O
25 RREF
B
57 DD15
B
89 BA0/WSTS
O
121 I2CD
B
26 AGND3
P
58 DD0
B
90 SA11
O
122 GPIO8
B
27 AVDD3
P
59 DD14
B
91 SA12
O
123 VSSA
P
28 DGND1
P
60 DD1
B
92 CKE
O
124 VSEL
I
29 AGND1
P
61 DD13
B
93 RAS_/RE_
O/I 125 VBAT
I
30 DP
B
62 DD2
B
94 CKO
31 DM
B
63 DD12
B
95 CAS_/CS_
32 AVDD1
P
64 DD3
B
96 DQM
O
126 VDDA
O/I 127 BSYNC
O
128 DREQ
P
B
B
3.3 Pin Descriptions
Table 3.3 – GL824 208 Pin Descriptions
USB Interface
Pin Name
GPIO5(ISP)
1
GPIO6
2
GPIO7
3
BYYNC
4
DREQ
5
DCLK
6
SDATA
7
SSICLK
8
SSIDI
9
SSIDO
10
DRVVBUS
34
Type
B
(pu)
B
(pu)
B
(pu)
B
(pd)
B
(pd)
O
(pd)
B
(pd)
B
(pd)
B
(pd)
B
(pd)
O
ID
36
I
ID
VBUS
39
I
VBUS
RREF
40
B
Reference resistor
DP
48
B
USB D+
DM
49
58~61,
198~201
B
B
(pd)
I
(pd)
USB D-
PIO1~8
Test
Pin#
62
Description
General Purpose I/O 5 (In System Programming)
General Purpose I/O 6
General Purpose I/O 7
Byte synchronization signal (for MP3 decoder I/F)
Data request input (for MP3 decoder I/F)
Serial output data bus clock (for MP3 decoder I/F)
Serial output data (for MP3 decoder I/F)
Synchronous Serial Clock Output
Synchronous Serial data input
Synchronous Serial data output
Drive VBUS on control output pin
Programmable I/O #1~#8
Test pin
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 16
GL824/GL824C USB 2.0 On-The-Go Controller
EXTRST_
63
RXD
196
TXD
197
I2CK
202
I2CD
203
VSEL
206
I
(pd)
B
(pu)
O
(pu)
O
(pu)
B
(pu)
I
VBAT
207
I
External reset
UART receives data input
UART transmits data output
I2C bus clock
I2C data
Key voltage detection input
Battery voltage detection input
ATA/ATAPI Interface
Pin Name
Pin#
Type
CS0_
65
O
PESETZ (PCVS2Z)
CS1_
86
O
PESETZ (PCVS1Z)
67,71,69
O
I
(pd)
O
I
(pu)
O
DA0~2
AINTRQ
80
DMACK_
81
AIORDY
82
DIOR_
83
DIOW_
84
DMARQ
85
O
I
(pd)
Description
Address 0~2
IREQZ
DMACK
IORDY (WAITZ)
I/O read strobe
I/O write strobe
DMARQ
90,94,98,102,
DD0~15
ARESET_
108,112,116,
120,118,114,
110,106,100,
B
(pd)
Data 0~15
96,92,88
122
O
ARESET
SDRAM/Host Interface
Pin Name
SA1~12
Pin#
133,131,129,
130,132,134,
135,138,140,
137,144,146
Type
O
O/I
(pd)
SA0/A0
136
BA0/WSTS
142
BA1/RSTS
139
O
CKE
148
RAS_/RE_
150
O
O/I
(pu)
Description
SDRAM_A1~A12
SDRAM_A0 / share pin with A0 pin of HOST interface
SDRAM_BA0 / share pin with write status pin of HOST
interface
SDRAM_BA1 / share pin with read status pin of HOST
interface
SDRAM_CKE
SDRAM_RAS / share pin with read enable pin of HOST
interface
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 17
GL824/GL824C USB 2.0 On-The-Go Controller
CKO
152
CAS_/CS_
154
DQM
156
WE_/WE_
159
DQ0~15
187,185,183,
179,175,171,
167,163,161,
165,169,173,
177,181,184,
O
O/I
(pu)
O
O/I
(pu)
Clock
SDRAM_CAS / Share pin with chip select pin of HOST
interface
SDRAM_UDQM
Write enable / Share pin with write enable pin of HOST
interface
B
(pd)
SDRAM_D0~D15 / Share pin with Data0~15 bus of HOST
interface
186
CompactFlash / MicroDrive Interface
Pin Name
CF_CDZ
Pin#
64
Type
B
(pu)
Description
Card detection
91,89,70,147,
143,124,121,
CFSM_D0~15
117,87,68,
66,145,141,
123,119,115
93,95,97
B
(pd)
Data bus 0~15
IORDY
99
CF_RST
101
INTRQ
105
CF_IOWZ
107
O
I
(pu)
B
(pd)
I
(pd)
O
CF_IORZ
109
O
I/O read strobe
CF_CS1Z
111
O
CS1Z
CF_CS0Z
113
O
CS0Z
CF_A0~2
Address 0~2
I/O read stobe
Reset
INTRQ
I/O write strobe
SmartMeia / xD-Picture Card / NAND Flash Memory Interface
Pin Name
Pin#
SM_CDZ
149
SM_WPDZ
151
SM_CLE
153
XD_CDZ
155
SM_ALE
158
Type
B
(pu)
B
(pu)
O
B
(pu)
O
Description
SM_REZ
160
O
Read enable
SM_WEZ
162
Write enable
SM_RBZ
164
O
B
(pu)
Card detection
Write Protect Detect
Command latch enable
Card detection
Address latch enable
Read/Busy
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 18
GL824/GL824C USB 2.0 On-The-Go Controller
SM_WPZ
166
SM_D0~7
168,170,174,
178,182,180,
176,172
B
(pu)
Write Protect Detect
B
(pd)
Address 0~7
SecureDigital / MultiMediaCard Interface
Pin Name
Pin#
SD_CDZ
15
SD_WPZ
16
SD_D0~3
MMC_D4~7
SD_CLK
SD_CMD
18,17,22,21,
23~26
19
20
Type
B
(pu)
B
(pu)
B
(pu)
O
B
(pu)
Description
Card detection#
Write Protect Detection
Data 0~7
SD/MMC clock
SD/MMC command and response
Memory Stick Pro / Memory Stick Interface
Pin Name
MS_BS
MS_D0~3
Pin#
Type
27
O
B
(pd)
B
(pu)
O
29,28,30,32
MS_INS
31
MS_CLK
33
Description
Bus state
Data 0~3
Card detection
Clock
Miscellaneous Interface
Pin Name
GPIO1~8
NC
Pin#
23~26,1~3,
204
103,104,157
Type
B
(pu)
-
Description
General Purpose I/O #1~#8
No connection
Power / Ground
Pin Name
Type
VDD
Pin#
11,79,125,
188
12,78,126,
189
13,77,127,
190
14,76,128,
191
35
VSS
CVCC
Description
P
Core power 2.5V
P
Core Ground
P
Pad ground
P
Pad power 3.3V
P
Digital circuit power 2.5V
37
P
Digital circuit ground
AVSSA
38
P
AVSSA
AGND
41
P
Analog ground #3
CGND
PGND
PVCC
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 19
GL824/GL824C USB 2.0 On-The-Go Controller
AVDD
42
P
Analog power#3
DVDD
43
P
Digital power #1
DGND
44
P
Digital ground #1
GNDS
45
P
Ground
AGND
46
P
Analog ground #1
AGND
47
P
Analog ground #1
AVDD
50
P
Analog power
RVO
51
P
2.5V regulator output
RVDD
52
P
2.5V regulator power
RVSS
53
P
2.5V regulator ground
PGND
54
P
24MHz crystal ground
X2
55
P
24MHz crystal output
X1
56
P
24MHz crystal input
P
24MHz crystal power 3.3V
I
PMOS #1~#4 input 3.3V
O
PMOS #1~#4 output 3.3V
VSSA
57
72,74,192,
194
73,75,,193,
195
205
P
ADC ground
VDDA
208
P
ADC 3.3V power
PVCC
PMOSI1~4
PMOSO1~4
Table 3.4 – GL824C 128 Pin Descriptions
USB Interface
Pin Name
Pin#
BYYNC
127
DREQ
128
DCLK
1
SDATA
2
SSIDI
3
DRVVBUS
20
Type
B
(pd)
B
(pd)
O
(pd)
B
(pd)
B
(pd)
O
Description
ID
22
I
ID
VBUS
24
I
VBUS
RREF
25
B
Reference resistor
DP
30
B
USB D+
DM
31
USB D-
PIO1
39
Test
41
B
B
(pd)
I
(pd)
Byte synchronization signal (for MP3 decoder I/F)
Data request input (for MP3 decoder I/F)
Serial output data bus clock (for MP3 decoder I/F)
Serial output data (for MP3 decoder I/F)
Synchronous Serial data input
Drive VBUS on control output pin
Programmable I/O #1
Test pin
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 20
GL824/GL824C USB 2.0 On-The-Go Controller
EXTRST_
42
RXD
117
TXD
118
I2CK
120
I2CD
121
VSEL
124
I
(pd)
B
(pu)
O
(pu)
O
(pu)
B
(pu)
I
VBAT
125
I
External reset
UART receives data input
UART transmits data output
I2C bus clock
I2C data
Key voltage detection input
Battery voltage detection input
ATA/ATAPI Interface
Pin Name
Pin#
Type
CS0_
43
O
PESETZ (PCVS2Z)
CS1_
56
O
PESETZ (PCVS1Z)
44,46,45
O
I
(pd)
O
I
(pu)
O
DA0~2
AINTRQ
50
DMACK_
51
AIORDY
52
DIOR_
53
DIOW_
54
DMARQ
55
O
I
(pd)
Description
Address 0~2
IREQZ
DMACK
IORDY (WAITZ)
I/O read strobe
I/O write strobe
DMARQ
58,60,62,64,
DD0~15
ARESET_
66,68,70,
72,71,69,
67,65,63,
B
(pd)
Data 0~15
61,59,57
73
O
ARESET
SDRAM Interface
Pin Name
SA1~12
Pin#
81,79,77,
78,80,82,
83,86,88,
85,90,91
Type
O
O/I
(pd)
SA0/A0
84
BA0/WSTS
89
BA1/RSTS
87
O
CKE
92
RAS_/RE_
93
O
O/I
(pu)
Description
SDRAM_A1~A12
SDRAM_A0 / share pin with A0 pin of HOST interface
SDRAM_BA0 / share pin with write status pin of HOST
interface
SDRAM_BA1 / share pin with read status pin of HOST
interface
SDRAM_CKE
SDRAM_RAS / share pin with read enable pin of HOST
interface
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 21
GL824/GL824C USB 2.0 On-The-Go Controller
CKO
94
CAS_/CS_
95
DQM
96
WE_/WE_
97
DQ0~15
113,111,109,
107,105,103,
101,99,98,
100,102,104,
106,108,110,
O
O/I
(pu)
O
O/I
(pu)
Clock
SDRAM_CAS / Share pin with chip select pin of HOST
interface
SDRAM_UDQM
Write enable / Share pin with write enable pin of HOST
interface
B
(pd)
SDRAM_D0~D15 / Share pin with Data0~15 bus of HOST
interface
112
SecureDigital / MultiMediaCard Interface
Pin Name
Pin#
SD_CDZ
119
SD_WPZ
40
SD_D0~3
8,7,12,11,
SD_CLK
9
SD_CMD
10
Type
B
(pu)
B
(pu)
B
(pu)
O
B
(pu)
Description
Card detection#
Write Protect Detection
Data 0~3
SD/MMC clock
SD/MMC command and response
Memory Stick Pro / Memory Stick Interface
Pin Name
MS_BS
MS_D0~3
Pin#
Type
13
O
B
(pd)
B
(pu)
O
15,14,13,18
MS_INS
17
MS_CLK
19
Description
Bus state
Data 0~3
Card detection
Clock
Miscellaneous Interface
Pin Name
GPIO8
Pin#
122
Type
B
(pu)
Description
General Purpose I/O #8
Power / Ground
Pin Name
CVCC
CGND
PVCC
VDD
Pin#
4,49,74,
114
5,48,75,
115
6,47,76,
116
21
Type
Description
P
Core power 2.5V
P
Core Ground
P
Pad power 3.3V
P
Digital circuit power 2.5V
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 22
GL824/GL824C USB 2.0 On-The-Go Controller
VSS
23
P
Digital circuit ground
AGND
26
P
Analog ground #3
AVDD
27
P
Analog power#3
DGND
28
P
Digital ground #1
GNDS
29
P
Ground
AVDD
32
P
Analog power
RVO
33
P
2.5V regulator output
RVDD
34
P
2.5V regulator power
RVSS
35
P
2.5V regulator ground
X2
36
P
24MHz crystal output
X1
37
P
24MHz crystal input
PVCC
38
P
24MHz crystal power 3.3V
VSSA
123
P
ADC ground
VDDA
126
P
ADC 3.3V power
Notation:
Type
O
I
B
B/I
B/O
P
A
pu
pd
odpu
Output
Input
Bi-directional
Bi-directional, default input
Bi-directional, default output
Power / Ground
Analog
Internal pull up
Internal pull down
Open drain with internal pull up
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 23
GL824/GL824C USB 2.0 On-The-Go Controller
CHAPTER 4
DP
DM
BLOCK DIAGRAM
OTG
Physical/Logic
Controller
ATAPI
Interface
SIE
SDRAM
Interface
MCU
8051
/RST
VCC
PLL
60 MHz
Reset
Internal
Reset
Voltage
Regulator
Internal
Power
EPFIFO
HOST
Interface
UART
Interface
Flash Cards
Interface
RAM
Flash
ROM
I2C
Interface
ATAPI
Interface
16- bit bus
Share Pin
Interface
Flash
Cards
Interface
SSI
Interface
Figure 4.1 - GL824 Block Diagram
Figure 4.2 - GL824 System Block Diagram
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 24
GL824/GL824C USB 2.0 On-The-Go Controller
CHAPTER 5
FUNCTION DESCRIPTION
5.1 OTG (On-The-Go)
A dual-role OTG device that has the following features and characteristics:
•Liminted Hos capability
•High/Full-speed operation as peripheral
•High/Full-speed support as host
•Targeted Peripheral List
•Session Request Protocol
•Host Negotiation Protocol
•One Mini-AB receptacle
•Minimum 8mA output on VBUS
5.2 SIE (Serial Interface Engine)
The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing
and state machine logic to habdle USB packets and transactions.
5.3 EPFIFO (Endpoint FIFO)
Endpoint FIFO includes Control FIFO (FIFO0), Interrupt FIFO (FIFO3) and Bulk In/Out FIFO (BULKFIFO).
•Control FIFO
FIFO of control endpoint 0.
It is 64-bytes FIFO, and it is used for endpoint 0 data transfer.
64-bytes depth FIFO of endpoint 3 for status interrupt.
•Interrupt FIFO
•Bulk In/Out FIFO It can be in the TX mode or RX mode:
a. It contains ping-pong FIFO (512 bytes each bank) for transmit/receive data
continuously.
b. It can be directly accessed by Uc.
c. Support automatic hardware SmartMedia ECC error correction.
5.4 SSI (Synchronous Serial Interface)
The Synchronous Serial Interface provides serial data in and out for communication with serial fingerprint
sensor The SSI uses following pins: SSICLK, SSIDO and SSIDI.
SSICLK:
SSIDO:
SSIDI:
Synchronous Serial Interface Clock
Synchronous Serial Interface Data Output
Synchronous Serial Interface Data Input
5.4.1 One Byte Receive/Transmit Mode
GL824 provides a programmable synchronous serial interface. The SSI not only supports both clock normal
and clock opposite phases but also supports MSB or LSB data formats. One Byte Receive/Transmit timing
diagram see Figure 5.1 ~ Figure 5.2. User can read/write register/command from/to fingerprint sensor in this mode.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 25
GL824/GL824C USB 2.0 On-The-Go Controller
Figure 5.1 - One Byte Receive/Transmit Timing Diagram (Clock Opposite)
tWL
SSICLK
SSIDO
SSIDI
D7
D7
tWH
D6
D6
D5
D5
tSU
D4
D4
D3
D3
tH
D2
D2
D1
D1
D0
D0
tV
Figure 5.2 - One Byte Receive/Transmit timing diagram (clock normal)
5.4.2 Continues Receive/Transmit Data Mode
For fingerprint sensor application, GL824 gets image row/column data by continues receive mode. Figure 5.3
shows the data receive timing diagram. The SSICLK clock rate can be configured by DIV register.
Figure 5.3 - Continues Receive/Transmit Data timing diagram (clock opposite)
Figure 5.4 - Continues Receive/Transmit Data timing diagram (clock normal)
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 26
GL824/GL824C USB 2.0 On-The-Go Controller
Table 5.1 - AC Characteristics
Symbol
Parameter
Min.
Max.
Unit
tWL
Clock Low Time
35
-
ns
tWH
Clock High Time
35
-
ns
tSU
Data Setup Time
1/2 * tWL
-
ns
tH
Data Hold Time
3/4 * tWL
-
ns
tV
Data Valid Time
1/4 * tWL
-
ns
5.5 UART (Universal Asynchronous Receiver/Transmitter)
GL824 has three 16-bit timers/counters that are same as the timer of the standard 8052 family up to 921.6Kbps.
The serial port has three asynchronous modes of operation. For fingerprint sensor application, the data frame
consists of 10 bits: one start bit, eight data bits and one stop bit. Serial data is transmitted on the TxD pin and
received on the RxD pin. The data frame shows in Figure 5.5.
D0
D1
D2
D3
D4
D5
D6
D7
D8
Data Byte
Start Bit
Stop Bit
Ninth Data Bit (Modes 2 and 3 only)
Figure 5.5 - Data Frame
5.6 Host Interface
l Pin Description
/CS: Chip Select and active low.
A0: Command/Status and Data select. When A0 is high, GL824 is operation at Command Write and
Status Read mode. When A0 is low, GL824 is operation at continues data receive/transfer mode.
/RE: Read Enable; Active low. GL824 read frequency must lower than 30 MHz.
/WE: Write Enable; Active low. Write frequency must lower than 30 MHz.
Data[0:15]: 16 bit Data bus
WSTS: Command/Data Write Status. When WSTS is high, it indicated that GL824 is ready for HOST
write command/data.
RSTS: Command/Data Read Status. When RSTS is high, it indicated that GL824 is ready for HOST
read data/status.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 27
GL824/GL824C USB 2.0 On-The-Go Controller
l Command Write
Command, address and data are all written through Data[0:15] port by bring /WE to low, while A0 is high
and WSTS also pull high, it indicated that GL824 is ready for HOST write command. When /CS is low,
command is latched on the rising edge of /WE. When WSTS goes low it indicates that Command is latched
into command register by GL824.
Figure 5.6 - Command Write Timing Diagram
l Status Read
Register status, address and data can be read through Data[0:15] port by bring RE to low, while A0 is high
and RSTS also return high, it indicated that GL824 is ready for HOST read status. When /CS is low.
Register status latched on the rising edge of /RE. After status read operation is finished, RSTS is low.
t CRH
tSC tCR
/ CS
A0
/WE
tRL
/RE
Status
Data[0: 15]
tD
t rH
RSTS
Figure 5.7 - Status Read Timing Diagram
l Data Write
External HOST pull A0 low, while WSTS active high, it indicated that Data Buffer Memory is ready to be
written by external microprocessor through Data[0:15] port. HOST continues write 256 words data by bring
/CS is low. Data is latched on the rising edge of /WE. The GL824 Data Buffer Memory Address Pointer is
increased automatically. After data continues write operation is finished and latched into Data Buffer
Memory, WSTS will drive low. When GL824 Data Buffer Memory is ready for HOST write data, WSTS return
to high.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 28
GL824/GL824C USB 2.0 On-The-Go Controller
Figure 5.8 - Data Write Timing Diagram
l Data Read
External HOST pull A0 low, while RSTS active high, it indicated that Data Buffer Memory is ready to be
read by external microprocessor through Data[0:15] port. HOST continues read 256 words data by bring
/CS is low. Data is latched on the rising edge of /RE. The GL824 Data Buffer Memory Address Pointer is
increased automatically. After data continues read operation is finished, RSTS is low. When GL824 Data
Buffer Memory is ready for HOST read data, RSTS return to high.
Figure 5.9 - Data Read Timing Diagram
Table 5.2 - Host Interface AC Characteristics
Symbol
Min.
Max.
Unit
Chip Select Low to Write Enable Low delay time
5
-
ns
Chip Select High for Write Enable High delay time
5
-
ns
tSC
A0 High to Write Enable Low delay time
5
-
ns
tWL
Write Enable Low time
20
-
ns
tSU
Data Setup Time for /WE signal
20
-
ns
tH
Data Hold Time for /WE signal
5
-
ns
tRL
Read Enable Low time
20
-
ns
Write Enable clock cycle time
40
-
ns
tEH
Write Pulse High width
20
-
ns
tEL
Write pulse Low width
20
-
ns
tCR
Chip Select Low to Read Enable Low delay time
5
-
ns
Chip Select High for Read Enable High delay time
5
-
ns
Command/Data read hold time for enable signal
-
5
ns
tCW
tCWH
tCYC
tCRH
trH
Parameter
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 29
GL824/GL824C USB 2.0 On-The-Go Controller
tD
Data ready for command/Data read
©2000-2006 Genesys Logic Inc. - All rights reserved.
5
-
ns
Page 30
GL824/GL824C USB 2.0 On-The-Go Controller
CHAPTER 6
ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings
Table 6.1 - Absolute Maximum Ratings
Parameter
Value
Storage Temperature
-65°C to +150 °C
Ambient Temperature
-40°C to +80 °C
Supply Voltage to Ground Potential
-0.5V to +4.0V
DC Input Voltage to Any Pin
-0.5V to +5.8V
6.2 Operating Conditions
Table 6.2 - Operating Conditions
Parameter
Value
Ta (Ambient Temperature Under Bias)
0°C to 70°C
Supply Voltage
+3.0V to +3.6V
Ground Voltage
0V
FOSC (Oscillator or Crystal Frequency)
24 MHz ± 0.25%
6.3 DC Characteristics
Table 6.3 - DC Characteristics
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
3.0
-
3.6
V
VIH
Input High Voltage
2.6
-
5
V
VIL
Input Low Voltage
0
-
0.7
V
-5
-
5
µA
II
Input Leakage current
0 < VIN < VCC
VOH
Output High Voltage
3.0
-
-
V
VOL
Output Low Voltage
-
-
0.2
V
IOH
Output Current High
VDD=3.3V VOH=2.6V
-
8
-
mA
IOL
Output Current Low
VDD=3.3V VOL=0.8V
-
8
-
mA
CIN
Input Pin Capacitance
-
5
-
pF
ISUSP
Suspend current
-
-
500
µA
ICC
Supply current
-
-
100
mA
1.5K external pull-up
included
Connect to USB with 8051
operating
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 31
GL824/GL824C USB 2.0 On-The-Go Controller
6.4 PMOS Characteristics
Table 6.4 – PMOS Characteristics
(Core Power=2.5V, IO Power=3.3V)
TT (25oC)
SS (80oC)
FF (0oC)
Driving Strength
124.4
102.5
140.5
Turn-On Slew Rate (V/uS)
0.256
0.175
0.2560.321
On-Resistance (ohm)
1.61
1.95
1.611.42
Simulation Results
Note:
1.
Driving strength is defined as the PMOS sinking current when Vio=3.3V, Vd=3.1V.
2.
Turn-on slew rate is defined as the falling speed of PMOS’s gate voltage from 3.2V to 0.2V.
3.
On-resistance is calculated by 0.2V divided by driving strength.
Figure 6.1 – Embedded PMOS Switch Architecture
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 32
GL824/GL824C USB 2.0 On-The-Go Controller
Figure 6.2 – I-V Curve of PMOS Swtich
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 33
GL824/GL824C USB 2.0 On-The-Go Controller
Figure 6.3 – Transient Analysis of PMOS Switch
6.5 AC Characteristics
6.5.1 External Flash
NVMA[0..15]
NVMOE#
NVMWE#
NVMD[0..7]
dddddxdddddddddddddddxddddd
\\\\\;\\\\\\\\\\\\\\@’\\\\\
Twc
lllllrhhhhhhhhhhhhhhhflllll
\\\\\;\\\@;\\\\\@’\\\;\\@’\
Tow
Tww
Tra
hhhhhhhhhhfllllllrhhhhhhhhh
dddddxddddxddddddddddxdddxd
Figure 6.4 – Timing Diagram of External Flash
Parameter
Description
Min
Typ
Max
TWC
Write data cycle time
-
102.5
-
TWW
Write pulse width
-
41.6
-
TOW
OE# to WE# time
-
38.6
-
TRA
Read Access time
-
-
90
©2000-2006 Genesys Logic Inc. - All rights reserved.
Unit
ns
Page 34
GL824/GL824C USB 2.0 On-The-Go Controller
6.5.2 SmartMedia
Read
RE#
D[0..7]
\\\\\;\\\\\\\\\\\\\@;\\\\\@’
Tcr
Trw
hhhhhfllllllrhhhhhhhfllllllr
Tds
Tdh
\\\\\\\\;\\@;\@’\\\\\\\\\\\\
zzzzzzzznddddddozzzzzzzznddd
Write
CLE
ALE
WE#
D[0..7]
lrhhhhflllllllllllllllllllll
\;\\\@’\\\\\\\\\\\\\;\\\\@’\
Tcw
lllllllllrhhhhhhhfllllllllll
TwwT
\\\\\\\\\\\\\\\\\\\\;\@’\\\\
hhhhhhhhhhhhhhhhhhhhfllrhhfl
Tdp
Tcd Tdw
Tai Tdw
Tdd
Tad
\;@;@’\\\;@’;@;@’\\\\;@;@’\\
zzzndozzzzndozndozzzzndddozn
Figure 6.5 - Timing Diagram of SmartMedia
Parameter
Tcw
Description
CLE active width
Mode
Min
Typ
Max
Normal
-
165
-
Slow
-
198
-
Normal
-
100
-
Slow
-
166
-
Normal
-
66
-
Slow
-
100
-
-
-
33.3
-
Normal
-
67
-
Slow
-
100
-
Twc
Write data cycle time
Tww
Write pulse width
Tcd
CLE-to-command delay
Tdw
Data width
Tad
ALE-to-address delay
-
-
33.3
-
Tai
Address data interval time
-
-
33.3
-
Tdp
Data pre-output delay
-
-
33.3
-
Tdd
Data delay time
-
-
33.3
-
Tcr
Read data cycle time
Normal
-
133.3
-
Slow
-
166.6
-
Trw
Read pulse width
-
-
100
-
Tds
Data setup time
-
-
40
-
Tdh
Data hold time
-
-
20
-
©2000-2006 Genesys Logic Inc. - All rights reserved.
Unit
ns
Page 35
GL824/GL824C USB 2.0 On-The-Go Controller
6.5.3 xD-Picture
Read
RE#
D[0..7]
\\\\\;\\\\\\\\\\\\\@;\\\\\@’
Tcr
Trw
hhhhhfllllllrhhhhhhhfllllllr
Tds
Tdh
\\\\\\\\;\\@;\@’\\\\\\\\\\\\
zzzzzzzznddddddozzzzzzzznddd
Write
CLE
ALE
WE#
D[0..7]
lrhhhhflllllllllllllllllllll
\;\\\@’\\\\\\\\\\\\\;\\\\@’\
Tcw
lllllllllrhhhhhhhfllllllllll
TwwT
\\\\\\\\\\\\\\\\\\\\;\@’\\\\
hhhhhhhhhhhhhhhhhhhhfllrhhfl
Tdp
Tcd Tdw
Tai Tdw
Tdd
Tad
\;@;@’\\\;@’;@;@’\\\\;@;@’\\
zzzndozzzzndozndozzzzndddozn
Figure 6.6 - Timing Diagram of xD-Picture
Parameter
Tcw
Description
CLE active width
Mode
Min
Typ
Normal
165
Slow
198
Normal
100
Slow
166
Normal
66
Slow
100
Twc
Write data cycle time
Tww
Write pulse width
Tcd
CLE-to-command delay
Tdw
Data width
Tad
ALE-to-address delay
33.3
Tai
Address data interval time
33.3
Tdp
Data pre-output delay
33.3
Tdd
Data delay time
33.3
Tcr
Read data cycle time
Trw
Read pulse width
100
Tds
Data setup time
40
Tdh
Data hold time
20
©2000-2006 Genesys Logic Inc. - All rights reserved.
Max
Unit
33.3
Normal
67
Slow
100
Normal
133.3
Slow
166.6
ns
Page 36
GL824/GL824C USB 2.0 On-The-Go Controller
6.5.4 Memory Stick
llrhhhhhhhhhhhhhhhfllllllllll
lllrfrfrfrfrfrfrfrfrfrfrfrfrf
ddddxdddddddddddddddxdddddddd
BS
SCLK
SDIO
Figure 6.7 - Timing Diagram of MemoryStick
Parameter
Fck
Description
SCLK frequency
Mode
Typ
0
1.5M
1
6M
2
15M
3
20M
Unit
Remark
Hz
6.5.5 Memory Stick PRO
llrhhhhhhhhhhhhhhhfllllllllll
lllrfrfrfrfrfrfrfrfrfrfrfrfrf
dddxdxdxdxdxdxdxdxdxdxdxdxdxd
BS
SCLK
DATA
Figure 6.8 - Timing Diagram of MemoryStick PRO
Parameter
Fck
Description
SCLK frequency
Mode
Typ
0
30M
1
40M
Unit
Remark
Hz
6.5.6 Secure Digital / MultiMedia Card
CMD
CLK
DAT
dddxdxdxdddddddddddddddddxdddd
rfrfrfrfrfrfrfrfrfrfrfrfrfrfrf
dddddddddddddxdddddddddddxdddd
Figure 6.9 - Timing Diagram of SD / MMC
Parameter
Fck
Description
CLK frequency
©2000-2006 Genesys Logic Inc. - All rights reserved.
Mode
Typ
0
375K
1
6M
2
15M
3
24M
4
48M
Unit
Remark
Hz
Page 37
GL824/GL824C USB 2.0 On-The-Go Controller
6.5.7 CompactFlash Card
\\\;\\\\\\\\\\@;\\\\@’\\\\
IOR-/IOWhhhflllllrhhhhhflllllrhhhh
Td
Thw
\\\;@’\\\;@’\\\\\\\\\\\\\\
WRITE DD[15:0] zzzzzndddddozzzzzndddddozz
Tsu Thr
\\\\\\\;@;@’\\\\\\\\\\\\\\
READ DD[15:0] zzzzzzzndddozzzzzzzndddozz
Figure 6.10 - Timing Diagram of CompactFlash
Parameter
Tcyc
Description
Read/Write Cycle Time
Tw
Read/Write Active Width
Td
Delay Time for Write Data
Thw
Data Hold Time following IOW-
Tsu
Data Setup Time before IOR-
©2000-2006 Genesys Logic Inc. - All rights reserved.
Mode
Min
Typ
Max
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
600
383
240
180
120
100
80
165
125
100
80
70
65
55
0
0
0
0
0
0
0
30
20
15
10
10
5
5
50
35
20
20
-
-
Unit
ns
Page 38
GL824/GL824C USB 2.0 On-The-Go Controller
Thr
4
5
6
0
1
2
3
4
5
6
Data Hold Time following IOR-
20
15
10
5
5
5
5
5
5
5
-
-
6.5.8 Reset Timing
Trst
Extrstz
Figure 6.11 - Timing Diagram of Reset
Parameter
Description
Minimum
Unit
Trst
This active low signal is used by the system
to reset the chip; the active low pulse should
be at least 1us wide.
1
us
Remark
6.5.9 ATA/ ATAPI
The GL824 complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes:
1.
DMA (Direct Memory Access) data transfer:
DMA data transfer means of data transfer between device and host memory without host processor
intervention.
- Multiword DMA: Multiword DMA is a data transfer protocol used with the READ DMA, WRITE
DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When a
Multiword DMA transfer is enabled as indicated by IDENTIFY DEVICE or IDENTIFY PACKET
DEVICE data, this data transfer protocol shall be used for the data transfers associated with these
commends. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.)
- Ultra DMA: Ultra DMA Is a data transfer protocol used with the READ DMA, WRITE DMA,
READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When this protocol is
enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these
commands are issued by the host. This protocol applies to the Ultra DMA data burst only. (Please
refer to the ATA / ATAPI-6 specification rev 1.0 for more information.)
Following listed the symbols and their respective definitions that are used in the timing diagram:
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 39
GL824/GL824C USB 2.0 On-The-Go Controller
-
Signal transition (asserted or negated)
-
Data transition (asserted or negated)
-
Data valid
-
Undefined but not necessarily released
-
Asserted, negated or released
-
Released
-
The “other” condition if a signal is shown with no change
All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown
towards the bottom of the page relative to the asserted condition.
The interface uses a mixture of negative and positive signals for control and data. The terms asserted and
negated are used for consistency and are independent of electrical characteristics.
In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following
illustrates the representation of a signal named Test going from negated to asserted and back to negated, based
on the polarity of the signal.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 40
GL824/GL824C USB 2.0 On-The-Go Controller
6.5.10 Register Transfers
Figure 6.12 – Register Transfers Timing
Notes:
1. Device address consists of signals CS0_, CS1_ and DA(2:0).
2. Data consists of IODD(7:0).
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of
whether the cycle is to be extended is made by the host after tA from the assertion of DIOR_ or DIOW_.
The assertion and negation of IORDY are described as following:
3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3.2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released
prior to negation and may be asserted for no more than 5 ns before release: no wait generated.
3.3 Device negates IORDY before tA, IORDY is released prior to negation and may be asserted for no
more than 5 ns before release: wait generated. The cycle completes after IORDY is released. For
cycles where a wait is generated and DIOR_ is asserted, the device shall read data on IODD(0:7) for
tRD before asserting IORDY.
4. DMACK_ shall remain negated during a register transfer.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 41
GL824/GL824C USB 2.0 On-The-Go Controller
Register transfer timing parameters
Timing (ns)
t0
Cycle time
2000
t1
Address valid to DIOR_/ DIOW_ setup
1000
t2
DIOR_/ DIOW_ pulse width 8-bit
300
t2i
DIOR_/ DIOW_ recovery time
900
t3
DIOW_ data setup
80
t4
DIOW_ data hold
40
t5
DIOR_ data setup
-
t6
DIOR_ data hold
-
t6Z
DIOR_ data tristate
-
t9
DIOR_/ DIOW_ to address valid hold
Read Data Valid to IORDY active
(if IORDY initially low after tA)
tRD
900
tA
IORDY Setup time
-
tB
IORDY Pulse Width
-
tC
IORDY assertion to release (max)
-
6.5.11 Multiword DMA data transfer
Register transfer timing parameters
Timing (ns)
t0
Cycle time
120
tD
DIOR_/ DIOW_ asserted pulse width
80
tE
DIOR_ data access
-
tF
DIOR_ data hold
-
tG
DIOR_/ DIOW_ data setup
40
tH
DIOW_ data hold
18
tI
DMACK to DIOR_/ DIOW_ setup
18
tJ
DIOR_/ DIOW_ to DMACK hold
20
tKR
DIOR_ negated pulse width
36
tKW
DIOW_ negated pulse width
36
tLR
DIOR_ to DMARQ delay
-
tLW
DIOW_ to DMARQ delay
-
tM
CS(1:0) (max) valid to DIOR_/ DIOW_
36
tN
CS(1:0) hold
18
tZ
DMACK_ to read data released
©2000-2006 Genesys Logic Inc. - All rights reserved.
-
Page 42
GL824/GL824C USB 2.0 On-The-Go Controller
Note:
The host shall not assert DMACK_ or negate both CS0_ and CS1_ until the assertion of DMARQ is detected.
The maximum time from the assertion of DMARQ to the assertion of DMACK_ or the negation of both CS0_
and CS1_ is not defined.
Figure 6.13 - Initiating a Multiword DMA Data Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 43
GL824/GL824C USB 2.0 On-The-Go Controller
Figure 6.14 - Sustaining a Multiword DMA Data Burst
Note:
To terminate the data burst, the Device shall negate DMARQ within the tL of the assertion of the current
DIOR_ or DIOW_ pulse. The last data word for the burst shall then be transferred by the negation of the
current DIOR_ or DIOW_ pulse. If all data for the command has not been transferred, the device shall reassert
DMARQ again at any later time to resume the DMA operation.
Figure 6.15 - Device Terminating a Multiword DMA Data Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 44
GL824/GL824C USB 2.0 On-The-Go Controller
Note:
1. To terminate the transmission of a data burst, the Host shall negate DMACK_ within the specified time
after a DIOR_ or DIOW_ pulse. No further DIOR_ or DIOW_ pulses shall be asserted for this burst.
2.
If the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait
for the host to reassert DMACK_ or may negate DMARQ at any time after detecting that DMACK_
has been negated.
Figure 6.16 - Host terminating a Multiword DMA Data Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 45
GL824/GL824C USB 2.0 On-The-Go Controller
6.5.12 Ultra DMA data transfer
Table 6.5 - Ultra DMA data burst timing requirements
Name
Mode 0
(in ns)
min
max
Mode 1
(in ns)
min
max
Mode 2
(in ns)
min
max
Mode 3
(in ns)
min
max
Mode 4
(in ns)
Min
Comment
max
Typical sustained average
two cycle time
Cycle time allowing for
asymmetry and clock
variations
Two cycle time allowing
for clock variations
Data setup time at
recipient
t2CYCTYP
240
160
120
90
60
tCYC
112
73
54
39
25
t2CYC
230
154
115
86
57
tDS
15
10
7
7
5
tDH
5
5
5
5
5
tDVS
70
48
30
20
6
tDVH
6
6
6
6
6
tFS
0
230
0
200
0
170
0
130
0
120
Data valid setup time at
sender
Data valid hold time at
sender
First STORBE time
tLI
0
150
0
150
0
150
0
100
0
100
Limited interlock time
tMLI
20
20
20
20
20
tUI
0
0
0
0
0
tAZ
10
10
10
10
20
20
20
20
20
tZAD
0
0
0
0
0
tENV
20
20
70
20
70
20
55
Interlock
time
with
minimum
Unlimited interlock time
10
tZAH
70
Data hold time at recipient
20
Drivers to assert or negate
55
tSR
50
30
20
NA
NA
tRFS
75
70
60
60
60
tRP
160
tIORDYZ
125
20
100
20
100
20
100
20
20
tZIORDY
0
0
0
0
0
tACK
20
20
20
20
20
tSS
50
50
50
50
50
©2000-2006 Genesys Logic Inc. - All rights reserved.
Maximum time allowed
for output drivers to
release
Minimum delay time
required for output
Envelope time
STROBE to DMARDY_
time
Ready to final STROBE
time
Minimum time to assert
STOP or negate DMARQ
Maximum time before
releasing IORDY
Minimum time before
driving STROBE
Setup and hold times for
DMACK_
Time from STROBE edge
to negation of DMARQ or
assertion of STOP
Page 46
GL824/GL824C USB 2.0 On-The-Go Controller
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are not in efficient until DMARQ and DMACK are asserted.
Figure 6.17 - Initiating an Ultra DMA Data-In Burst
Notes:
IODD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling
time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until
some time after they are driven by the device.
Figure 6.18 - Sustained Ultra DMA Data-In Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 47
GL824/GL824C USB 2.0 On-The-Go Controller
Notes:
1. The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after
HDMARDY_ is negated.
2. If the tSR timing is not satisfied, the host may receive zero, one, or two more data words from the device.
Figure 6.19 - Host Pausing an Ultra DMA Data-In Burst
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are
negated.
Figure 6.20 - Device Terminating an Ultra DMA Data-In Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 48
GL824/GL824C USB 2.0 On-The-Go Controller
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are
negated.
Figure 6.21 - Host Terminating an Ultra DMA Data-In Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 49
GL824/GL824C USB 2.0 On-The-Go Controller
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.
Figure 6.22 - Initiating an Ultra DMA Data-Out Burst
Notes:
IODD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling
time as well as cable propagation delay shall not allow the data signals to be considered stable at the devicet
until some time after they are driven by the host.
Figure 6.23 - Sustained Ultra DMA Data-Out Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 50
GL824/GL824C USB 2.0 On-The-Go Controller
Notes:
1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after
DDMARDY_ is negated.
2. If the tSR timing is not satisfied, the device may receive zero, one, or two more data words from the host.
Figure 6.24 - Device Pausing an Ultra DMA Data-Out Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 51
GL824/GL824C USB 2.0 On-The-Go Controller
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are
negated.
Figure 6.25 - Host terminating an Ultra DMA data-out burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 52
GL824/GL824C USB 2.0 On-The-Go Controller
Notes:
The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and
IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are
negated.
Figure 6.26 - Device Terminating an Ultra DMA Data-Out Burst
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 53
GL824/GL824C USB 2.0 On-The-Go Controller
CHAPTER 7
PACKAGE DIMENSION
SYMBOL
A
A1
A2
b
c
D
D1
E
E1
e
L
L1
Y
Internal No.
Green Package
Code No.
Lot Code
A1
A2
A
Date Code
DIMENSION MM (MIL)
MIN.
NOM.
MAX.
--1.60(63)
0.05(2)
-0.15(6)
1.35(53)
1.40(55)
1.45(57)
0.17(7)
0.22(9)
0.27(11)
0.09(4)
-0.20(8)
30.00 (1181) BSC
28.00 (1102) BSC
30.00 (1181) BSC
28.00 (1120) BSC
0.50 (20) BSC
0.45(18)
0.60(24)
0.75(30)
1.00 (39) REF
--0.08(3)
0o
3.5o
7o
GAGE PLANE
Figure 7.1 - GL824 208 Pin LQFP Package
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 54
GL824/GL824C USB 2.0 On-The-Go Controller
65
64
97
SYMBOL
A
A1
A2
b
c
D
D1
E
E1
e
L
L1
Y
Internal No.
Green
Package
Code No.
Date Code
Lot Code
33
128
NOTE: 1.REFER TO JEDEC MS-026/BEE REV.B
32
1
e
DIMENSION MM (MIL)
MIN.
NOM.
MAX.
1.60(63)
0.05(2)
0.15(6)
1.35(53)
1.40(55)
1.45(57)
0.13(5)
0.18(7)
0.23(9)
0.09(4)
0.20(8)
16.00 (630) BSC
14.00 (551) BSC
16.00 (630) BSC
14.00 (551) BSC
0.40 (16) BSC
0.45(18)
0.60(24)
0.75(30)
1.00 (39) REF
0.10(4)
0o
3.5o
7o
2.ALL DIMENSIIONS IN MILLIMETERS.
b
Q
E1
D1
Y S
S
D
E
b
BASE
METAL
X
GAGE
PLANE
PLATING
X
L
L1
SEATING PLANE
SECTION X-X
Detall
Q
Figure 7.2 - GL824C 128 Pin LQFP Package
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 55
GL824/GL824C USB 2.0 On-The-Go Controller
CHAPTER 8
ORDERING INFORMATION
Table 8.1 - Ordering Information
Part Number
Package
Green
Version
Status
GL824-MZGXX
208-pin LQFP
Green Package
XX
Available
GL824C-MXGXX
128-pin LQFP
Green Package
XX
Available
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 56
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