Lattice ISPLSI1048E125LQNI In-system programmable high density pld Datasheet

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ispLSI 1048E
®
In-System Programmable High Density PLD
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
— 96 I/O Pins, Twelve Dedicated Inputs
Output Routing Pool
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
E7 E6 E5 E4 E3 E2 E1 E0
D7
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
D Q
A1
A2
A3
A4
Logic
Global Routing Pool (GRP)
D5
Array
D Q
D Q
GLB
D4
D3
D2
A5
D Q
A6
D1
D0
A7
— Functionally and Pin-out Compatible to ispLSI 1048C
D6
D
ES
IG
N
Output Routing Pool
— High-Speed Global Interconnects
S
A0
— 288 Registers
Output Routing Pool
Features
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
Output Routing Pool
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
0139G1A-isp
EW
— tpd = 7.5 ns Propagation Delay
CLK
Description
— TTL Compatible Inputs and Outputs
— Electrically Eraseable and Reprogrammable
The ispLSI 1048E is a High Density Programmable Logic
Device containing 288 Registers, 96 Universal I/O pins,
12 Dedicated Input pins, four Dedicated Clock Input pins,
two dedicated Global OE input pins, and a Global Routing
Pool (GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1048E offers
5V non-volatile in-system programmability of the logic, as
well as the interconnect to provide truly reconfigurable
systems. A functional superset of the ispLSI 1048 architecture, the ispLSI 1048E device adds two new global
output enable pins and two additional dedicated inputs.
N
— Non-Volatile
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
FO
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
R
— 100% Tested at Time of Manufacture
EA
— Reprogram Soldered Devices for Faster Prototyping
48
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
10
The basic unit of logic on the ispLSI 1048E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
SI
— Synchronous and Asynchronous Clocks
is
pL
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
U
SE
— Lead-Free Package Options
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1048e_12
1
August 2006
Specifications ispLSI 1048E
Functional Block Diagram
Figure 1. ispLSI 1048E Functional Block Diagram
I/O I/O I/O I/O
91 90 89 88
I/O I/O I/O I/O
87 86 85 84
I/O I/O I/O I/O
83 82 81 80
IN IN
11 10
I/O I/O I/O I/O
79 78 77 76
I/O I/O I/O I/O
75 74 73 72
I/O I/O I/O I/O
71 70 69 68
I/O I/O I/O I/O
67 66 65 64
IN
9
IN
8
S
I/O I/O I/O I/O
95 94 93 92
Input Bus
Input Bus
Generic
Logic Blocks
(GLBs)
GOE 1
Output Routing Pool (ORP)
Output Routing Pool (ORP)
F7
F6
F5
F4
F3
F2
F1
F0
E7
E6
E5
E4
E3
E2
ES
IG
N
RESET
GOE 0
E1
E0
D7
I/O 12
I/O 13
I/O 14
I/O 15
A4
A5
B0
B1
B2
B3
B4
B5
B6
B7
Input Bus
ispEN
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
48
I/O I/O I/O I/O
16 17 18 19
C0
D
D3
D2
C1
C3
I/O 58
I/O 57
C5
C6
C7
Clock
Distribution
Network
Output Routing Pool (ORP)
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
D1
C4
I/O 60
I/O 59
D0
C2
I/O 63
I/O 62
I/O 61
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Input Bus
IN SCLK/ I/O I/O I/O I/O
4 IN 5 32 33 34 35
I/O I/O I/O I/O
36 37 38 39
I/O I/O I/O I/O
40 41 42 43
I/O I/O I/O I/O
44 45 46 47
Y Y Y Y
0 1 2 3
0139F(2)-48B-isp
10
IN 2 SDO/
IN 3
EA
Output Routing Pool (ORP)
Megablock
FO
A7
SDI/IN 0
MODE/IN 1
D4
R
A6
D5
lnput Bus
A3
EW
Global
Routing
Pool
(GRP)
A2
N
Output Routing Pool (ORP)
I/O 8
I/O 9
I/O 10
I/O 11
D6
A1
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
A0
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
IN 7
IN 6
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
pL
SI
The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered input, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to minimize overall output switching noise.
SE
is
Clocks in the ispLSI 1048E device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0). The logic
of this GLB allows the user to create an internal clock
from a combination of internal signals within the device.
U
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. Each ispLSI
1048E device contains six Megablocks.
2
Specifications ispLSI 1048E
Absolute Maximum Ratings 1
Supply Voltage Vcc. ................................. -0.5 to +7.0V
S
Input Voltage Applied ........................ -2.5 to VCC +1.0V
ES
IG
N
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
EW
D
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
VIL
VIH
Input Low Voltage
Commercial
Industrial
TA = 0°C to + 70°C
R
Supply Voltage
TA = -40°C to + 85°C
FO
VCC
N
PARAMETER
SYMBOL
EA
Input High Voltage
MIN.
MAX.
UNITS
4.75
5.25
V
4.5
5.5
V
0
0.8
V
2.0
Vcc+1
V
Table 2-0005/1048E
Capacitance (TA=25oC, f=1.0 MHz)
TYPICAL
UNITS
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
8
pf
VCC = 5.0V, VPIN = 2.0V
Y0 Clock Capacitance
15
pf
VCC = 5.0V, VPIN = 2.0V
10
C1
C2
48
PARAMETER
SYMBOL
TEST CONDITIONS
Table 2-0006/1048E
pL
SI
Data Retention Specifications
PARAMETER
Data Retention
MINIMUM
MAXIMUM
UNITS
20
–
Years
10000
–
Cycles
is
Erase/Reprogram Cycles
U
SE
Table 2-0008/1048E
3
Specifications ispLSI 1048E
Switching Test Conditions
Figure 2. Test Load
GND to 3.0V
Input Rise and Fall Time
+ 5V
≤ 3 ns 10% to 90%
1.5V
Output Timing Reference Levels
1.5V
Output Load
R1
See Figure 2
Device
Output
Table 2-0003/1048E
3-state levels are measured 0.5V from
steady-state active level.
ES
IG
N
Input Timing Reference Levels
S
Input Pulse Levels
Test
Point
CL*
D
R2
Output Load Conditions (see Figure 2)
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
A
B
C
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
*CL includes Test Fixture and Probe Capacitance.
EW
CL
0213a
N
R2
R
R1
FO
TEST CONDITION
48
DC Electrical Characteristics
EA
Table 2-0004a
SYMBOL
10
Over Recommended Operating Conditions
CONDITION
PARAMETER
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS1
Output Low Voltage
ICC2, 4
3
MIN.
TYP.
MAX. UNITS
–
–
0.4
V
IOH = -4 mA
2.4
–
–
V
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
–
–
-10
μA
Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC
–
–
10
μA
ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL
–
–
-150
μA
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
μA
Output Short Circuit Current
VCC = 5V, VOUT = 0.5V
–
–
-200
mA
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V Commercial
–
175
–
mA
SE
is
pL
SI
IOL= 8 mA
Output High Voltage
–
U
175
–
mA
Industrial
fCLOCK = 1 MHz
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems Table 2-0007/1048E
by tester ground degradation. Characterized but not 100% tested.
2. Measured using twelve 16-bit counters.
3. Typical values are at VCC = 5V and TA= 25°C.
4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC .
4
Specifications ispLSI 1048E
External Timing Parameters
Over Recommended Operating Conditions
-125
1
MIN. MAX. MIN. MAX. MIN. MAX.
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
7.5
–
A
2
Data Propagation Delay, Worst Case Path
–
10.0
–
A
3
Clock Frequency with Internal Feedback 3
125.0
–
91.0
4
Clock Frequency with External Feedback (
(
1
twh + twl
1
tsu2 + tco1
)
)
ns
12.5
ns
100.0
–
90.9
–
MHz
–
71.0
–
71.0
–
MHz
167.0
–
125.0
–
125.0
–
MHz
5.5
–
6.5
–
6.5
–
ns
–
6.5
–
6.5
ns
0.0
–
0.0
–
ns
Clock Frequency, Max. Toggle
6
GLB Reg. Setup Time before Clock,4 PT Bypass
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
4.5
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
–
9
GLB Reg. Setup Time before Clock
–
10 GLB Reg. Clock to Output Delay
–
11 GLB Reg. Hold Time after Clock
A
12 Ext. Reset Pin to Output Delay
–
13 Ext. Reset Pulse Duration
B
14 Input to Output Enable
C
15 Input to Output Disable
B
16 Global OE Output Enable
C
17 Global OE Output Disable
–
EW
5
–
6.5
–
7.5
–
7.5
–
ns
–
5.5
–
7.5
–
7.5
ns
0.0
–
0.0
–
0.0
–
ns
N
R
10.0
–
–
FO
–
10.0
UNITS
12.5
D
–
-90
-100
S
DESCRIPTION
–
10.0
–
13.5
–
13.5
ns
5.0
–
6.5
–
6.5
–
ns
–
12.0
–
15.0
–
15.0
ns
12.0
–
15.0
–
15.0
ns
7.0
–
9.0
–
9.0
ns
–
7.0
–
9.0
–
9.0
ns
18 External Synchronous Clock Pulse Duration, High
3.0
–
4.0
–
4.0
–
ns
–
19 External Synchronous Clock Pulse Duration, Low
3.0
–
4.0
–
4.0
–
ns
–
20
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0
–
3.5
–
4.0
–
ns
–
21
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
–
0.0
–
0.0
–
ns
48
EA
–
–
0.0
SI
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
U
SE
is
pL
1.
2.
3.
4.
2
#
10
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
tsu3
th3
TEST
COND.
ES
IG
N
4
PARAMETER
5
Table 2-0030A/1048E
Specifications ispLSI 1048E
External Timing Parameters
Over Recommended Operating Conditions
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
A
2
Data Propagation Delay, Worst Case Path
–
A
3
DESCRIPTION
1
Clock Frequency with Internal Feedback
-50
MIN. MAX. MIN. MAX.
3
1
tsu2 + tco1
–
4
Clock Frequency with External Feedback (
–
5
Clock Frequency, Max. Toggle
)
–
6
GLB Reg. Setup Time before Clock,4 PT Bypass
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
–
9
GLB Reg. Setup Time before Clock
–
10 GLB Reg. Clock to Output Delay
–
20.0
ns
18.5
–
24.5
ns
70.0
–
50.0
–
MHz
56.0
–
42.0
–
MHz
100.0
–
77.0
–
MHz
9.0
–
12.0
–
ns
–
7.0
–
9.5
ns
0.0
–
0.0
–
ns
11.0
–
14.5
–
ns
–
9.0
–
12.0
ns
0.0
–
0.0
–
ns
–
15.0
–
20.5
ns
10.0
–
13.0
–
ns
–
18.0
–
24.0
ns
–
18.0
–
24.0
ns
–
12.0
–
16.0
ns
–
12.0
–
16.0
ns
6.5
–
ns
EW
D
( twh 1+ twl )
15.0
UNITS
S
2
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
–
13 Ext. Reset Pulse Duration
B
14 Input to Output Enable
C
15 Input to Output Disable
B
16 Global OE Output Enable
C
17 Global OE Output Disable
–
18 External Synchronous Clock Pulse Duration, High
5.0
–
–
19 External Synchronous Clock Pulse Duration, Low
5.0
–
6.5
–
ns
–
20
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
4.0
–
6.5
–
ns
–
21
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
0.0
–
0.0
–
ns
48
EA
FO
R
N
–
A
SI
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
U
SE
is
pL
1.
2.
3.
4.
#
10
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
tsu3
th3
-70
TEST
COND.
ES
IG
N
4
PARAMETER
6
Table 2-0030B/1048E
Specifications ispLSI 1048E
Internal Timing Parameters1
-125
#2
DESCRIPTION
-100
-90
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs
–
0.3
–
23 I/O Latch Delay
–
1.9
–
24 I/O Register Setup Time before Clock
3.0
–
3.5
25 I/O Register Hold Time after Clock
0.0
–
0.0
26 I/O Register Clock to Out Delay
–
4.6
–
27 I/O Register Reset to Out Delay
–
4.6
–
28 Dedicated Input Delay
–
2.3
tgrp1
tgrp4
tgrp8
tgrp16
tgrp48
EW
GRP
2.3
–
2.5
ns
–
4.0
–
ns
–
-0.5
–
ns
5.0
–
5.0
ns
5.0
–
5.0
ns
ns
–
2.7
–
2.9
ns
–
1.9
–
2.2
ns
–
2.0
–
2.4
–
2.4
ns
–
2.3
–
2.6
–
2.7
ns
–
2.8
–
3.0
–
3.3
ns
–
4.9
–
5.4
–
5.7
ns
34 4 Product Term Bypass Path Delay (Combinatorial)
–
3.9
–
5.3
–
5.4
ns
35 4 Product Term Bypass Path Delay (Registered)
–
4.0
–
5.3
–
6.3
ns
36 1 Product Term/XOR Path Delay
–
3.6
–
4.6
–
6.5
ns
37 20 Product Term/XOR Path Delay
–
5.0
–
5.8
–
6.5
ns
–
5.0
–
6.3
–
7.3
ns
–
0.4
–
1.0
–
0.4
ns
40 GLB Register Setup Time before Clock
0.1
–
0.5
–
0.1
–
ns
41 GLB Register Hold Time after Clock
4.5
–
5.3
–
6.4
–
ns
42 GLB Register Clock to Output Delay
–
2.3
–
2.5
–
2.0
ns
43 GLB Register Reset to Output Delay
N
31 GRP Delay, 8 GLB Loads
R
32 GRP Delay, 16 GLB Loads
FO
33 GRP Delay, 48 GLB Loads
EA
48
38 XOR Adjacent Path Delay
3
SI
10
39 GLB Register Bypass Delay
4.9
–
6.2
–
6.3
ns
–
3.9
–
4.5
–
5.0
ns
45 GLB Product Term Output Enable to I/O Cell Delay
–
5.4
–
7.2
–
5.7
ns
2.9
4.0
3.5
4.7
4.0
5.2
ns
47 ORP Delay
–
1.0
–
1.0
–
1.0
ns
48 ORP Bypass Delay
–
0.0
–
0.0
–
0.0
ns
is
pL
–
44 GLB Product Term Reset to Register Delay
46 GLB Product Term Clock Delay
U
torp
torpbp
0.5
1.8
30 GRP Delay, 4 GLB Loads
SE
ORP
–
–
29 GRP Delay, 1 GLB Load
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
0.3
ES
IG
N
22 I/O Register Bypass
D
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
UNITS
S
PARAMETER
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Table 2-0036A/1048E
Specifications ispLSI 1048E
Internal Timing Parameters1
-70
#2
DESCRIPTION
-50
MIN. MAX. MIN. MAX.
Inputs
–
23 I/O Latch Delay
–
24 I/O Register Setup Time before Clock
4.1
25 I/O Register Hold Time after Clock
3.6
–
4.7
ns
–
6.5
–
ns
–
-0.7
–
ns
6.0
–
7.0
ns
27 I/O Register Reset to Out Delay
–
6.0
–
7.0
ns
–
4.3
–
6.1
ns
–
3.5
–
5.1
ns
–
3.7
–
5.4
ns
–
4.1
–
5.8
ns
–
4.8
–
6.6
ns
–
7.5
–
9.8
ns
34 4 Product Term Bypass Path Delay (Combinatorial)
–
8.5
–
10.7
ns
35 4 Product Term Bypass Path Delay (Registered)
–
7.4
–
9.2
ns
36 1 Product Term/XOR Path Delay
–
8.4
–
10.5
ns
37 20 Product Term/XOR Path Delay
–
8.4
–
10.5
ns
–
9.4
–
11.7
ns
EW
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
N
31 GRP Delay, 8 GLB Loads
R
32 GRP Delay, 16 GLB Loads
33 GRP Delay, 48 GLB Loads
FO
EA
3
48
38 XOR Adjacent Path Delay
–
1.6
–
2.2
ns
40 GLB Register Setup Time before Clock
0.1
–
0.0
–
ns
41 GLB Register Hold Time after Clock
8.5
–
11.5
–
ns
42 GLB Register Clock to Output Delay
–
2.0
–
3.0
ns
43 GLB Register Reset to Output Delay
SI
10
39 GLB Register Bypass Delay
6.3
–
7.3
ns
–
6.1
–
7.9
ns
45 GLB Product Term Output Enable to I/O Cell Delay
–
6.8
–
10.0
ns
5.1
6.4
6.9
8.3
ns
47 ORP Delay
–
2.0
–
2.5
ns
48 ORP Bypass Delay
–
0.0
–
0.0
ns
pL
–
44 GLB Product Term Reset to Register Delay
46 GLB Product Term Clock Delay
is
SE
torp
torpbp
ns
–
GLB
ORP
0.7
-0.6
GRP
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
–
26 I/O Register Clock to Out Delay
28 Dedicated Input Delay
tgrp1
tgrp4
tgrp8
tgrp16
tgrp48
0.6
ES
IG
N
22 I/O Register Bypass
D
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
UNITS
S
PARAMETER
U
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
Table 2-0036B/1048E
Specifications ispLSI 1048E
Internal Timing Parameters1
PARAMETER
#
-100
-125
DESCRIPTION
-90
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
49 Output Buffer Delay
–
1.3
–
50 Output Slew Limited Delay Adder
–
10.0
–
51 I/O Cell OE to Output Enabled
–
4.3
–
52 I/O Cell OE to Output Disabled
–
4.3
–
53 Global OE
–
2.7
–
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
0.9
0.9
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
0.9
0.9
57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Global Reset
tgr
R
59 Global Reset to GLB and I/O Registers
U
SE
is
pL
SI
10
48
EA
FO
1. Internal timing parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
9
1.7
ns
–
12.0
ns
5.1
–
6.4
ns
5.1
–
6.4
ns
3.9
–
2.6
ns
2.0
2.0
2.8
2.8
ns
2.0
2.0
2.8
2.8
ns
D
0.8
1.8
0.8
1.8
0.8
1.8
ns
0.0
0.0
0.0
0.0
0.0
0.5
ns
0.8
1.8
0.8
1.8
0.8
1.8
ns
–
2.8
–
4.3
–
4.5
ns
N
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
EW
56 Clock Delay, Clock GLB to Global GLB Clock Line
–
10.0
Clocks
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
2.0
ES
IG
N
tob
tsl
toen
todis
tgoe
S
Outputs
Table 2-0037A/1048E
Specifications ispLSI 1048E
Internal Timing Parameters1
#
-70
DESCRIPTION
-50
MIN. MAX. MIN. MAX.
Outputs
49 Output Buffer Delay
–
50 Output Slew Limited Delay Adder
–
51 I/O Cell OE to Output Enabled
–
52 I/O Cell OE to Output Disabled
–
53 Global OE
–
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
56 Clock Delay, Clock GLB to Global GLB Clock Line
57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
N
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset
tgr
EW
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
R
59 Global Reset to GLB and I/O Registers
U
SE
is
pL
SI
10
48
EA
FO
1. Internal timing parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
10
–
3.2
ns
12.0
–
12.0
ns
6.9
–
7.9
ns
6.9
–
7.9
ns
5.1
–
8.1
ns
D
Clocks
2.2
ES
IG
N
tob
tsl
toen
todis
tgoe
UNITS
S
PARAMETER
2.8
2.8
3.3
3.3
ns
2.8
2.8
3.3
3.3
ns
0.8
1.8
0.8
1.8
ns
0.1
0.6
0.0
0.7
ns
0.8
1.8
0.8
1.8
ns
–
4.5
–
7.5
ns
Table 2-0037B/1048E
Specifications ispLSI 1048E
ispLSI 1048E Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Ded. In
#34
#28
GLB Reg Bypass
ORP Bypass
#30
#35
#39
#48
Input
D Register Q
RST
#23 - 27
GRP Loading
Delay
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
#59
#29, 31-33
#36 - 38
GRP4
Reg 4 PT Bypass
D
Q
Control RE
PTs
OE
#44 - 46 CK
#55 - 58
EW
Y1,2,3
#40 - 43
D
Clock
Distribution
N
#54
Y0
#53
R
GOE 0,1
FO
Derivations of tsu, th and tco from the Product Term Clock 1
=
=
=
2.2 ns =
Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min))
(#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
(0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
th
=
=
=
3.5 ns =
Clock (max) + Reg h - Logic
(tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)
48
10
SI
Clock (max) + Reg co + Output
(tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
(#22 + #30 + #46) + (#42) + (#47 + #49)
(0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
pL
=
=
=
10.9 ns =
EA
tsu
tco
Derivations of tsu, th and tco from the Clock GLB 1
tsu
Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))
(#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
(0.3 + 2.0 + 5.0) + (0.1) – (0.9 + 2.3 + 0.8)
th
=
=
=
2.2 ns =
Clock (max) + Reg h - Logic
(tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
(#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
(0.9 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)
tco
=
=
=
9.6 ns =
Clock (max) + Reg co + Output
(tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
(#54 + #42 + #56) + (#42) + (#47 + #49)
(0.9 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
U
SE
is
=
=
=
3.4 ns =
1. Calculations are based upon timing specifications for the ispLSI 1048E-125.
Table 2-0042/1048E
11
#51, 52
#47
RST
#59
Reset
#49, 50
I/O Pin
(Output)
ES
IG
N
I/O Pin
(Input)
Comb 4 PT Bypass
#22
I/O Reg Bypass
S
Feedback
0491
Specifications ispLSI 1048E
Maximum GRP Delay vs. GLB Loads
10
ispLSI 1048E-50
ispLSI 1048E-70
7
6
ES
IG
N
GRP Delay (ns)
8
S
9
ispLSI 1048E-90/100
ispLSI 1048E-125
5
4
3
2
4
8
16
32
48
EW
1
D
1
GLB Loads
0127A/1048E
N
Power Consumption
Figure 3 shows the relationship between power and
operating speed.
FO
R
Power consumption in the ispLSI 1048E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
Figure 3. Typical Device Power Consumption vs fmax
EA
380
ispLSI 1048E
48
300
260
10
ICC (mA)
340
SI
220
pL
180
20
40
60
80
100
120
140
fmax (MHz)
Notes: Configuration of twelve 16-bit counters,
Typical current at 5V, 25°C
SE
is
0
U
ICC can be estimated for the ispLSI 1048E using the following equation:
ICC = 20 + (# of PTs * 0.42) + (# of nets * Max. freq * 0.010)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 4 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
0127B/1048E
12
Specifications ispLSI 1048E
Pin Description
PQFP / TQFP PIN NUMBERS
114
IN 2, IN 4
IN 6 - IN 11
47,
84,
51
110,
ispEN
18
SDI/IN 01
20
MODE/IN 11
46
SDO/IN 31
50
SCLK/IN 51
78
RESET
19
Y0
15
Y1
83
Dedicated input pins to the device.
111,
115,
116,
14
48
EA
FO
R
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. When low, the MODE,
SDI, SDO and SCLK controls become active.
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 also is used as one of the two control pins for the ISP state
machine. When ispEN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When ispEN is logic low, it
functions as pin to control the operation of the isp state machine. When
ispEN is high, it functions as a dedicated input pin.
Output/Input - This pin performs two functions. When ispEN is logic low,
it functions as an output pin to read serial shift register data. When
ispEN is high, it functions as a dedicated input pin.
10
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
SI
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
pL
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
80
SE
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Global Output Enable input pins.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
79
GND
1,
97,
17,
112
33,
49,
VCC
16,
48,
82,
113
U
DESCRIPTION
26,
32,
39,
45,
57,
63,
71,
77,
90,
96,
103,
109,
122,
128,
7,
13
is
Y2
Y3
25,
31,
38,
44,
56,
62,
70,
76,
89,
95,
102,
108,
121,
127,
6,
12,
S
64,
24,
30,
37,
43,
55,
61,
69,
75,
88,
94,
101,
107,
120,
126,
5,
11,
ES
IG
N
GOE0, GOE1
23,
29,
36,
42,
54,
60,
68,
74,
87,
93,
100,
106,
119,
125,
4,
10,
D
22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
105,
118,
124,
3,
9,
N
21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
104,
117,
123,
2,
8,
EW
NAME
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
65,
81,
Ground (GND)
VCC
Table 2 - 0002C-48E
1. Pins have dual function capability.
13
Specifications ispLSI 1048E
Pin Configuration
EW
N
R
FO
ispLSI 1048E
10
48
EA
Top View
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
Y1
VCC
GND
Y2
Y3
SCLK/IN 51
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
GND
U
GND
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
1MODE/IN 1
IN 2
VCC
GND
1SDO/IN 3
IN 4
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
GOE 0
SE
is
pL
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
IN 11
Y0
VCC
GND
ispEN
RESET
1SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
D
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
ES
IG
N
S
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
IN 10
IN 9
GOE 1
VCC
GND
IN 8
IN 7
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
ispLSI 1048E 128-Pin PQFP Pinout Diagram
1. Pins have dual function capability.
14
0124-48C
Specifications ispLSI 1048E
Pin Configuration
EW
N
R
FO
ispLSI 1048E
10
48
EA
Top View
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
GND
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
1MODE/IN 1
IN 2
VCC
GND
1SDO/IN 3
IN 4
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
GOE 0
U
SE
is
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
pL
SI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
IN 11
Y0
VCC
GND
ispEN
RESET
1SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
D
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
ES
IG
N
S
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
IN 10
IN 9
GOE 1
VCC
GND
IN 8
IN 7
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
ispLSI 1048E 128-Pin TQFP Pinout Diagram
1. Pins have dual function capability.
0124-48/TQFP
15
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
Y1
VCC
GND
Y2
Y3
SCLK/IN 51
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
GND
Specifications ispLSI 1048E
Package Thermal Characteristics
For the ispLSI 1048E-125LT, it is strongly recommended
that the actual Icc be verified to ensure that the maximum
junction temperature (TJ) with power supplied is not
exceeded. Depending on the specific logic design and
clock speed, airflow may be required to satisfy the maxi-
ES
IG
N
S
mum allowable junction temperature (TJ) specification.
Please refer to the Thermal Management section of the
Lattice Semiconductor Data Book or CD-ROM for additional information on calculating TJ.
Part Number Description
ispLSI 1048E – XXX
X
X
X
Device Family
Grade
Blank = Commercial
I = Industrial
D
Device Number
Package
Q = PQFP
T = TQFP
QN = Lead-Free PQFP
TN = Lead-Free TQFP
EW
Speed
Conventional Packaging
EA
ispLSI 1048E Ordering Information
Power
L = Low
FO
R
N
125 = 125 MHz fmax
100 = 100 MHz fmax
90 = 90 MHz fmax
70 = 70 MHz fmax
50 = 50 MHz fmax
COMMERCIAL
tpd (ns)
125
125
7.5
7.5
10
10
90
90
SI
100
100
10
10
ispLSI
PACKAGE
ispLSI 1048E-125LQ
ispLSI 1048E-125LT
ispLSI 1048E-100LQ
ispLSI 1048E-100LT
128-Pin PQFP
128-Pin TQFP
128-Pin PQFP
128-Pin TQFP
128-Pin PQFP
128-Pin TQFP
128-Pin PQFP
128-Pin TQFP
128-Pin PQFP
128-Pin TQFP
70
70
50
15
15
20
50
20
ispLSI 1048E-50LT
is
SE
U
FAMILY
ORDERING NUMBER
ispLSI 1048E-90LQ
ispLSI 1048E-90LT
ispLSI 1048E-70LQ
ispLSI 1048E-70LT
ispLSI 1048E-50LQ
pL
ispLSI
48
fmax (MHz)
10
FAMILY
Table 2-0041A/1048E
INDUSTRIAL
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
70
15
ispLSI 1048E-70LQI*
128-Pin PQFP
50
20
ispLSI 1048E-50LQI*
128-Pin PQFP
*Use 1048E-70 for new 1048E-50 designs.
Table 2-0041B/1048E
16
Specifications ispLSI 1048E
ispLSI 1048E Ordering Information (Cont.)
Lead-Free Packaging
COMMERCIAL
fmax (MHz)
tpd (ns)
125
125
7.5
7.5
100
100
10
10
90
90
10
10
70
70
50
15
15
20
ispLSI 1048E-90LQN
ispLSI 1048E-90LTN
ispLSI 1048E-70LQN
ispLSI 1048E-70LTN
ispLSI 1048E-50LQN
50
20
ispLSI 1048E-50LTN
S
PACKAGE
ispLSI 1048E-125LQN
ispLSI 1048E-125LTN
ispLSI 1048E-100LQN
ispLSI 1048E-100LTN
ES
IG
N
Lead-Free 128-Pin PQFP
Lead-Free 128-Pin TQFP
Lead-Free 128-Pin PQFP
Lead-Free 128-Pin TQFP
N
INDUSTRIAL
Lead-Free 128-Pin PQFP
Lead-Free 128-Pin TQFP
Lead-Free 128-Pin PQFP
Lead-Free 128-Pin TQFP
Lead-Free 128-Pin PQFP
D
ispLSI
ORDERING NUMBER
EW
FAMILY
Lead-Free 128-Pin TQFP
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
ispLSI
70
15
ispLSI 1048E-70LQNI
Lead-Free 128-Pin PQFP
FO
R
FAMILY
Revision History
Version
11
12
Previous Lattice release.
Updated for lead-free package options.
U
SE
is
pL
SI
10
48
—
August 2006
Change Summary
EA
Date
17
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