Dallas DS1646 Nonvolatile timekeeping ram Datasheet

DS1646/DS1646P
Nonvolatile Timekeeping RAM
www.dalsemi.com
FEATURES
−
−
−
−
−
PIN ASSIGNMENT
Integrates NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
Clock registers are accessed identically to the
static RAM. These registers are resident in
the eight top RAM locations
Totally nonvolatile with over 10 years of
operation in the absence of power
BCD coded year, month, date, day, hours,
minutes, and seconds with leap year
compensation valid up to 2100
Power-fail write protection allows for ±10%
VCC power supply tolerance
DS1646 only (DIP Module)
Standard JEDEC bytewide 128k x 8 RAM
pinout
DS1646P only (PowerCap® Module Board)
Surface mountable package for direct
connection to PowerCap containing battery
and crystal
Replaceable battery (PowerCap)
Power-fail output
Pin-for-pin compatible with other densities
of DS164XP Timekeeping RAM
ORDERING INFORMATION
DS1646
32-pin DIP module
*DS1646P
34-pin PowerCap Module
Board
*DS9034PCX
Power Cap
(Required; must be ordered
separately)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
32
31
30
29
28
27
26
25
24
23
22
21
VCC
A15
NC
WE
A13
A8
A9
A11
OE
A10
CE
A0
1
2
3
4
5
6
7
8
9
10
11
12
DQ0
13
20
DQ6
DQ1
DQ2
14
19
DQ5
15
18
DQ4
GND
16
17
DQ3
DQ7
32-Pin Encapsulated Package
NC
A15
A16
PFO
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
X1
GND VBAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34-Pin PowerCap Module Board
(Uses DS9034PCX PowerCap)
1 of 11
022101
DS1646/DS1646P
PIN DESCRIPTION
A0-A16
CE
OE
WE
VCC
GND
- Address Input
- Chip Enable
- Output Enable
- Write Enable
- +5V
- Ground
DQ0-DQ7
NC
PFO
X1, X2
VBAT
- Data Input/Output
- No Connection
- Power-fail Output
(DS1646P only)
- Crystal Connection
- Battery Connection
DESCRIPTION
The DS1646 is a 128k x 8 nonvolatile static RAM with a full-function real time clock, which are both
accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any
JEDEC standard 128k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and
EEPROM, providing read/write nonvolatility and the addition of the real time clock function. The real
time clock information resides in the eight uppermost RAM locations. The RTC registers contain year,
month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the
month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access
of incorrect data that can occur during clock update cycles. The double-buffered system also prevents
time loss as the timekeeping countdown continues unabated by access to time register data. The DS1646
also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-oftolerance condition. This feature prevents loss of data from unpredictable system operation brought on by
low VCC as errant access and update cycles are avoided.
PACKAGES
The DS1646 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1646P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS - READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1646 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was present at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that clock accuracy is not
affected by the access of data. All of the DS1646 registers are updated simultaneously after the clock
status is reset. Updating is within a second after the read bit is written to 0.
2 of 11
DS1646/DS1646P
BLOCK DIAGRAM DS1646 Figure 1
TRUTH TABLE DS1646 Table 1
VCC
5V ± 10%
<4.5V >VBAT
<VBAT
CE
OE
WE
VIH
X
VIL
VIL
VIL
X
X
X
X
X
VIL
VIH
X
X
X
X
VIL
VIH
VIH
X
X
MODE
DESELECT
DESELECT
WRITE
READ
READ
DESELECT
DESELECT
DQ
HIGH-Z
HIGH-Z
DATA IN
DATA OUT
HIGH-Z
HIGH-Z
HIGH-Z
POWER
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
CMOS STANDBY
DATA RETENTION
MODE
SETTING THE CLOCK
The MSB Bit, B7, of the control register is the write bit. Setting the write bit to a 1, like the read bit halts
updates to the DS1646 registers. The user can then load them with the correct day, date and time data in
24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters
and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the second’s registers. Setting it
to a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and
the oscillator is running, the LSB of the second’s register will toggle at 512 Hz. When the seconds
register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access
remain valid (i.e., CE low, OE low, and address for seconds register remain valid and stable).
3 of 11
DS1646/DS1646P
CLOCK ACCURACY (DIP MODULE)
The DS1646 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. Clock accuracy is also effected by the electrical environment and caution should be taken to
place the RTC in the lowest level EMI section of the PCB layout. For additional information please see
application note 58.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1646 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in
the lowest level EMI section of the PCB layout. For additional information please see application note
58.
1646 REGISTER MAP - BANK1 Table 2
ADDRESS
B7
X
X
X
X
X
1FFFF
1FFFE
1FFFD
1FFFC
1FFFB
1FFFA
1FFF9
OSC
1FFF8
W
OSC = STOP BIT
W
= WRITE BIT
B6
X
X
FT
X
R
B5
X
X
X
DATA
B4
B3
B2
X
X
X
X
X
R = READ BIT
X = UNUSED
B1
X
FUNCTION
B0
YEAR
00-99
MONTH
01-12
DATE
01-31
DAY
01-07
HOUR
00-23
MINUTES
00-59
SECONDS
00-59
X
CONTROL
A
FT = FREQUENCY TEST
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1646 is in the read mode whenever WE (write enable) is high; CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NVSRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip-enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA, the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
4 of 11
DS1646/DS1646P
WRITING DATA TO RAM OR CLOCK
The DS1646 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE and CE . The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of
another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
When VCC is within nominal limits (VCC > 4.5 volts) the DS1646 can be accessed as described above with
read or write cycles. However, when VCC is below the power-fail point VPF (point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-fail output signal ( PFO ) will be
driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the
level of the internal battery supply, power input is switched from the VCC pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal
level.
5 of 11
DS1646/DS1646P
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Storage Temperature
Soldering Temperature
-0.3V to +7.0V
-40°C to +85°C
260°C for 10 seconds (DIP Package) (See Note 7)
See IPC/JEDEC Standard J-STD-020A for
Surface Mount Devices
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
Range
Commercial
Temperature
0°C to +70°C
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Supply Voltage
Logic 1 Voltage All Inputs
Logic 0 Voltage All Inputs
SYMBOL
VCC
VIH
VIL
(Over the Operating Range)
MIN
4.5
2.2
-0.3
TYP
5.0
SYMBOL
ICC1
ICC2
ICC3
MIN
TYP
IIL
IOL
VOH
-1
-1
2.4
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Average VCC Power Supply Current
TTL Standby Current ( CE =VIH)
CMOS Standby Current
( CE =VCC-0.2V)
Input Leakage Current (any input)
Output Leakage Current
Output Logic 1 Voltage
(IOUT = -1.0 mA)
Output Logic 0 Voltage
(IOUT = +2.1 mA)
Write Protection Voltage
VCC
5V ± 10%
UNITS
V
V
V
NOTES
1
(Over the Operating Range)
3
2
VOL
VPF
MAX
5.5
VCC+0.3
0.8
4.0
6 of 11
4.25
MAX
85
6
4.0
UNITS
mA
mA
mA
+1
+1
µA
µA
V
0.4
V
4.5
V
NOTES
2, 3
2, 3
2, 3
DS1646/DS1646P
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Read Cycle Time
Address Access Time
CE Access Time
CE Data Off Time
Output Enable Access Time
Output Enable Data Off Time
Output Enable to DQ Low-Z
CE to DQ Low-Z
Output Hold from Address
Write Cycle Time
Address Setup Time
CE Pulse Width
Address Hold from End of Write
Write Pulse Width
WE Data Off Time
WE or CE Inactive Time
Data Setup Time
Data Hold Time High
SYMBOL
tRC
tAA
tCEA
tCEZ
tOEA
tOEZ
tOEL
tCEL
tOH
tWC
tAS
tCEW
tAH1
tAH2
tWEW
tWEZ
tWR
tDS
tDH1
tDH2
(Over the Operating Range)
MIN
120
TYP
MAX
120
120
40
100
40
5
5
5
120
0
100
5
30
75
40
10
85
0
25
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
5
6
5
6
AC TEST CONDITIONS
Input Levels:
Transition Times:
0V to 3V
5 ns
CAPACITANCE
PARAMETER
Capacitance on all pins (except DQ)
Capacitance on DQ pins
(tA = 25°C)
SYMBOL
CI
CDQ
MIN
AC ELECTRICAL CHARACTERISTICS
(POWER-UP/DOWN TIMING)
PARAMETER
CE or WE at VIH before Power-Down
VPF (Max) to VPF (Min) VCC Fall Time
VPF (Min) to VSO VCC Fall Time
VSO to VPF (Min) VCC Rise Time
VPF (Min) to VPF (Max) VCC Rise Time
Power-Up
Expected Data Retention Time
(Oscillator On)
SYMBOL
tPD
tF
tFB
tRB
tR
tREC
tDR
TYP
MAX
7
10
UNITS
pF
pF
NOTES
(Over the Operating Range)
MIN
0
300
10
1
0
15
10
7 of 11
TYP
MAX
35
UNITS
µs
µs
µs
µs
µs
ms
years
NOTES
4
DS1646/DS1646P
DS1646 READ CYCLE TIMING
DS1646 WRITE CYCLE TIMING
8 of 11
DS1646/DS1646P
POWER-DOWN/POWER-UP TIMING
NOTES:
1.
OUTPUT LOAD
All voltages are referenced to ground.
2. Typical values are at 25°C and nominal
supplies.
3.
Outputs are open.
4. Data retention time is at 25°C and is
calculated from the date code on the device
package. The date code XXYY is the year
followed by the week of the year in which
the device was manufactured. For example,
9225 would mean the 25th week of 1992.
5. tAH1, tDH1 are measured from WE going high.
6. tAH2, tDH2 are measured from CE going high.
7.
Real-Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering
techniques as long as temperatures as long as temperature exposure to the lithium energy source
contained within does not exceed +85°C. Post-solder cleaning with water washing techniques is
acceptable, provided that ultrasonic vibration is not used.
In addition, for the PowerCap version:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live-bug”).
b. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than
3 (three) seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To
remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick
to remove solder.
9 of 11
DS1646/DS1646P
DS1646 32-PIN PACKAGE
PKG
DIM
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
28-PIN
MIN
MAX
1.670
1.690
38.42
38.93
0.715
0.740
18.16
18.80
0.335
0.365
8.51
9.27
0.075
0.105
1.91
2.67
0.015
0.030
0.38
0.76
0.140
0.180
3.56
4.57
0.090
0.110
2.29
2.79
0.590
0.630
14.99
16.00
0.010
0.018
0.25
0.45
0.015
0.025
0.38
0.64
DS1646P
PKG
DIM
A
B
C
D
E
F
G
MIN
0.920
0.980
0.052
0.048
0.015
0.025
INCHES
NOM
0.925
0.985
0.055
0.050
0.020
0.027
MAX
0.930
0.990
0.080
0.058
0.052
0.025
0.030
NOTE:
For the PowerCap version:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented with the label side up (“live - bug”).
b. Hand Soldering and touch-up: Do not touch or apply the soldering iron to leads for more than
3 (three) seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To
remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to
remove solder.
10 of 11
DS1646/DS1646P
DS1646P WITH DS9034PCX ATTACHED
PKG
DIM
A
B
C
D
E
F
G
MIN
0.920
0.955
0.240
0.052
0.048
0.015
0.020
INCHES
NOM
0.925
0.960
0.245
0.055
0.050
0.020
0.025
MAX
0.930
0.965
0.250
0.058
0.052
0.025
0.030
INCHES
NOM
1.050
0.826
0.050
0.030
0.112
MAX
-
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
DIM
A
B
C
D
E
11 of 11
MIN
-
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