Mitsumi MM1313 I2c bus control 5-input 2-output av switch Datasheet

MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
I2C BUS Control 5-Input 2-Output AV Switch
Monolithic IC MM1313
Outline
This IC is a 5-input 2-output AV switch with I2C control, developed for use in televisions. Two outputs enable
it to support two screens or "picture-in-picture".
Features
1. Serial control by I2C bus.
2. 5-inputs, 2-outputs.
3. Video and audio system switches can be controlled independently.
4. 6dB amplifier built in to video system.
5. Built-in Y/C MIX circuit.
6. Slave address can be changed : 90H or 92H.
7. Audio muting possible by external pin.
8. Maintains high impedance even when I2C BUS line (SDA, SCL) power supply is off.
9. Built-in 3 value discrimination function.
10.On-chip power ON reset function.
11.Two types of audio input impedance : 60kΩ and 30kΩ.
MM1313AD : 60kΩ
MM1313BD : 30kΩ
12.Supports 2-screen or P-IN-P TV.
Package
SDIP-42A (MM1313AD, MM1313BD)
Applications
1. Televisions
2. Other video equipment
MITSUMI
Equivalent Block Diagram
I2C BUS Control 5-Input 2-Output AV Switch MM1313
I2C BUS Control 5-Input 2-Output AV Switch MM1313
MITSUMI
Pin Function
Pin No.
Name
Internal equivalent circuit diagram Pin No.
Name
41
MTV-V
33
LOUT1
1
V1-V
22
LOUT2
7
V2-V
32
ROUT1
13
V3-V
24
ROUT2
27
STV-V
3
V1-Y
9
V2-Y
31
YIN1
5
V1-C
36
BIAS
11
V2-C
29
CIN1
42
2
8
14
25
40
4
10
16
26
MTV-L
V1-L
V2-L
V3-L
STV-L
MTV-R
V1-R
V2-R
V3-R
STV-R
19
SCL
34
VOUT1
20
SDA
23
VOUT2
37
YOUT1
6
S1
39
COUT1
12
S2
21
ADR
28
Mute
Internal equivalent circuit diagram
I2C BUS Control 5-Input 2-Output AV Switch MM1313
MITSUMI
Absolute Maximum Ratings (Ta=25°C)
Item
Storage temperature
Operating temperature
Power supply voltage
Allowable power dissipation
Electrical Characteristics
Symbol
TSTG
TOPR
VCC
Pd
Ratings
-40~+125
-20~+75
12
850
Units
°C
°C
V
mW
(Ta=25°C, VCC=9V)
Measure Conditions (unless otherwise indicated,
Min. Typ. Max. Units
Measurement Circuit Figure 1)
ment pin
8
9
10
V
38
VCC=9V, no signal, no load
40
52
mA
Item
Symbol
Operating power supply voltage
Current consumption
VOUT1 output
Voltage gain
Frequency characteristics
VCC
ICC
GV1
FV1
TP1
TP1
Differential gain
DGV1
TP1
Differential phase
DPV1
TP1
Input dynamic range
DV 1
SG1~3
VOUT2 output
Voltage gain
GV2
TP6
Frequency characteristics
FV2
TP6
Differential gain
DGV2
TP6
Differential phase
DPV2
TP6
Input dynamic range
DV 2
SG1~3
GY1
GY2
TP2
TP2
FY1
TP2
FY2
TP2
Differential gain
DGY
TP2
Differential phase
DPY
TP2
Sine wave 1.0VP-P, 100kHz
5.5
Sine wave 1.0VP-P, 10MHz/100kHz -1.0
Vn-V : Staircase 1VP-P
APL=10~90%
Vn-Y : Staircase (luminance signal) 1VP-P -3
Vn-C : Chroma signal 0.3VP-P
APL=10~90%
Vn-V : Staircase 1VP-P
APL=10~90%
Vn-Y : Staircase (luminance signal) 1VP-P -3
Vn-C : Chroma signal 0.3VP-P
APL=10~90%
Sine wave 100kHz
Maximum input for total higher 1.6
harmonic distortion factor < 1.0%
6.0
0
6.5
1.0
dB
dB
0
3
%
0
3
deg
Sine wave 1.0VP-P, 100kHz
5.5
Sine wave 1.0VP-P
-1.0
10MHz/100kHz
Vn-V : Staircase 1VP-P
APL=10~90%
Vn-Y : Staircase (luminance signal) 1VP-P -3
Vn-C : Chroma signal 0.3VP-P
APL=10~90%
Vn-V : Staircase 1VP-P
APL=10~90%
Vn-Y : Staircase (luminance signal) 1VP-P -3
Vn-C : Chroma signal 0.3VP-P
APL=10~90%
Sine wave 100kHz
Maximum input for total higher 1.6
harmonic distortion factor < 1.0%
6.0
6.5
dB
0
1.0
dB
0
3
%
0
3
deg
1.9
VP-P
1.9
VP-P
YOUT1 output
Voltage gain
Frequency characteristics
Vn-Y : Sine wave 1.0VP-P, 100kHz
YIN1 : Sine wave 2.0VP-P, 100kHz
Vn-Y : Sine wave 1.0VP-P
10MHz/100kHz
YIN1 : Staircase 2.0VP-P
10MHz/100kHz
Vn-Y : Staircase 1VP-P
APL=10~90%
YIN1: Staircase 2VP-P
APL=10~90%
Vn-Y : Staircase 1VP-P
APL=10~90%
YIN1 : Staircase 2VP-P
APL=10~90%
5.5
-0.5
6.0
0
6.5
0.5
-1.0
0
1.0
-1.0
0
1.0
-3
0
3
%
-3
0
3
deg
dB
dB
I2C BUS Control 5-Input 2-Output AV Switch MM1313
MITSUMI
Item
Symbol
DY1
Input dynamic range
DY2
Output impedance
COUT1 output
ZOYC1
Measure Conditions (unless otherwise indicated,
Min. Typ. Max. Units
Measurement Circuit Figure 1)
ment pin
Vn-Y : Sine wave 100kHz
SG2
Maximum input for total higher 1.6
1.9
harmonic distortion factor < 1.0%
VP-P
VIN1 : Sine wave 100kHz
SG4
Maximum input for total higher 3.2
3.8
harmonic distortion factor < 1.0%
50
Ω
GC1
GC2
TP3
TP3
FC1
TP3
FC2
TP3
Differential gain
DGC
TP3
Differential phase
DPC
TP3
DC1
SG3
Voltage gain
Frequency characteristics
Input dynamic range
DC2
Input impedance
Output impedance
LOUT1 output
SG5
ZIC
ZOC1
Frequency characteristics
Total higher harmonic distortion
GL11
GL12
FL1
THDL1
TP4
TP4
TP4
TP4
Input dynamic range
DL1
SG6
Output offset voltage
VOFFL1
33
Voltage gain
Input impedance
ZIL1
Output impedance
ZOL1
LOUT2 output
Voltage gain
GL2
Frequency characteristics
FL2
Total higher harmonic distortion THDL2
TP7
TP7
TP7
Input dynamic range
DL2
SG6
Output offset voltage
VOFFL2
22
Output impedance
ROUT1 output
Vn-C : Sine wave 1.0VP-P, 100kHz
CIN1 : Sine wave 2.0VP-P, 100kHz
Vn-C : Sine wave 1.0VP-P
10MHz/100kHz
CIN1 : Sine wave 2.0VP-P
10MHz/100kHz
CIN1 : Staircase 2VP-P
APL=10~90%
CIN1 : Staircase 2VP-P
APL=10~90%
Vn-C : Sine wave 100kHz
Maximum input for total higher
harmonic distortion factor < 1.0%
CIN1: Sine wave 100kHz
Maximum input for total higher
harmonic distortion factor < 1.0%
Vn-C, CIN1
5.5
-0.5
6.0
0
6.5
0.5
-1.0
0
1.0
-1.0
0
1.0
-3
0
3
%
-3
0
3
deg
2.75
3.25
dB
VP-P
5.5
6.5
10
15
50
20
b7=0, Sine wave 2.5VP-P, 1kHz
-6.5
b7=1, Sine wave 2.5VP-P, 1kHz
-0.5
Sine wave 2.5VP-P, 1MHz/1kHz -3.0
Sine wave 2.5VP-P, 1kHz
Sine wave 1kHz
Maximum input for total higher 2.6
harmonic distortion factor < 0.5%
LOUT1 pin DC difference during
SW switching
42
-6.0
0.0
0
0.03
-5.5
0.5
1.0
0.1
Sine wave 2.5VP-P, 1kHz
-0.5
Sine wave 2.5VP-P, 1MHz/1kHz -3.0
Sine wave 2.5VP-P, 1kHz
Sine wave 1kHz
Maximum input for total higher 2.6
harmonic distortion factor < 0.5%
LOUT2 pin DC difference during
SW switching
ZOL2
GR11
GR12
Frequency characteristics
FR1
Total higher harmonic distortion THDR1
Voltage gain
2.8
Input dynamic range
DR1
SG7
Output offset voltage
VOFFR1
32
Input impedance
Output impedance
ZIR1
ZOR1
b7=0, Sine wave 2.5VP-P, 1kHz
-6.5
b7=1, Sine wave 2.5VP-P, 1kHz
-0.5
Sine wave 2.5VP-P, 1MHz/1kHz -3.0
Sine wave 2.5VP-P, 1kHz
Sine wave 1kHz
Maximum input for total higher 2.6
harmonic distortion factor < 0.5%
ROUT1 pin DC difference during
SW switching
42
kΩ
Ω
dB
dB
%
Vrms
0
±15
mV
60
120
78
kΩ
Ω
0.0
0
0.03
0.5
1.0
0.1
dB
dB
%
2.8
0
Vrms
±15
-6.0
0.0
0
0.03
mV
Ω
120
TP5
TP5
TP5
TP5
dB
-5.5
0.5
1.0
0.1
2.8
dB
dB
%
Vrms
0
±15
mV
60
120
78
kΩ
Ω
I2C BUS Control 5-Input 2-Output AV Switch MM1313
MITSUMI
Symbol Measure Conditions (unless otherwise indicated, Min. Typ. Max. Units
Measurement Circuit Figure 1)
ment pin
Item
ROUT2 output
Voltage gain
GR2
Frequency characteristics
FR2
Total higher harmonic distortion THDR2
TP8
TP8
TP8
Input dynamic range
DR2
SG7
Output offset voltage
VOFFR2
24
Sine wave 2.5VP-P, 1kHz
-0.5
Sine wave 2.5VP-P, 1MHz/1kHz -3.0
Sine wave 2.5VP-P, 1kHz
Sine wave 1kHz
Maximum input for total higher 2.6
harmonic distortion factor < 0.5%
ROUT2 pin DC difference during
switching
ZOR2
Output impedance
Crosswalk
VOUT 1
VOUT 2
YOUT 1
COUT 1
LOUT 1
LOUT 2
ROUT 1
ROUT 2
Video I/O Pin Voltage
Input pin voltage
CTV1
CTV2
CTY1
CTC1
CTL1
CTL2
CTR1
CTR2
0.5
1.0
0.1
2.8
0
TP1
TP2
TP3
TP6
TP4
TP5
TP7
TP8
±15
Ω
-53
-53
-53
-53
-80
-80
-80
-80
dB
dB
dB
dB
dB
dB
dB
dB
4.6
4.9
5.2
V
4.1
4.4
4.7
V
3.3
3.6
3.9
V
4.0
3.9
4.3
4.2
4.6
4.5
V
V
Measurement Circuit Figure 2
1kHz, 2.5VP-P
VVOP
Output pin voltage
VSOP
No signal, no load
No signal, no load
I2C logic low level discrimination value
I2Clogic high level discrimination value
SDA for 3mA inflow
when SDA, SCL=4.5V impressed
when SDA, SCL=0.4V impressed
0.0
3.0
0.0
-10
-10
4.7
4.0
4.7
4.0
4.7
200
250
4.0
1.5
5.0
0.4
+10
+10
100
V
V
V
µA
µA
kHz
µS
µS
µS
µS
µS
nS
nS
1000 nS
300
nS
µS
I2C BUS BUS Control Signal
SDA
tBUF
tR
tF
SCL
P
S tHD:STA tLOW
tHD:DAT
tHIGH
tSU:DAT tSU:STA Sr
mV
-60
-60
-60
-60
-90
-90
-90
-90
Measurement Circuit Figure 2
for SG1 input : 4.43MHz, 1VP-P
for SG2 input : 4.43MHz, 0.5VP-P
No signal, no load
VOUT1 pin, VOUT2 pin
No signal, no load
YOUT1 pin, COUT1 pin
No signal, no load
dB
dB
%
Vrms
120
VVIP
Audio I/O Pin Voltage
Input pin voltage
VAIP
Output pin voltage
VAOP
Logic section (Refer to figure below)
Input voltage L
VIL
Input voltage H
VIH
Low level output voltage (SDA)
VOL
High level input current
IIH
Low level input current
IIL
Clock frequency
fSCL
Data transmission waiting time
tBUF
SCL start hold time
tHD;STA
SCL low level hold time
tLOW
SCL high level hold time
tHIGH
SCL start set-up time
tSU;STA
SDA data hold time
tHD;DAT
SDA data set-up time
tSD;DAT
SCL rise time
tR
SCL fall time
tF
SCL stop set-up time
tSU;STO
0.0
0
0.03
tSU:STD P
MITSUMI
Measurement Circuit
Measurement Circuit 1
I2C BUS Control 5-Input 2-Output AV Switch MM1313
MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
Measurement Circuit 2 (Crosstalk measurement)
I2C BUS Control 5-Input 2-Output AV Switch MM1313
MITSUMI
I2C BUS
SDA
SCL
S
1
2
3
4 5
6
7 8 A
1
2
3
8
A
P
S:Start Condition
P:Stop Condition
A:Acknowledge
The I2C BUS is a BUS system developed by Philips for internal use in equipment. Data transmission is carried
out by the two SDA and SCL lines, in byte units, with the MSB first from start condition.
[Control Register]
The control register contains data sent from the master in order to determine the status of each switch.
S
Slave address
1
0
0
1
0
R/W
0 0/1 0
A
Control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Address byte
A
Control register 2
b7 b6 b5 b4 b3 b2 b1 b0
A
P
Control data
The data format is set as shown in the figure above. The first 7 bits in the address byte are allocated to the
slave address, and the remaining 1 bit is allocated to the read/write bit. The read/write bit is set at 0 when
using as a control register.
The MM1313 slave address can be selected as 90H/92H depending on the status of the ADR pin. When ADR
pin is low it is 90H.
The relationship between the control register bits and switch control is as shown below.
b7
b6
Audio S/Comp
Gain
Select
b5
b4
Video-Select
b3
b2
b1
b0
Audio-Select
The control register bits are reset to 0 when power is applied.
MM1313 control is carried out by the 3-byte structure of the 1 address byte and 2 control data bytes. The first
byte in the control data is control data for output 1, and the remaining 1 byte is control data for output 2.
All of the remaining data (fourth byte and after) are ignored.
Refer to the separate tables for details on switch control.
I2C BUS Control 5-Input 2-Output AV Switch MM1313
MITSUMI
[Status Register]
The status register contains data for sending device status to the master.
S
Slave address
1
0
0
1
0
R/W
0
0/1
1
Status register
A
b7
b6
Address byte
b5
b4
b3
b2
b1
b0
NA
P
Status data
The data format is set as shown in the figure above. The first 7 bits in the address byte are allocated to the
slave address, and the remaining 1 bit is allocated to the read/write bit. The read/write bit is set at 1 when
using as a status register.
The MM1313 slave address can be selected as 91H/93H depending on the status of the ADR pin. When the
ADR pin is low it is 91H. However, the confirmation response after completion of the status register should be
non-acknowledge.
The status register output data as shown below.
b7
b6
b5
b4
b3
b2
P-ON
S1
S1
S2
S2
RESET
OPEN
SEL
OPEN
SEL
b1
b0
P-ON RESET : Returns 1 for power on reset. However once data read begins, 0 is returned next.
S1/S2 OPEN : Returns 0 when the S1/S2 pin is not open, and returns 1 when the S1/S2 pin is open
S1/S2 SEL : Returns 0 when the S1/S2 pin is not grounded, and returns 1 when the S1/S2 pin is grounded.
S1/S2 OPEN, SEL have 3-value discrimination, and the combinations are as shown below.
S1/S2 pin DC voltage
S1/S2 OPEN
S1/S2 SEL
0.8V or less
0
1
1.3V or more, 3.5V or less
0
0
4.5V or more
1
0
[Power On Reset]
Power on reset is built in to reset each control register to 0 when power is turned on.
Power on reset threshold has hysteresis as shown in the figure below. The IC power on reset status can be
discriminated by reading the status register P-ON RESET.
Reset released
Undefined
Reset status
0.6V
4.3V
5.4V
VCC
I2C BUS Control 5-Input 2-Output AV Switch MM1313
MITSUMI
Switch Control Table
1. Video Output 1
2. Video Output 2
b6
b5
b4
b3
VOUT1
YOUT1
COUT1
b6
b5
b4
b3
VOUT2
0
0
0
0
Mute
Mute
Mute
0
0
0
0
Mute
0
0
0
1
MTV-V
YIN1
CIN1
0
0
0
1
MTV-V
0
0
1
0
V1-V
YIN1
CIN1
0
0
1
0
V1-V
0
0
1
1
V2-V
YIN1
CIN1
0
0
1
1
V2-V
0
1
0
0
V3-V
YIN1
CIN1
0
1
0
0
V3-V
0
1
0
1
STV-V
YIN1
CIN1
0
1
0
1
STV-V
0
1
1
0
Mute
0
1
0
1
Mute
1
1
Mute
1
1
1
0
0
0
Mute
Mute
Mute
1
0
0
0
Mute
1
0
0
1
MTV-V
YIN1
CIN1
1
0
0
1
MTV-V
1
0
1
0
V1-Y+C
V1-Y
V1-C
1
0
1
0
V1-Y+C
1
0
1
1
V2-Y+C
V2-Y
V2-C
1
0
1
1
V2-Y+C
1
1
0
0
V3-V
YIN1
CIN1
1
1
0
0
V3-V
1
1
0
1
STV-V
YIN1
CIN1
1
1
0
1
STV-V
1
1
1
0
Mute
1
1
0
1
Mute
1
1
Mute
1
1
3. Audio Output 1
Mute pin
Mute
4. Audio Output 1 Gain
Switching
b2
b1
b0
LOUT1
ROUT1
0
0
0
Mute
Mute
b7
Output gain
0
0
1
MTV-L
MTV-R
0
-6dB output
0
1
0
V1-L
V1-R
1
0dB output
1.5V or less
0
1
1
V2-L
V2-R
(OPEN)
1
0
0
V3-L
V3-R
1
0
1
STV-L
STV-R
1
0
1
1
Mute
Mute
-
-
-
Mute
Mute
b2
b1
b0
LOUT2
ROUT2
0
0
0
Mute
Mute
0
0
1
MTV-L
MTV-R
0
1
0
V1-L
V1-R
1.5V or less
0
1
1
V2-L
V2-R
(OPEN)
1
0
0
V3-L
V3-R
1
0
1
STV-L
STV-R
1
0
1
1
Mute
Mute
-
-
Mute
Mute
1
3.0V or more
5. Audio Output 2
Mute pin
1
3.0V or more
-
Mute
MITSUMI
I2C BUS Control 5-Input 2-Output AV Switch MM1313
Application Circuit
Notes
1. VOUT is set at 4.4V and CIN at 4.9V
Please note that capacitance polarity may vary depending on comb filter bias.
2. Each audio output can be muted by making pin 19 high. Mute is off when it is open or low.
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