Elpida HM5112805FTD-5 128m edo dram (16-mword ã 8-bit) 8k refresh/4k refresh Datasheet

HM5112805FTD-5,
HM5113805FTD-5
E0174H10 (Ver. 1.0)
(Previous ADE-203-1052B (Z))
Jul. 16, 2001
L
EO
128M EDO DRAM (16-Mword × 8-bit)
8k refresh/4k refresh
Description
Features
Pr
The HM5112805F Series, HM5113805F Series are 128M-bit dynamic RAMs organized as 16,777,216-word
× 8-bit. The y have re alize d high per forma nce and low powe r by employing C MOS proc ess tec hnology.
HM5112805F S erie s, HM5113805F S erie s off er Extende d Da ta Out (ED O) P age Mode as a high spee d
access mode. They are packaged in 32-pin plastic TSOPII.
od
• Single 3.3 V supply: 3.3 V ± 0.15 V
• Access time: 50 ns (max)
• Power dissipation
⎯ Active: 759 mW (max) (HM5112805F Series)
897 mW (max) (HM5113805F Series)
⎯ Standby : 3.5 mW (max) (CMOS interface)
• EDO page mode capability
• Refresh cycles
⎯ RAS-only refresh
8192 cycles/64 ms (HM5112805F)
4096 cycles/64 ms (HM5113805F)
⎯ CBR/Hidden refresh
4096 cycles/64 ms (HM5112805F, HM5113805F)
• 3 variations of refresh
⎯ RAS-only refresh
⎯ CAS-before-RAS refresh
⎯ Hidden refresh
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This product became EOL in December, 2006.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HM5112805FTD-5, HM5113805FTD-5
Ordering Information
Type No.
Access time
Package
HM5112805FTD-5
50 ns
400-mil 32-pin plastic TSOP II (TTP-32DF)
HM5113805FTD-5
50 ns
L
EO
od
Pr
t
uc
Data Sheet E0174H10
2
HM5112805FTD-5, HM5113805FTD-5
Pin Arrangement (HM5112805F Series)
32-pin TSOP
L
EO
VCC
1
32
VSS
I/O0
2
31
I/O7
I/O1
3
30
I/O6
I/O2
4
29
I/O5
I/O3
5
28
I/O4
NC
6
27
VSS
VCC
7
26
CAS
WE
8
25
OE
RAS
9
24
A12
A0
10
23
A11
A1
11
22
A10
A2
12
21
A9
Pr
A3
13
20
A8
A4
14
19
A7
A5
15
18
A6
VCC
16
17
VSS
od
(Top view)
Pin Description
Function
A0 to A12
Address input
— Row/Refresh address A0 to A12
— Column address
A0 to A10
I/O0 to I/O7
Data input/output
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
t
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Pin name
Data Sheet E0174H10
3
HM5112805FTD-5, HM5113805FTD-5
Pin Arrangement (HM5113805F Series)
32-pin TSOP
L
EO
1
32
VSS
I/O0
2
31
I/O7
I/O1
3
30
I/O6
I/O2
4
29
I/O5
I/O3
5
28
I/O4
NC
6
27
VSS
VCC
7
26
CAS
WE
8
25
OE
RAS
9
24
NC
A0
10
23
A11
A1
11
22
A10
A2
12
21
A9
A3
13
20
A8
A4
14
19
A7
A5
15
18
A6
VCC
16
17
VSS
od
Pr
VCC
(Top view)
Pin Description
Function
A0 to A11
Address input
— Row/Refresh address A0 to A11
— Column address
A0 to A11
I/O0 to I/O7
Data input/output
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
Data Sheet E0174H10
4
t
uc
Pin name
HM5112805FTD-5, HM5113805FTD-5
Block Diagram (HM5112805F Series)
A0
EO
A1
to
Upper pellet
Column decoder
•
•
•
Column
address
buffers
16M array
A10
Row decoder
I/O buffers
16M array
I/O1
I/O3
I/O4
I/O6
16M array
Pr
Timing and control
RAS
CAS
WE
OE
Lower pellet
od
Timing and control
Column decoder
Column
address
buffers
Row
address
buffers
16M array
t
uc
•
•
•
16M array
Row decoder
A12
Row
address
buffers
L
A11
16M array
I/O buffers
16M array
16M array
I/O0
I/O2
I/O5
I/O7
Data Sheet E0174H10
5
HM5112805FTD-5, HM5113805FTD-5
Block Diagram (HM5113805F Series)
A1
to
A10
Column
address
buffers
16M array
Row
address
buffers
L
A11
•
•
•
Upper pellet
Column decoder
16M array
Row decoder
EO
A0
I/O buffers
16M array
I/O1
I/O3
I/O4
I/O6
16M array
Pr
Timing and control
RAS
CAS
WE
OE
od
Lower pellet
Timing and control
Column decoder
Column
address
buffers
Row decoder
Row
address
buffers
16M array
I/O buffers
16M array
16M array
Data Sheet E0174H10
6
t
uc
•
•
•
16M array
I/O0
I/O2
I/O5
I/O7
HM5112805FTD-5, HM5113805FTD-5
Operation Table
CAS
WE
OE
I/O 0 to I/O 7
Operation
H
×
×
×
High-Z
Standby
L
L
H
EO
RAS
L
L
L
Dout
Read cycle
L*
2
×
Din
Early write cycle
2
H
Din
Delayed write cycle
L
L
L*
L
L
H to L
L to H
Dout/Din
Read-modify-write cycle
L
H
×
×
High-Z
RAS-only refresh cycle
H to L
L
H
×
High-Z
CAS-before-RAS refresh cycle
L
L
H
H
High-Z
Read cycle (Output disabled)
L
Notes: 1. H: VIH (inactive), L: VIL (active), ×: VIH or VIL
2. t WCS ≥ 0 ns: Early write cycle
t WCS < 0 ns: Delayed write cycle
Parameter
Pr
Absolute Maximum Ratings
Symbol
Value
Unit
Terminal voltage on any pin relative to VSS
VT
–0.5 to VCC + 0.5 (≤ 4.6 V (max))
V
Power supply voltage relative to VSS
VCC
–0.5 to +4.6
V
Short circuit output current
Iout
50
mA
od
Power dissipation
PT
Storage temperature
Tstg
DC Operating Conditions
1.0
W
–55 to +125
°C
Symbol
Min
Typ
Supply voltage
VCC
3.15
3.3
VSS
0
0
Input high voltage
VIH
2.0
—
Input low voltage
VIL
–0.3
—
Ambient temperature range
Ta
0
—
Max
Unit
Notes
t
uc
Parameter
3.45
V
1, 2
0
V
2
VCC + 0.3
V
1
0.8
V
1
70
˚C
Notes: 1. All voltage referred to VSS .
2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins
must be on the same level.
Data Sheet E0174H10
7
HM5112805FTD-5, HM5113805FTD-5
DC Characteristics (HM5112805F Series)
HM5112805F
-5
Symbol
Min
Max
Unit
Test conditions
I CC1
—
220
mA
t RC = min
I CC2
—
4
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
1
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
I CC3
—
220
mA
t RC = min
I CC5
—
10
mA
RAS = VIH, CAS = VIL
Dout = enable
CAS-before-RAS refresh current I CC6
—
220
mA
t RC = min
—
220
mA
RAS = VIL , CAS cycle,
t HPC = t HPC min
EO
Parameter
1,
Operating current* *
2
Standby current
L
RAS-only refresh current* 2
Standby current*
1
1,
EDO page mode current* *
Output leakage current
Output high voltage
Output low voltage
I CC7
Pr
Input leakage current
3
I LI
–5
5
µA
0 V ≤ Vin ≤ VCC + 0.3 V
I LO
–5
5
µA
0 V ≤ Vout ≤ VCC
Dout = disable
VOH
2.4
VCC
V
High Iout = –2 mA
VOL
0
0.4
V
Low Iout = 2 mA
od
Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Measured with one sequential address change per EDO cycle, t HPC .
t
uc
Data Sheet E0174H10
8
HM5112805FTD-5, HM5113805FTD-5
DC Characteristics (HM5113805F Series)
HM5113805F
-5
Symbol
Min
Max
Unit
Test conditions
I CC1
—
260
mA
t RC = min
I CC2
—
4
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
1
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
I CC3
—
260
mA
t RC = min
I CC5
—
10
mA
RAS = VIH, CAS = VIL
Dout = enable
CAS-before-RAS refresh current I CC6
—
260
mA
t RC = min
—
220
mA
RAS = VIL , CAS cycle,
t HPC = t HPC min
EO
Parameter
1,
Operating current* *
2
Standby current
L
RAS-only refresh current* 2
Standby current*
1
1,
EDO page mode current* *
Output leakage current
Output high voltage
Output low voltage
I CC7
Pr
Input leakage current
3
I LI
–5
5
µA
0 V ≤ Vin ≤ VCC + 0.3 V
I LO
–5
5
µA
0 V ≤ Vout ≤ VCC
Dout = disable
VOH
2.4
VCC
V
High Iout = –2 mA
VOL
0
0.4
V
Low Iout = 2 mA
od
Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Measured with one sequential address change per EDO cycle, t HPC .
Capacitance (Ta = 25˚C, VCC = 3.3 V ± 0.15 V)
Symbol
Typ
Input capacitance (Address)
CI1
—
Input capacitance (Clocks)
CI2
—
Output capacitance (Data-in, Data-out)
CI/O
—
t
uc
Parameter
Max
Unit
Notes
7
pF
1
7
pF
1
8
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. RAS and CAS = VIH to disable Dout.
Data Sheet E0174H10
9
HM5112805FTD-5, HM5113805FTD-5
AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.15 V, VSS = 0 V) *1, *2, *19
Test Conditions
Input rise and fall time: 2 ns
Input pulse levels: VIL = 0 V, VIH = 3.0 V
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
EO
•
•
•
•
•
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
L
HM5112805F/HM5113805F
-5
Symbol
Min
Max
Unit
Random read or write cycle time
t RC
84
—
ns
RAS precharge time
t RP
30
—
ns
t CP
8
—
ns
t RAS
50
10000
ns
t CAS
8
10000
ns
t ASR
0
—
ns
t RAH
8
—
ns
CAS precharge time
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
t ASC
Column address hold time
t CAH
RAS to CAS delay time
t RCD
RAS to column address delay time
t RAD
RAS hold time
t RSH
CAS hold time
t CSH
CAS to RAS precharge time
Notes
0
—
ns
8
—
ns
12
37
ns
3
10
25
ns
4
13
—
ns
38
—
ns
t CRP
5
—
ns
OE to Din delay time
t OED
13
—
ns
5
OE delay time from Din
t DZO
0
—
ns
6
CAS delay time from Din
t DZC
0
—
ns
6
Transition time (rise and fall)
tT
2
50
ns
7
Data Sheet E0174H10
10
t
uc
Column address setup time
od
Pr
Parameter
HM5112805FTD-5, HM5113805FTD-5
Read Cycle
HM5112805F/HM5113805F
-5
Symbol
Min
Max
Unit
Notes
Access time from RAS
t RAC
—
50
ns
8, 9
Access time from CAS
t CAC
—
13
ns
9, 10, 17
Access time from address
t AA
—
25
ns
9, 11, 17
Access time from OE
t OEA
—
13
ns
9
Read command setup time
t RCS
0
—
ns
Read command hold time to CAS
t RCH
0
—
ns
Read command hold time from RAS
t RCHR
50
—
ns
Read command hold time to RAS
t RRH
0
—
ns
Column address to RAS lead time
t RAL
25
—
ns
Column address to CAS lead time
t CAL
15
—
ns
CAS to output in low-Z
t CLZ
0
—
ns
t OH
3
—
ns
Output data hold time from OE
t OHO
3
—
ns
Output buffer turn-off time
t OFF
—
13
ns
13, 21
Output buffer turn-off to OE
t OEZ
—
13
ns
13
CAS to Din delay time
t CDD
13
—
ns
5
L
EO
Parameter
Output data hold time from RAS
t OHR
Output buffer turn-off to RAS
t OFR
Output buffer turn-off to WE
t WEZ
WE to Din delay time
t WED
RAS to Din delay time
t RDD
od
Pr
Output data hold time
12
12
21
3
—
ns
21
—
13
ns
13, 21
—
13
ns
13
13
—
ns
13
—
ns
t
uc
Data Sheet E0174H10
11
HM5112805FTD-5, HM5113805FTD-5
Write Cycle
HM5112805F/HM5113805F
-5
Symbol
Min
Max
Unit
Notes
Write command setup time
t WCS
0
—
ns
14
Write command hold time
t WCH
8
—
ns
Write command pulse width
t WP
8
—
ns
Write command to RAS lead time
t RWL
13
—
ns
Write command to CAS lead time
t CWL
8
—
ns
Data-in setup time
t DS
0
—
ns
15
Data-in hold time
t DH
8
—
ns
15
Notes
L
EO
Parameter
Read-Modify-Write Cycle
Pr
HM5112805F/HM5113805F
-5
Parameter
Min
Max
Unit
t RWC
116
—
ns
RAS to WE delay time
t RWD
67
—
ns
14
t CWD
30
—
ns
14
42
—
ns
14
13
—
ns
CAS to WE delay time
Column address to WE delay time
t AWD
OE hold time from WE
t OEH
Refresh Cycle
od
Symbol
Read-modify-write cycle time
-5
t
uc
HM5112805F/HM5113805F
Parameter
Symbol
Min
Max
Unit
CAS setup time (CBR refresh cycle)
t CSR
5
—
ns
CAS hold time (CBR refresh cycle)
t CHR
8
—
ns
WE setup time (CBR refresh cycle)
t WRP
0
—
ns
WE hold time (CBR refresh cycle)
t WRH
8
—
ns
RAS precharge to CAS hold time
t RPC
5
—
ns
Data Sheet E0174H10
12
Notes
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Cycle
HM5112805F/HM5113805F
-5
Symbol
Min
Max
Unit
Notes
EDO page mode cycle time
t HPC
20
—
ns
20
EDO page mode RAS pulse width
t RASP
—
100000
ns
16
Access time from CAS precharge
t CPA
—
28
ns
9, 17
RAS hold time from CAS precharge
t CPRH
28
—
ns
Output data hold time from CAS low
t DOH
3
—
ns
CAS hold time referred OE
t COL
8
—
ns
CAS to OE setup time
t COP
5
—
ns
Read command hold time from
CAS precharge
t RCHC
28
—
ns
Write pulse width during CAS precharge t WPE
8
—
ns
OE precharge time
8
—
ns
L
EO
Parameter
t OEP
9, 22
Pr
EDO Page Mode Read-Modify-Write Cycle
HM5112805F/HM5113805F
-5
od
Parameter
Symbol
EDO page mode read-modify-write cycle t HPRWC
time
WE delay time from CAS precharge
t CPW
Max
Unit
57
—
ns
45
—
ns
Parameter
Symbol
Max
Refresh period
t REF
64
Parameter
Symbol
Max
Refresh period
t REF
64
Refresh(HM5113805F Series)
Notes
14
t
uc
Refresh(HM5112805F Series)
Min
Unit
Notes
ms
8192 cycles
Unit
Notes
ms
4096 cycles
Data Sheet E0174H10
13
HM5112805FTD-5, HM5113805FTD-5
L
EO
Notes: 1. AC measurements assume t T = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
3. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a
reference point only; if t RCD is greater than the specified t RCD (max) limit, than the access time is
controlled exclusively by t CAC .
4. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a
reference point only; if t RAD is greater than the specified t RAD (max) limit, then access time is
controlled exclusively by t AA .
5. Either t OED or t CDD must be satisfied.
6. Either t DZO or t DZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that t RCD ≤ t RCD (max) and t RAD ≤ t RAD (max). If t RCD or t RAD is greater than the maximum
recommended value shown in this table, t RAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that t RCD ≥ t RCD (max) and t RCD + t CAC (max) ≥ t RAD + t AA (max).
11. Assumes that t RAD ≥ t RAD (max) and t RCD + t CAC (max) ≤ t RAD + t AA (max).
12. Either t RCH or t RRH must be satisfied for a read cycles.
13. t OFF (max), t OEZ (max), t WEZ (max) and t OFR (max) define the time at which the outputs achieve the
open circuit condition and are not referred to output voltage levels.
14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if t WCS ≥ t WCS (min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ t RWD (min),
t CWD ≥ t CWD (min), and t AWD ≥ t AWD (min), or t CWD ≥ t CWD (min), t AWD ≥ t AWD (min) and t CPW ≥ t CPW (min), the
cycle is a read-modify-write and the data output will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
15. t DS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed
write or read-modify-write cycles.
16. t RASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among t AA , t CAC and t CPA.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to the device.
19. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes large
VCC/V SS line noise, which causes to degrade VIH min/VIL max level.
20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read
cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page
mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + t CP + 2 t T) becomes greater than the
specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO
page mode mix cycle (1) and (2).
21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold
time and turn off time are specified by the timing specifications of later rising edge of RAS and
CAS between t OHR and t OH and between t OFR and t OFF.
od
Pr
t
uc
Data Sheet E0174H10
14
HM5112805FTD-5, HM5113805FTD-5
L
EO
22. t DOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing
reference level.
23. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL.
od
Pr
t
uc
Data Sheet E0174H10
15
HM5112805FTD-5, HM5113805FTD-5
Timing Waveforms*23
Read Cycle
EO
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tT
tRSH
tCAS
L
CAS
tASR
tRAH
tRAL
tCAL
tASC
tCAH
Pr
Address
tRAD
Column
Row
tRRH
tRCHR
tRCS
od
WE
tRCH
tDZC
tCDD
tWED
tRDD
High-Z
tDZO
tOEA
OE
tCAC
tAA
tRAC
tCLZ
t
uc
;
Din
tOED
tOEZ
tOHO
tOFF
tOH
tOFR
tOHR
tWEZ
Dout
Dout
Data Sheet E0174H10
16
HM5112805FTD-5, HM5113805FTD-5
Early Write Cycle
tRC
tRAS
tRP
EO
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
CAS
L
tASR
tASC
tCAH
Pr
Address
tRAH
Row
Column
tWCS
tDS
tDH
Din
High-Z*
Dout
t
uc
Din
od
WE
tWCH
* t WCS
t WCS (min)
Data Sheet E0174H10
17
HM5112805FTD-5, HM5113805FTD-5
Delayed Write Cycle*18
tRC
tRAS
tRP
EO
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
CAS
L
tRAH
tASR
Address
tASC
Row
tCAH
Column
Pr
tRCS
WE
High-Z
tDS
tDH
Din
tOED
tDZO
tOEH
tOEP
OE
tOEZ
tCLZ
High-Z
Dout
Invalid Dout
Data Sheet E0174H10
18
t
uc
;
Din
tRWL
tWP
od
tDZC
tCWL
HM5112805FTD-5, HM5113805FTD-5
Read-Modify-Write Cycle*18
tRWC
tRAS
tRP
EO
RAS
tT
tRCD
tCAS
tCRP
CAS
L
tASR
Address
tRAD
tASC
tRAH
Row
tCAH
Column
Pr
tCWL
tCWD
tRCS
tRWL
tWP
tAWD
tRWD
WE
od
tDZC
tDH
tDS
High-Z
Din
;
Din
tOED
tOEH
tOEA
tOEP
OE
tCAC
tAA
tOEZ
tRAC
tOHO
Dout
t
uc
tDZO
Dout
High-Z
tCLZ
Data Sheet E0174H10
19
HM5112805FTD-5, HM5113805FTD-5
RAS-Only Refresh Cycle
tRC
tRAS
tRP
EO
RAS
tT
tRPC
tCRP
tCRP
CAS
L
tASR
Address
tRAH
Row
tOFR
High-Z
od
Data Sheet E0174H10
20
t
uc
;
Dout
Pr
tOFF
HM5112805FTD-5, HM5113805FTD-5
CAS-Before-RAS Refresh Cycle
tRC
tRP
tRC
tRP
EO
tRAS
tRAS
tRP
RAS
tT
tRPC
tCP
tRPC
tCSR
tCHR
tCP
tCRP
tCSR
tCHR
L
CAS
tWRP
tWRH
tWRP
tWRH
WE
Pr
Address
tOFR
od
tOFF
High-Z
t
uc
;
Dout
Data Sheet E0174H10
21
HM5112805FTD-5, HM5113805FTD-5
Hidden Refresh Cycle
tRC
tRAS
tRP
tRC
tRAS
tRC
tRP
tRAS
tRP
EO
RAS
tT
tRSH
tCHR
tCRP
tRCD
CAS
tRAL
L
tRAD
tASR
Address
tRAH
tASC
Row
tCAH
Column
Pr
tRRH
tRCS
WE
tWED
od
tDZC
tRCH
tCDD
tRDD
High-Z
Din
tDZO
OE
tCAC
tAA
tRAC
t
uc
tOEA
tOFF
;
tCLZ
tOH
Dout
Dout
Data Sheet E0174H10
22
tOED
tOFR
tOHR
tOEZ
tWEZ
tOHO
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Read Cycle (1)
t RP
t HPC
t RASP
EO
RAS
tT
t CSH
t CP
t HPC
t CAS
CAS
t HPC
t CPRH
t CP
t
t CRP
RSH
t CAS
t RCHR
t RCS
t CP
tCAS
tCAS
t RCHC
t RCH t RCS
t RRH
t RCH
WE
Address
tRAH tASC
tCAH
L
tASR
Row
Column 1
t WPE
t ASC t CAH
t ASC t CAH
Column 2
Column 3
t CAL
t CAL
t RAL
t CAH
tASC
t WED
Column 4
t CAL
t CAL
tRDD
tCDD
tDZC
Pr
High-Z
Din
tCOL
tDZO
tCOP
t OEP
OE
tCPA
tOEA
tOEZ
tOHO
tAA
tOEZ
;
tCAC
tAA
tOFR
tOHR
tOEZ
tCPA
tCPA
tAA
tCAC
od
tAA
tCAC
tOED
tOEP
tWEZ
tRAC
Dout
tOEA
tDOH
Dout 1
Dout 2
Dout 2
tOHO
Dout 3
tCAC
tOHO
tOFF
tOH
tOEA
Dout 4
t
uc
Data Sheet E0174H10
23
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Read Cycle (2)
t RP
t RASP
EO
RAS
tT
t CSH
t CP
t HPC
t CAS
CAS
tHPC
t CP
t HPC
t CP
t CAS
t CAS
t CRP
tRSH
tCAS
t RCHC
t RRH
t RCH
t RCS
WE
Address
tRAH tASC
tCAH
L
tASR
Row
Column 1
t ASC t CAH
t ASC t CAH
Column 2
t CAL
t RAL
t CAH
tASC
Column 3
t CAL
t WED
Column 4
t CAL
tRDD
t CAL
tDZC
tCDD
Pr
High-Z
Din
tCOL
tDZO
tCOP
t OEP
OE
tOEA
tCPA
tOEZ
tOFR
tOHR
tOEZ
tCPA
tAA
;
tCAC
tAA
tCPA
tAA
tCAC
od
tAA
tCAC
tOED
tOEP
tDOH
tRAC
Dout
tOHO
tOEA
tOEZ
tDOH
tOHO
Dout 1
Dout 2
Dout 2
Dout 3
tCAC
tOHO
tOFF
tOH
tOEA
Dout 4
t
uc
Data Sheet E0174H10
24
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Early Write Cycle
tRP
tRASP
EO
RAS
tT
tCSH
tHPC
tCAS
tRCD
tCP
tRSH
tCAS
tCP
tCAS
tCRP
CAS
L
tASR
Address
Row
tRAH
tASC
Column 1
Column 2
tWCH
tDH
Din 1
tWCS
tWCH
tASC
tCAH
Column N
tWCS
tWCH
tDS
tDH
Din 2
High-Z*
tDS
tDH
Din N
t
uc
Dout
tCAH
od
tDS
Din
tASC
Pr
tWCS
WE
tCAH
* t WCS
t WCS (min)
Data Sheet E0174H10
25
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Delayed Write Cycle*18
tRASP
EO
tRP
RAS
tT
tCP
tRCD
tCRP
tCP
tCSH
tHPC
tCAS
tCAS
tRSH
tCAS
CAS
L
tRAD
tASR
tASC
tCAH
tASC
tCAH
Column 1
Column 2
tRAH
Address
Row
tASC
tCAH
tWP
tDZC tDS
tRCS
Din
1
tDZO tOED
tDH
Din
2
tDZO
tOED
tOEP
tOEH
tDZO
tDH
Din
N
tOED
tOEP
tOEH
t
uc
;
tOEP
tOEH
tWP
tDZC tDS
od
tWP
tDZC tDS
tDH
Din
tCWL
tRWL
tRCS
tRCS
WE
tCWL
Pr
tCWL
Column N
OE
tCLZ
tCLZ
tOEZ
tCLZ
tOEZ
Dout
Invalid Dout
Invalid Dout
Data Sheet E0174H10
26
tOEZ
Invalid Dout
High-Z
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Read-Modify-Write Cycle*18
t RASP
EO
t RP
RAS
tT
t HPRWC
t CP
t RCD
t RSH
t CP
t CAS
t CAS
t CRP
t CAS
CAS
L
t RAD
t ASR
Address
t ASC
t RAH
Row
t ASC
t CAH
t CAH
Column 1
Column 2
Column N
Pr
t RWD
t CWL
t AWD
t RCS
t CPW
t AWD
t CWD
Din
1
t OED
t OEP
t OEH
t RWL
t CWD
t WP
t
t DZC DS
t DH
Din
2
t OED
t DZO
t OEP
t OEH
t OED
t DZO
t OHO
Din
N
t OEP
t OEH
t OHO
;
;
t OHO
t DH
t
uc
OE
t CWL
t AWD
t RCS
t WP
t
t DZC DS
t DH
t DZO
t CWL
od
t WP
t
t DZC DS
Din
t CPW
t RCS
t CWD
WE
t ASC
t CAH
t OEA
t CAC
t OEA
t CAC
t AA
t OEA
t CAC
t AA
t CPA
t RAC
t OEZ
t CLZ
t AA
t CPA
t OEZ
t CLZ
t OEZ
t CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
Data Sheet E0174H10
27
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Mix Cycle (1)* 20
t RP
t RASP
EO
RAS
tT
t CAS
CAS
t CRP
t CP
t CP
t CP
t CAS
tCAS
t CSH
tCAS
tCWL
tRSH
t RCD
t WCS
tCPW
tAWD
WE
L
t ASC
tRAH
tASR
Address
Row
tASC t CAH
Column 2
Column 3
tASC
t RAL
t CAH
Column 4
t CAL
tRDD
tCDD
t CAL
t DH
Din 1
tWP
t DH
t DS
High-Z
Din 3
tOED
;
Din
Column 1
t ASC t CAH
Pr
t DS
tCAH
t RRH
t RCH
t RCS
t RCS
t WCH
OE
tCPA
tAA
tOEA
tAA
tCAC
Dout
tWED
t DOH
Dout 2
tOFR
tWEZ
tCPA
od
tCPA
tOEP
t OEZ
tCAC t OHO
Dout 3
tAA
tOEZ
tCAC
tOHO
tOEA
tOFF
tOH
Dout 4
t
uc
Data Sheet E0174H10
28
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Mix Cycle (2) *20
t RP
t RASP
RAS
EO
tT
CAS
t CSH
t CAS
t RCD
t CAS
tCAS
t RCHR
t RCS
t RCH
tWCS t WCH
tCWL
t ASC
tRAH
Row
tCAH
Column 1
t ASC t CAH
t ASC t CAH
Column 2
Column 3
tRSH
t RCS
t RRH
t RCH
tWP
tCPW
L
Address
tCAS
t RCS
WE
tASR
t CRP
t CP
t CP
t CP
t RAL
t CAH
tASC
Column 4
t CAL
t CAL
t DS
t DH
Pr
t DS
High-Z
Din
Din 2
Din 3
t OEP
t OEP
tOED
tOED
tCOP
tWED
tCOL
OE
t OEA
tOEA
tCAC
tOEZ
tCPA
tAA
tCAC
tRAC
t OHO
Dout 1
tOFR
tWEZ
tCPA
od
tAA
Dout
tRDD
tCDD
t DH
tOEZ
t OHO
Dout 3
tAA
tCAC
tOEZ
tOEA
tOFF
tOH
tOHO
Dout 4
t
uc
Data Sheet E0174H10
29
HM5112805FTD-5, HM5113805FTD-5
Package Dimensions
HM5112805FTD Series
HM5113805FTD Series (TTP-32DF)
Unit: mm
17
10.16
32
L
1.27
1.20 Max
M
0.80
11.76 ± 0.20
Pr
1.15 Max
0.21
0.10
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
TTP-32DF
—
—
0.54 g
od
*Dimension including the plating thickness
Base material dimension
0° – 5° 0.50 ± 0.10
0.45
*0.42 ± 0.08
0.40 ± 0.06
16
*0.12 ± 0.05
0.10 ± 0.04
1
0.05 ± 0.05
EO
As of January, 2001
20.95
21.35 Max
t
uc
Data Sheet E0174H10
30
HM5112805FTD-5, HM5113805FTD-5
Cautions
L
EO
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any
third party’s patent, copyright, trademark, or other intellectual property rights for information contained
in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third
party’s rights, including intellectual property rights, in connection with use of the information contained
in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands especially
high quality and reliability or where its failure or malfunction may directly threaten human life or cause
risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally
foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such
as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily
injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
od
Pr
t
uc
Data Sheet E0174H10
31
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