IDT IDT74ALVC16245PV 3.3v cmos 16-bit bus transceiver with 3-state output Datasheet

IDT74ALVC16245
3.3V CMOS 16-BIT BUS TRANSCIEVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT
BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
IDT74ALVC16245
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
µ W typ. static)
• CMOS power levels (0.4µ
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
This 16-bit bus transceiver is built using advanced dual metal CMOS
technology. The ALVC16245 is designed for asynchronous communication
between data buses. The control-function implementation minimizes external
timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
It allows data transmission from the A bus to the B bus or from the B bus to the
A bus, depending on the logic level at the direction-control (DIR) input. The
output-enable (OE) input can be used to disable the device so that the buses
are effectively isolated.
The ALVC16245 has been designed with a ±24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
DRIVE FEATURES:
APPLICATIONS:
• High Output Drivers: ±24mA
• Suitable for heavy loads
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1 DIR
1
2 DIR
48
1A 1
1A 2
2A 1
2A 2
2A 3
5
1A 4
1A 5
1A 6
1A 7
1A 8
17
2A5
2A 6
2A 7
2B 5
20
2B6
22
2A 8
12
19
27
1B 7
37
2B7
26
23
1B 8
2B 4
29
1B 6
38
2B 3
30
1B 5
40
11
2B 2
32
1B 4
41
9
14
16
2A 4
8
2B 1
33
1B 3
43
6
13
35
1B 2
44
2 OE
36
1B 1
46
3
1A 3
25
1 OE
47
2
24
2B 8
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4604/2
IDT74ALVC16245
3.3V CMOS 16-BIT BUS TRANSCIEVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
VTERM(2)
Max
Unit
Terminal Voltage with Respect to GND
–0.5 to +4.6
V
1 DIR
1
48
1 OE
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
1B 1
2
47
1A 1
TSTG
Storage Temperature
–65 to +150
°C
1B 2
3
46
1A 2
IOUT
DC Output Current
–50 to +50
mA
IIK
±50
mA
GND
4
45
GND
Continuous Clamp Current,
VI < 0 or VI > VCC
1B 3
5
44
1A 3
IOK
Continuous Clamp Current, VO < 0
–50
mA
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
1B 4
6
43
1A 4
V CC
7
42
V CC
1B 5
8
41
1A 5
1B 6
9
40
1A 6
GND
10
39
GND
1B 7
11
38
1A 7
1B 8
12
37
1A 8
2B 1
13
36
2A 1
2B 2
14
35
2A 2
GND
15
34
GND
2B 3
16
33
2A 3
2B 4
17
32
2A 4
V CC
18
31
V CC
2B 5
19
30
2A 5
2B 6
20
29
2A 6
GND
21
28
GND
2B 7
22
27
2A 7
23
26
2A 8
2B 8
2 D IR
24
25
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
Conditions
Typ.
Max.
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
Output Capacitance
VOUT = 0V
7
9
pF
COUT
I/O Port Capacitance
VIN = 0V
7
9
pF
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
2 OE
Description
xOE
Output Enable Inputs (Active LOW)
xDIR
Direction Control Inputs
xAx
Side A Inputs or 3-State Outputs
xBx
Side B Inputs or 3-State Outputs
FUNCTION TABLE (EACH 8-BIT SECTION)(1)
SSOP/ TSSOP/ TVSOP
TOP VIEW
Inputs
xOE
xDIR
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
Z
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2
Unit
Outputs
IDT74ALVC16245
3.3V CMOS 16-BIT BUS TRANSCIEVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
VIH
VIL
Min.
Typ.(1)
Max.
Unit
VCC = 2.3V to 2.7V
1.7
—
—
V
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Test Conditions
V
IIH
Input HIGH Current
VCC = 3.6V
VI = VCC
—
—
±5
µA
IIL
Input LOW Current
VCC = 3.6V
VI = GND
—
—
±5
µA
IOZH
High Impedance Output Current
VCC = 3.6V
VO = VCC
—
—
±10
µA
IOZL
(3-State Output pins)
VO = GND
—
—
±10
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
—
–0.7
–1.2
V
VH
ICCL
ICCH
ICCZ
∆ICC
Input Hysteresis
Quiescent Power Supply Current
VCC = 3.3V
VCC = 3.6V
VIN = GND or VCC
—
—
100
0.1
—
40
mV
µA
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
VOL
Test Conditions(1)
Parameter
Output HIGH Voltage
Output LOW Voltage
Min.
Max.
Unit
V
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC – 0.2
—
VCC = 2.3V
IOH = – 6mA
2
—
VCC = 2.3V
IOH = – 12mA
1.7
—
VCC = 2.7V
2.2
—
VCC = 3V
2.4
—
VCC = 3V
IOH = – 24mA
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 6mA
—
0.4
IOL = 12mA
—
0.7
VCC = 2.7V
IOL = 12mA
—
0.4
VCC = 3V
IOL = 24mA
—
0.55
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
3
IDT74ALVC16245
3.3V CMOS 16-BIT BUS TRANSCIEVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance Outputs enabled
CPD
Power Dissipation Capacitance Outputs disabled
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Test Conditions
Typical
Typical
Unit
CL = 0pF, f = 10Mhz
22
29
pF
4
5
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
Symbol
Parameter
tPLH
Propagation Delay
tPHL
xAx to xBx or xBx to xAx
tPZH
Output Enable Time
tPZL
xOE to xAx or xBx
tPHZ
Output Disable Time
tPLZ
xOE to xAx or xBx
tSK(o)
Output Skew(2)
VCC = 3.3V ± 0.3V
Max.
Min.
Max.
Min.
Max.
Unit
1
3.7
—
3.6
1
3
ns
1
5.7
—
5.4
1
4.4
ns
1
5.2
—
4.6
1
4.1
ns
—
—
—
—
—
500
ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
VCC = 2.7V
Min.
IDT74ALVC16245
3.3V CMOS 16-BIT BUS TRANSCIEVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
Symbol
VIH
VT
0V
VOH
VT
VOL
SAME PHASE
INPUT TRANSITION
VCC(2)= 2.5V±0.2V
Unit
VLOAD
6
6
2 x Vcc
V
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
tPLH
tPHL
tPLH
tPHL
OUTPUT
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
ALVC Link
Propagation Delay
VLOAD
VCC
Open
500Ω
(1, 2)
VIN
CONTROL
INPUT
VOUT
Pulse
Generator
DISABLE
ENABLE
GND
D.U.T.
tPZL
OUTPUT
SWITCH
NORMALLY CLOSED
LOW
tPZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
500Ω
RT
CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test
Switch
Open Drain
Disable Low
Enable Low
TIMING
INPUT
VLOAD
ASYNCHRONOUS
CONTROL
Open
tPHZ
VOH
VOH - VHZ
0V
VT
0V
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SWITCH POSITION
All Other Tests
VLOAD/2
VOL + VLZ
VOL
ALVC Link
DATA
INPUT
GND
VLOAD/2
VT
Enable and Disable Times
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
Disable High
Enable High
tPLZ
VIH
VT
0V
SYNCHRONOUS
CONTROL
tSU
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
tH
tREM
tSU
tH
ALVC Link
INPUT
OUTPUT 1
VIH
VT
0V
tPHL1
tPLH1
tSK (x)
tSK (x)
OUTPUT 2
tPLH2
Set-up, Hold, and Release Times
VOH
VT
VOL
LOW-HIGH-LOW
PULSE
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
tW
VT
ALVC Link
Pulse Width
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
VT
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVC16245
3.3V CMOS 16-BIT BUS TRANSCIEVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
ALVC X
Bus-Hold
Temp. Range
XX
Family
XX
XXX
Device Type Package
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
PV
PA
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Shrink Small Outline Package
Thin Shrink Small Outline Package
TSSOP - Green
Thin Very Small Outline Package
245
16-Bit Bus Transceiver with 3-State Outputs
16
Double-Density, ±24mA
Blank
No Bus-Hold
74
–40°C to +85°C
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