Vishay IRFZ48RS Power mosfet Datasheet

IRFZ48RS, IRFZ48RL, SiHFZ48RS, SiHFZ48RL
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Advanced Process Technology
60
RDS(on) (Ω)
VGS = 10 V
Qg (Max.) (nC)
110
Qgs (nC)
29
Qgd (nC)
36
Configuration
COMPLIANT
• Fast Switching
• Fully Avalanche Rated
• Drop in Replacement of the IRFZ48/SiHFZ48 for
Linear/Audio Applications
• Lead (Pb)-free Available
D
D2PAK (TO-263)
G
RoHS*
• 175 °C Operating Temperature
Single
I2PAK (TO-262)
Available
• Dynamic dV/dt
0.018
DESCRIPTION
Advanced Power MOSFETs from Vishay utilize advanced
processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
Power MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in a
wide variety of applications.
The D2PAK is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D2PAK is suitable for high current applications because of its
low internal connection resistance and can dissipate up to
2 W in a typical surface mount application.
G
D
S
S
N-Channel MOSFET
ORDERING INFORMATION
D2PAK (TO-263)
IRFZ48RSPbF
SiHFZ48RS-E3
IRFZ48RS
SiHFZ48RS
Package
Lead (Pb)-free
SnPb
I2PAK (TO-262)
IRFZ48RLPbF
SiHFZ48RL-E3
-
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
60
Gate-Source Voltage
VGS
± 20
Continuous Drain Currente
Pulsed Drain
VGS at 10 V
TC = 25 °C
ID
TC = 100 °C
Currenta, e
IDM
Linear Derating Factor
Single Pulse Avalanche
Peak Diode Recovery
A
290
EAS
100
mJ
PD
190
W
dV/dt
4.5
V/ns
TJ, Tstg
- 55 to + 175
TC = 25 °C
Operating Junction and Storage Temperature Range
50
50
W/°C
dV/dtc, e
Soldering Recommendations (Peak Temperature)d
V
1.3
Energyb, e
Maximum Power Dissipation
UNIT
for 10 s
300d
°C
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91296
S-Pending-Rev. A, 22-Jul-08
WORK-IN-PROGRESS
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IRFZ48RS, IRFZ48RL, SiHFZ48RS, SiHFZ48RL
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
Mounting Torque
LIMIT
UNIT
10
lbf · in
1.1
N·m
6-32 or M3 screw
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, Starting TJ = 25 °C, L = 22 µH, RG = 25 Ω, IAS = 72 A (see fig. 12).
c. ISD ≤ 72 A, dI/dt ≤ 200 A/µs, VDD ≤ VDS, TJ ≤ 175 °C.
d. 1.6 mm from case.
e. Current limited by the package, (Die Current = 72 A).
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
62
Case-to-Sink, Flat, Greased Surface
RthCS
0.50
-
Maximum Junction-to-Case (Drain)
RthJC
-
0.8
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
VDS
VGS = 0 V, ID = 250 µA
60
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mAc
-
0.60
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.0
V
nA
IGSS
IDSS
RDS(on)
gfs
VGS = ± 20 V
-
-
± 100
VDS = 60 V, VGS = 0 V
-
-
25
VDS = 48 V, VGS = 0 V, TJ = 150 °C
-
-
250
-
-
0.018
Ω
27
-
-
S
ID = 43 Ab
VGS = 10 V
VDS = 25 V, ID = 43
Ab
µA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5c
VGS = 10 V
ID = 72 A, VDS = 48 V,
see fig. 6 and 13b, c
-
2400
-
-
1300
-
-
190
-
-
-
110
-
-
29
Gate-Drain Charge
Qgd
-
-
36
Turn-On Delay Time
td(on)
-
8.1
-
-
250
-
-
210
-
-
250
-
-
4.5
-
-
7.5
-
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
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VDD = 30 V, ID = 72 A,
RG = 9.1 Ω, RD = 0.34 Ω, see fig. 10b, c
Between lead,
6 mm (0.25") from
package and center of
die contact
D
pF
nC
ns
nH
G
S
Document Number: 91296
S-Pending-Rev. A, 22-Jul-08
IRFZ48RS, IRFZ48RL, SiHFZ48RS, SiHFZ48RL
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
-
-
50c
-
-
290
-
-
2.0
UNIT
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 72 A, VGS = 0 Vb
TJ = 25 °C, IF = 72 A, dI/dt = 100 A/µsb, c
V
-
120
180
ns
-
0.50
0.80
µC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Current limited by the package, (Die Current = 72 A).
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics
Document Number: 91296
S-Pending-Rev. A, 22-Jul-08
Fig. 2 - Typical Output Characteristics
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IRFZ48RS, IRFZ48RL, SiHFZ48RS, SiHFZ48RL
Vishay Siliconix
RDS(on) , Drain-to-Source On Resistance
(Normalized)
Fig. 3 - Typical Transfer Characteristics
2.5
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
ID = 72A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( ° C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91296
S-Pending-Rev. A, 22-Jul-08
IRFZ48RS, IRFZ48RL, SiHFZ48RS, SiHFZ48RL
Vishay Siliconix
80
ID , Drain Current (A)
LIMITED BY PACKAGE
60
40
20
0
25
50
75
100
125
150
175
TC , Case Temperature ( ° C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Drain Current vs. Case Temperature
1000
VDS
OPERATION IN THIS AREA LIMITED
BY RDS(on)
VGS
ID , Drain Current (A)
10us
100
RD
D.U.T.
RG
100us
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
1ms
Fig. 10a - Switching Time Test Circuit
10
10ms
VDS
90 %
TC = 25 °C
TJ = 175 °C
Single Pulse
1
0.1
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
1000
10 %
VGS
td(on)
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Document Number: 91296
S-Pending-Rev. A, 22-Jul-08
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IRFZ48RS, IRFZ48RL, SiHFZ48RS, SiHFZ48RL
Vishay Siliconix
Thermal Response(Z thJC )
1
D = 0.50
0.20
0.1
0.10
PDM
0.05
t1
0.02
t2
SINGLE PULSE
(THERMAL RESPONSE)
0.01
0.01
0.00001
0.0001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.001
0.01
0.1
1
10
t1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
Driver
L
VDS
D.U.T.
RG
+
A
- VDD
IAS
20 V
tp
IAS
0.01 Ω
EAS , Single Pulse Avalanche Energy (mJ)
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
250
ID
29A
51A
BOTTOM 72A
TOP
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J, Junction Temperature ( ° C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
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Document Number: 91296
S-Pending-Rev. A, 22-Jul-08
IRFZ48RS, IRFZ48RL, SiHFZ48RS, SiHFZ48RL
Vishay Siliconix
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
0.2 µF
12 V
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Maximum Avalanche Energy vs. Drain Current
Fig. 13b - Gate Charge Test Circuit
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91296.
Document Number: 91296
S-Pending-Rev. A, 22-Jul-08
www.vishay.com
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
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Document Number: 91000
Revision: 18-Jul-08
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