IDT IDT7216L35J 16 x 16 parallel cmos multiplier Datasheet

IDT7216L
IDT7217L
16 x 16 PARALLEL
CMOS MULTIPLIERS
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT7216/IDT7217 are high-speed, low-power
16 x 16-bit multipliers ideal for fast, real time digital signal
processing applications. Utilization of a modified Booths
algorithm and IDT’s high-performance, submicron CMOS
technology, has achieved speeds comparable to bipolar (20ns
max.), at 1/10 the power consumption.
The IDT7216/IDT7217 are ideal for applications requiring
high-speed multiplication such as fast Fourier transform
analysis, digital filtering, graphic display systems, speech
synthesis and recognition and in any system requirement
where multiplication speeds of a mini/microcomputer are
inadequate.
All input registers, as well as LSP and MSP output registers, use the same positive edge-triggered D-type flip-flop. In
the IDT7216, there are independent clocks (CLKX, CLKY,
CLKM, CLKL) associated with each of these registers. The
IDT7217 has only a single clock input (CLK) and three register
enables. ENX and ENY control the two input registers, while
ENP controls the entire product.
The IDT7216/IDT7217 offer additional flexibility with the FA
control and MSPSEL functions. The FA control formats the
output for two’s complement by shifting the MSP up one bit
and then repeating the sign bit in the MSB of the LSP. The
•
•
•
•
•
•
•
•
•
•
•
16 x 16 parallel multiplier with double precision product
16ns clocked multiply time
Low power consumption: 120mA
Produced with advanced submicron CMOS high performance technology
IDT7216L is pin- and function compatible with TRW
MPY016H/K and AMD Am29516
IDT7217L requires a single clock with register enables
making it pin- and function compatible with AMD
Am29517
Configured for easy array expansion
User-controlled option for transparent output register
mode
Round control for rounding the MSP
Input and output directly TTL-compatible
Three-state output
Available in Top Braze, DIP, PLCC, Flatpack and Pin
Grid Array
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962-86873 is listed on this
function for IDT7216 and Standard Military Drawing
#5962-87686 is listed for this function for IDT7217.
Speeds available: Commercial: L16/20/25/35/45/55/65
Military:
L20/25/30/40/55/65/75
FUNCTIONAL BLOCK DIAGRAMS
XM X15-0
IDT7216
RND
YM Y15-0/P15-0
16
16
XREGISTER
XM X15-0
REGISTER
IDT7217
RND
YM Y15-0/P15-0
16
16
YREGISTER
XREGISTER
REGISTER
YREGISTER
CLK
ENX
CLKY
CLKX
OEL
OEL
ENY
MULTIPLIER
ARRAY
FA
MULTIPLIER
ARRAY
FA
FORMAT ADJUST
MSP
LSP
REGISTER REGISTER
16
16
FT
CLKM
CLKL
FT
FORMAT ADJUST
MSP
LSP
REGISTER REGISTER
16
16
ENP
MULTIPLEXER
MSPSEL
OEP
PRODUCT
MSPSEL
OEP
16
MSPOUT (P31 - P16)
MULTIPLEXER
PRODUCT
16
MSPOUT (P31 - P16)
2580 drw 01
2580 drw 02
The IDT Logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1995 Integrated Device Technology, Inc.
11.3
AUGUST 1995
DSC-2023/6
1
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (Cont’d.)
MSPSEL low selects the MSP to be available at the product
output port, while a high selects the LSP to be available.
Keeping this pin low will ensure compatibility with the TRW
MPY016H.
The IDT7216/IDT7217 multipliers are manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making them ideally suited to applications demanding the
highest level of performance and reliability.
PIN CONFIGURATIONS
IDT7216
X4
X3
X2
X1
X0
OEL
CLKL
CLKY
P0, Y0
P1, Y1
P2, Y2
P3, Y3
P4, Y4
P5, Y5
P6, Y6
P7, Y7
P8, Y8
P9, Y9
P10, Y10
P11, Y11
P12, Y12
P13, Y13
P14, Y14
P15, Y15
P0, P16
P1, P17
P2, P18
P3, P19
P4, P20
P5, P21
P6, P22
P7, P23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
C64-2 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
IDT7217
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
CLKX
RND
XM
YM
VCC
VCC
GND
GND
MSPSEL
FT
FA
OEP
CLKM
P15 , P31
P14 , P30
P13 , P29
P12 , P28
P11 , P27
P10 , P26
P9, P25
P8, P24
X4
X3
X2
X1
X0
OEL
CLK
ENY
P0, Y0
P1, Y1
P2, Y2
P3, Y3
P4, Y4
P5, Y5
P6, Y6
P7, Y7
P8, Y8
P9, Y9
P10, Y10
P11, Y11
P12, Y12
P13, Y13
P14, Y14
P15, Y15
P0, P16
P1, P17
P2, P18
P3, P19
P4, P20
P5, P21
P6, P22
P7, P23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
C64-2 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2580 drw 03
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
ENX
RND
XM
YM
VCC
VCC
GND
GND
MSPSEL
FT
FA
OEP
ENP
P15 , P31
P14 , P30
P13 , P29
P12 , P28
P11 , P27
P10 , P26
P9, P25
P8, P24
2580 drw 04
64-PIN DIP
TOP VIEW
64-PIN DIP
TOP VIEW
11.3
2
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Cont’d.)
IDT7216/IDT7217
11
NC
X13
X15
RND
X14
CLKX
or
ENX*
XM
YM
VCC GND
FT
OEP
VCC GND MSPSEL
FA
CLKM
or
ENP*
10
X11
X12
09
X9
X10
P30,
P14
P31,
P15
08
X7
X8
P28,
P12
P29,
P13
07
X5
X6
P26,
P10
P27,
P11
06
X3
X4
P24,
P8
P25,
P9
05
X1
X2
P22,
P6
P23,
P7
04
OEL
X0
P20,
P4
P21,
P5
03
CLKY
or
CLKL
or
CLK*
P18,
P2
P19,
P3
P17,
P1
ENY*
02
NC
01
Pin 1
Designator
A
G68-2
Y0,
P0
Y2,
P2
Y4,
P4
Y6,
P6
Y8,
P8
Y10,
P10
Y12,
P12
Y14,
P14
P16,
P0
Y1,
P1
Y3,
P3
Y5,
P5
Y7,
P7
Y9,
P9
Y11,
P11
Y13,
P13
Y15,
P15
NC
B
C
D
E
F
G
H
J
K
NC
L
*Pin designation for IDT7217
PGA
TOP VIEW
11.3
2580 drw 05
3
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Cont’d.)
P15, P31
P14, P30
P13, P29
P12, P28
P11, P27
P10, P26
P9, P25
P8, P24
P7, P23
P6, P22
P5, P21
P4, P20
P3, P19
P2, P18
P1, P17
P0, P16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ENP
OEP
FA
FT
MSPSEL
GND
GND
VCC
VCC
YM
XM
RND
ENX
X15
X14
X13
IDT7217
OEP
FA
FT
MSPSEL
GND
GND
VCC
VCC
YM
XM
RND
CLKX
X15
X14
X13
IDT7216
64636261 605958575655 545352 515049
64636261 605958575655 545352 515049
F64-1
P15,
P14,
P13,
P12,
P11,
P10,
P9,
P8,
P7,
P6,
P5,
P4,
P3,
P2,
P1,
P0,
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
OEL
CLKL
CLKY
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P31
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
17181920 212223242526 272829 303132
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
F64-1
P15, Y15
P14, Y14
P13, Y13
P12, Y12
P11, Y11
P10, Y10
P9, Y9
P8, Y8
P7, Y7
P6, Y6
P5, Y5
P4, Y4
P3, Y3
P2, Y2
P1, Y1
P0, Y0
P15, Y15
P14, Y14
P13, Y13
P12, Y12
P11, Y11
P10, Y10
P9, Y9
P8, Y8
P7, Y7
P6, Y6
P5, Y5
P4, Y4
P3, Y3
P2, Y2
P1, Y1
P0, Y0
17181920 212223242526 272829 303132
2580 drw 06
2580 drw 07
64-LEAD FLATPACK
TOP VIEW
IDT7216
IDT7217
NC
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
OEL
CLK
ENY
NC
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
OEL
CLKL
CLKY
64-LEAD FLATPACK
TOP VIEW
60 59 58 5756 5554 53 5251 50 4948 47 46 45 44
J68-1
L68-1,
L68-1
60 59 58 5756 5554 53 5251 50 4948 47 46 45 44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
NC
P0, Y0
P1, Y1
P2, Y2
P3, Y3
P4, Y4
P5, Y5
P6, Y6
P7, Y7
P8, Y8
P9, Y9
P10, Y10
P11, Y11
P12, Y12
P13, Y13
P14, Y14
P15, Y15
X13 61
X14 62
X15 63
ENX 64
RND 65
XM 66
YM 67
VCC68
VCC 1
GND 2
GND 3
MSPSEL 4
FT 5
FA 6
OEP 7
ENP 8
NC 9
10 1112 13 14 1516 17 1819 20 212223 24 25 26
L68-1,
L68-1
J68-1
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
NC
P0, Y0
P1, Y1
P2, Y2
P3, Y3
P4, Y4
P5, Y5
P6, Y6
P7, Y7
P8, Y8
P9, Y9
P10, Y10
P11, Y11
P12, Y12
P13, Y13
P14, Y14
P15, Y15
10 1112 13 14 1516 17 1819 20 2122 23 24 25 26
P15, P31
P14, P30
P13, P29
P12, P28
P11, P27
P10, P26
P9, P25
P8, P24
P7, P23
P6, P22
P5, P21
P4, P20
P3, P19
P2, P18
P1, P17
P0, P16
NC
P15, P31
P14, P30
P13, P29
P12, P28
P11, P27
P10, P26
P9, P25
P8, P24
P7, P23
P6, P22
P5, P21
P4, P20
P3, P19
P2, P18
P1, P17
P0, P16
NC
X13 61
X14 62
X15 63
CLKX 64
RND 65
XM 66
YM 67
VCC 68
VCC 1
GND 2
GND 3
MSPSEL 4
FT 5
FA 6
OEP 7
CLKM 8
NC 9
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
OEL
CLK
ENY
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2580 drw 08
PLCC
TOP VIEW
2580 drw 09
PLCC
TOP VIEW
11.3
4
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Pin Name
I/O
X0 - X15
I
Y0 - Y15/
P0 - P15
P16 - P31
I/O
O
OEL
I
OEP
I
XM, YM
I
RND
I
MSPSEL
I
FA
I
FT
I
Description
Data Inputs
Y0 - Y15 are data inputs
P0 - P15 are LSP register output, enabled when OEL = 0
Data Output (LSP or MSP)
Output enable control for LSP (least significant product). When low enables P0 - P15. When high P0 - P15
tristated.
Output enable control for MSP (most significant product). When low enables P16 - P31. When high P16 P31 tristated.
Mode control for each data word. Low designates unsigned data input and high designates two's
complement.
"Round" control for rounding of MSP. When high, 1 is added to the most significant bit of LSP. This
signal is affected by the state of FA pin. When FA = 1 and RND = 1, 1 is added to the 2-15 bit (P15). When
RND = 1 and FA = 0, 1 is added to the 2 -16 bit (P14). The RND input is registered. It is clocked on the
rising edge of the logical OR of CLKX and CLKY in the 7216 and on the rising edge of CLK in the 7217.
Rounding always occurs in the positive direction which may introduce a systematic bias.
When low, MSP is output on P16 - P31 lines. When high, LSP is output on P16 - P31.
Format adjust control. When high, a full 32 bit product is selected. When low, a left shifted 31 bit product
is selected with the sign bit replicated in the LSP. FA is normally high, except for certain fractional two's
complement applications (see multiplier input / output formats).
Flow through control. When high, both MSP and LSP registers are by-passed.
CLK
I
7217 X, Y, RND, LSP and MSP register clock input.
CLKX
I
7216 X register clock input. Also clocks RND register.
CLKY
I
7216 Y register clock input. Also clocks RND register.
CLKL
I
7216 LSP register clock input.
CLKM
I
7216 MSP register clock input.
ENX
ENY
I
7217 X register clock enable. Also enables RND register clock.
I
7217 Y register clock enable. Also enables RND register clock.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCC
VTERM
TA
TBIAS
TSTG
IOUT
CAPACITANCE (TA = +25°C, f = 1.0 MHz)
Rating
Commercial
Military
Unit
Power Supply
Voltage
Terminal Voltage
with Respect to
GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
–0.5 to +7.0
–0.5 to +7.0
V
VCC + 0.5
VCC + 0.5
V
0 to +70
–55 to +125
°C
–55 to +125
–65 to +135
°C
–55 to +125
–65 to +150
°C
50
50
mA
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
10
pF
COUT
Output Capacitance
VOUT = 0V
12
pF
NOTE:
2580 tbl 04
1. This parameter is measured at characterization and not tested.
NOTE:
2580 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
EL
11.3
5
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Commercial
Symbol
Parameter
Test
Conditions(1)
Min.
Typ.(1)
Military
Max.
Min.
Typ.(1)
Max.
Unit
VIH
Input High Voltage
Guaranteed Logic High Level
2.0
—
—
2.0
—
—
V
VIL
Input Low Voltage
Guaranteed Logic Low Level
—
—
0.8
—
—
0.8
V
|ILI|
Input Leakage Current
VCC = Max., VIN = 0 to VCC
—
—
10
—
—
10
µA
|ILO|
Output Leakage Current
—
—
10
—
—
10
µA
ICC
Operating Power Supply Current
—
40
80
—
40
100
mA
ICCQ1
Quiescent Power Supply Current
VCC = Max., OE = 2.0V
VOUT = 0 to VCC
VCC = Max., Outputs Disabled
f = 10MHz(2)
VIN ≥ VIH, VIN ≤ VIL
—
20
40
—
20
50
mA
ICCQ2
Quiescent Power Supply Current
VIN ≥ VCC – 0.2V, VIN ≤ 0.2V
—
4
20
—
4
25
mA
ICC/f (2,3) Increase in Power Supply
Current
VOH
Output HIGH Voltage
VCC = Max., Outputs Disabled
—
—
4
—
—
6
VCC = Min., IOH = –2.0mA
2.4
—
—
2.4
—
—
mA/
MHz
V
VOL(4)
Output LOW Voltage
VCC = Min., IOL = 8mA
—
—
0.4
—
—
0.4
V
IOS
Output Short Circuit Current
VCC = Max., VO = GND
-20
—
-120
-20
—
-120
mA
NOTES:
2580 tbl 03
1. Typical implies VCC = 5V and TA = +25°C.
2. ICC is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range:
ICC = 80+ 4(f –10)mA; for the military range, ICC = 100 + 6(f –10). f = operating frequency in MHz, f = 1/tMUC for IDT7216 and f = 1/tMC for IDT7217.
3. For frequencies greater than 10MHz, guaranteed by design, not production tested.
4. IOL = 4mA for tMC >65ns.
11.3
6
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS COMMERCIAL (VCC = 5V ± 10%, TA = 0° to +70°C)
Symbol
Parameter
tMUC
tMC
tS
tH
tPWH
tPWL
tPDSEL
tPDP
tPDY
tENA
tDIS
tS
tH
tHCL
Time(4)
Symbol
tMUC
tMC
tS
tH
tPWH
tPWL
tPDSEL
tPDP
tPDY
tENA
tDIS
tS
tH
tHCL
7216L16 (5)
7217L16
Min.
Max.
Unclocked Multiply
Clocked Multiply Time(4)
X, Y, RND Set-up Time
X, Y, RND Hold Time
Clock Pulse Width High
Clock Pulse Width Low
MSPSEL to Product Out(4)
Output Clock to P (4)
Output Clock to Y (4)
3-State Enable Time
3-State Disable Time(2)
Clock Enable Set-up Time (IDT7217 only)
Clock Enable Hold Time (IDT7217 only)
Clock Low Hold Time CLKXY
Relative to CLKML (IDT7216 only)(1,3)
2
2
10
1
7
7
2
2
2
—
—
9
0
0
25
16
—
—
—
—
15
15
15
15
15
—
—
—
7216L20
7217L20
Min.
Max.
2
2
11
1
9
9
2
2
2
—
—
10
0
0
30
20
—
—
—
—
18
18
18
18
18
—
—
—
7216L45
7217L45
Min.
Max.
Parameter
Unclocked Multiply Time(4)
Clocked Multiply Time(4)
X, Y, RND Set-up Time
X, Y, RND Hold Time
Clock Pulse Width High
Clock Pulse Width Low
MSPSEL to Product Out(4)
Output Clock to P (4)
Output Clock to Y (4)
3-State Enable Time
3-State Disable Time(2)
Clock Enable Set-up Time (IDT7217 only)
Clock Enable Hold Time (IDT7217 only)
Clock Low Hold Time CLKXY Relative to CLKML
(IDT7216 only) (1,3)
2
2
15
3
15
15
2
2
2
—
—
10
3
0
7216L25
7217L25
Min.
Max.
65
45
—
—
—
—
25
25
25
25
22
—
—
—
2
2
12
2
10
10
2
2
2
—
—
10
2
0
38
25
—
—
—
—
20
20
20
20
20
—
—
—
7216L55
7217L55
Min.
Max.
2
2
20
3
15
20
2
2
2
—
—
10
3
0
75
55
—
—
—
—
25
30
30
30
25
—
—
—
7216L35
7217L35
Min.
Max.
2
2
12
3
10
10
2
2
2
—
—
10
3
0
55
35
—
—
—
—
25
25
25
25
22
—
—
—
7216L65
7217L65
Min.
Max.
2
2
20
3
15
20
2
2
2
—
—
10
3
0
85
65
—
—
—
—
30
30
30
35
25
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
2580 tbl 06
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured ±500mV from steady state voltage.
3. Guaranteed by design, not production tested.
4. Minimum propagation delay times are guaranteed, not production tested.
5. This speed is available in PGA and PLCC packages only.
11.3
7
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS MILITARY (VCC = 5V ± 10%, TA = –55° to +125°C)
Symbol
Parameter
tMUC
tMC
tS
tH
tPWH
tPWL
tPDSEL
tPDP
tPDY
tENA
tDIS
tS
tH
tHCL
Time(4)
Symbol
tMUC
tMC
tS
tH
tPWH
tPWL
tPDSEL
tPDP
tPDY
tENA
tDIS
tS
tH
tHCL
7216L20 (5)
7217L20
Min.
Max.
Unclocked Multiply
Clocked Multiply Time(4)
X, Y, RND Set-up Time
X, Y, RND Hold Time
Clock Pulse Width High
Clock Pulse Width Low
MSPSEL to Product Out(4)
Output Clock to P (4)
Output Clock to Y (4)
3-State Enable Time
3-State Disable Time(2)
Clock Enable Set-up Time (IDT7217 only)
Clock Enable Hold Time (IDT7217 only)
Clock Low Hold Time CLKXY Relative to
CLKML (IDT7216 only)(1,3)
2
2
11
1
9
9
2
2
2
—
—
10
0
0
30
30
—
—
—
—
18
18
18
18
20
—
—
—
7216L25
7217L25
Min.
Max.
2
2
12
2
10
10
2
2
2
—
—
10
2
0
38
25
—
—
—
—
20
20
20
20
22
—
—
—
7216L55
7217L55
Min.
Max.
Parameter
Time(4)
Unclocked Multiply
Clocked Multiply Time(4)
X, Y, RND Set-up Time
X, Y, RND Hold Time
Clock Pulse Width High
Clock Pulse Width Low
MSPSEL to Product Out(4)
Output Clock to P (4)
Output Clock to Y (4)
3-State Enable Time
3-State Disable Time(2)
Clock Enable Set-up Time (IDT7217 only)
Clock Enable Hold Time (IDT7217 only)
Clock Low Hold Time CLKXY Relative to CLKML
(IDT7216 only) (1,3)
2
2
20
3
15
15
2
2
2
—
—
15
3
0
7216L30
7217L30
Min.
Max.
75
55
—
—
—
—
30
30
30
25
25
—
—
—
2
2
12
2
10
10
2
2
2
—
—
10
2
0
43
30
—
—
—
—
20
20
20
20
22
—
—
—
7216L65
7217L65
Min.
Max.
2
2
25
3
15
15
2
2
2
—
—
15
3
0
85
65
—
—
—
—
35
30
30
35
25
—
—
—
7216L40
7217L40
Min.
Max.
2
2
15
3
15
15
2
2
2
—
—
12
3
0
60
40
—
—
—
—
25
25
25
25
25
—
—
—
7216L75
7217L75
Min.
Max.
2
2
25
3
15
15
2
2
2
—
—
15
3
0
95
75
—
—
—
—
35
35
35
40
25
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
2580 tbl 07
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured ±500mV from steady state voltage.
3. Guaranteed by design, not production tested.
4. Minimum propagation delay times are guaranteed, not production tested.
5. This speed is available in PGA and Flatpack packages only.
11.3
8
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tPWH
CLKX
CLKY
tS
tHCL
tH
tPWL
INPUT X1, Y1,
RND
tMC
CLKM
CLKL
tPDY
OUTPUT Y
CLKM
CLKL
tPDSEL
MSPSEL
tPDP
OUTPUT P
tMUC
2580 drw 13
Figure 4. IDT7216 Timing Diagram
tPWH
CLK
tS
tH
tS
tH
tPWL
ENX
ENY
X1, Y1,
RND
tS
tH
ENP
tMC
tPDY
OUTPUT Y
tPDSEL
MSPSEL
tPDP
OUTPUT P
tMUC
2580 drw 14
Figure 5. IDT7217 Timing Diagram
11.3
9
2
–1
11.3
=
X
2
–2
0
2
–1
2
–2
X8
X7
X6
X5
X4
X3
X2
X1
X0
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2 –14 2 –15
Y9
DIGITAL VALUE
SIGNAL
DIGITAL VALUE
SIGNAL
0
2
–1
2
–2
–2
1
2
0
Y9
2–7
Y15 Y14 Y13 Y12 Y11 Y10
2–1 2–2
MSP
P9
2–4
–8
2
Y8
–8
2
X8
MSP
–9
2
Y7
–9
2
X7
X5
X4
X3
X2
X1
X0
Y5
Y4
Y3
Y2
Y1
Y0
2–10 2–11 2–12 2–13 2–14 2–15 2–16
Y6
2–10 2–11 2–12 2–13 2–14 2–15 2–16
X6
DIGITAL VALUE
SIGNAL
DIGITAL VALUE
SIGNAL
Figure 6. Fractional Two’s Complement Notation
–2
2
P8
–3
2
2–4
2–5
–6
2
2–7
–9
2
MSP
–8
2
P6
P5
P4
P3
P2
P1
P0
P7
P6
LSP
P5
P4
P3
P2
P1
P0
P8
P7
P6
P5
P4
P3
P2
P1
Figure 7. Fractional Unsigned Magnitude Notation
LSP
FA = 0
DIGITAL VALUE
SIGNAL
P0
2580 drw 16
2580 drw17
MANDATORY
FA = 1
DIGITAL VALUE
SIGNAL
FA = 1
DIGITAL VALUE
SIGNAL
2–10 2–11 2–12 2–13 2–14 2–15 2–16 2–17 2–18 2–19 2–20 2–21 2–22 2–23 2–24 2–25 2–26 2–27 2–28 2–29 2–30 2–31 2–32
P9
LSP
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10
–3
2
2–5 2–6
2–7
2–4
2–5 2–6
–3
2–1 2–2
2
X9
–1
P7
2 –1 2 –2 2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2 –14 2 –15 2 –16 2 –17 2 –18 2 –19 2 –20 2–21 2 –22 2 –23 2–24 2 –25 2–26 2 –27 2 –28 2 –29 2 –30
X15 X14 X13 X12 X11 X10
–2
P8
2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2 –14 2 –15 –2 0 2 –16 2 –17 2 –18 2 –19 2 –20 2 –21 2 –22 2 –23 2–24 2–25 2–26 2 –27 2 –28 2 –29 2 –30
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10
–2
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9
–2
X9
2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2 –14 2 –15
Y15 Y14 Y13 Y12 Y11 Y10
0
BINARY POINT
=
*=
X
–2
X15 X14 X13 X12 X11 X10
BINARY POINT
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
10
11.3
=
*=
=
X9
X8
X7
X6
X5
X4
X3
X2
X1 X0
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
2 –1 2 –2 2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2–14 2 –15 2 –16
Y15 Y14 Y13 Y12 Y11 Y10
0
2
–1
2
–2
MSP
X
2
9
Y9
14
13
11
210
–215 2
2
212 2
Y15 Y14 Y13 Y12 Y11 Y10
29
2
27
228 2
226 225
224
MSP
223
22
2
221
20
2
219
218
217
216
215 –230 214 213
12
2
10
211 2
31
29
230 2
P7
P6
P5
P4
P3
228 227 226 225
MSP
224
223
22
2
21
2
20
2
219
217
216 215
214 213
12
2
10
211 2
9
2
Figure 9. Integer Two’s Complement Notation
18
2
8
27
P7
LSP
28
P8
LSP
27
P7
P8
28
27
Y7
27
X7
8
2
Y8
2
X8
LSP
5
2
24
26
P6
26
P6
26
5
25
P5
25
P5
2
4
2
P4
4
2
P4
24
Y6 Y5 Y4
26
X6 X5 X4
P2
3
2
P3
3
2
P3
22
P2
22
P2
2
Y2
22
X2
23 2
Y3
23
X3
* In this format an overflow occurs in the attempted multiplication of the two's complement number 1,000 . . . 0 with 1,000.0 yielding an erroneous
30
product of –1 in the fraction case and –2 in the integer case.
–2
P9
9
2
P9
14
13
11
2 10 2 9
–215 2
2
2 12 2
X9
X15 X14 X13 X12 X11 X10
Figure 8. Fractional Mixed Mode Notation
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10
30
–2
P8
P1
P0
SIGNAL
1
2
P1
1
2
P1
21
Y1
21
0
0
0
2
P0
0
2
P0
2
Y0
2
X1 X0
FA = 1
2580 drw 19
DIGITAL VALUE
SIGNAL
FA = 0
DIGITAL VALUE
SIGNAL
DIGITAL VALUE
SIGNAL
DIGITAL VALUE
SIGNAL
BINARY POINT
2580 drw 18
MANDATORY
FA = 1
2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2 –14 2 –15 2 –16 2 –17 2 –18 2 –19 2 –20 2 –21 2 –22 2 –23 2–24 2–25 2–26 2 –27 2 –28 2 –29 2 –30 2 –31 DIGITAL VALUE
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10
–2
P9
SIGNAL
(UNSIGNED MAGNITUDE)
DIGITAL VALUE
SIGNAL
(TWO'S COMPLEMENT)
DIGITAL VALUE
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10
X
-2 0 2 –1 2 –2 2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2 –14 2 –15
X15 X14 X13 X12 X11 X10
BINARY POINT
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
11
Y9
11.3
224
MSB
23
2
22
2
221
220
217
216 215
214 213
212
211
10
2
X
–2
31
MSB
2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 23 2 22 221 220
213
212
11
2
10
2
Figure 11. Integer Mixed Mode Notation
2 19 218 2 17 2 16 2 15 2 14 2 13 2 12 2 11 2 10 2 9
14
2
Y8
Y9
Y15 Y14 Y13 Y12 Y11 Y10
215
28
29
–215 2 14 2 13 2 12 2 11 2 10
X8
X9
X15 X14 X13 X12 X11 X10
8
7
7
27
P7
2
Y7
2
27
Y6
2
6
P6
26
7
5
5
2
5
P5
2
Y5
2
X5
P7
2
X6
26
7
Y7
2
X7
LSP
8
2
P8
28
Y8
28
X8
X7
LSP
2
9
2
Figure 10. Integer Unsigned Magnitude Notation
219 218
P8
25
2
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9
227 226
28
28
2
29
29
2
P9
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10
231 230
29
2
Y15 Y14 Y13 Y12 Y11 Y10
11
2
215 2 14 2 13 2 12 2 11 2 10
X
212
29
213
10
14
215
2
X9
X15 X14 X13 X12 X11 X10
24
Y4
24
X4
24
P4
6
2
P6
26
Y6
26
5
5
2
3
2
3
P3
3
2
Y3
2
X3
5
P5
2
Y5
2
2
2
2
P2
2
2
Y2
2
X2
24
P4
24
Y4
24
X6 X5 X4
3
2
2
2
2
P2
2
Y2
2
X2
21
P1
21
Y1
21
20
P0
20
Y0
20
X1 X0
20
X0
21
P1
21
20
P0
20
Y1 Y0
21
X1
2580 drw 20
MANDATORY
FA = 1
DIGITAL VALUE
SIGNAL
DIGITAL VALUE
SIGNAL
DIGITAL VALUE
SIGNAL
2580 drw 21
MANDATORY
FA = 1
DIGITAL VALUE
SIGNAL
SIGNAL
(UNSIGNED MAGNITUDE)
DIGITAL VALUE
SIGNAL
(TWO'S COMPLEMENT)
DIGITAL VALUE
BINARY POINT
3
2
P3
2
Y3
3
2
X3
BINARY POINT
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
12
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
VCC
7.0V
500Ω
Pulse
Generator
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
V OUT
VIN
GND to 3.0V
Input Rise/Fall Times
1.5V
Output Load
D.U.T.
See Figure 1
2580 tbl 08
50pF
RT
SWITCH POSITION
500Ω
CL
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Figure 12. AC Test Load Circuit
DEFINITIONS:
2580 tbl 09
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
VCC
ESD
PROTECTION
I OH
IIH
INPUTS
IIL
OUTPUTS
R
I OL
Figure 13. Input Interface Circuit
Figure 14. Output Interface Circuit
ORDERING INFORMATION
IDT
XXXX
Device Type
X
Power
X
Speed
X
Package
X
Process/
Temperature
Range
Blank
B
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
C
J
F
G
Topbraze DIP
Plastic Leaded Chip Carrier
Flatpack
Pin Grid Array
16
20
25
35
45
55
65
20
25
30
Commercial (tMC)
40
55
65
75
L
Low Power
7216
7217
16 x 16 Multiplier
Military (tMC)
2580 drw 22
11.3
13
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