ON MC74HCT74AN Dual d flip-flop with set and reset with lsttl compatible input Datasheet

MC74HCT74A
Dual D Flip-Flop with Set
and Reset with LSTTL
Compatible Inputs
High–Performance Silicon–Gate CMOS
http://onsemi.com
The MC74HCT74A is identical in pinout to the LS74. This device
may be used as a level converter for interfacing TTL or NMOS outputs
to High Speed CMOS inputs.
This device consists of two D flip–flops with individual Set, Reset,
and Clock inputs. Information at a D–input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip–flop. The Set
and Reset inputs are asynchronous.
•
•
•
•
•
•
•
MARKING
DIAGRAMS
14
PDIP–14
N SUFFIX
CASE 646
1
14
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 136 FETs or 34 Equivalent Gates
SOIC–14
D SUFFIX
CASE 751A
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
1
2
5
3
6
PIN ASSIGNMENT
RESET 1
1
14
DATA 1
2
13
VCC
RESET 2
CLOCK 1
3
12
DATA 2
SET 1
4
11
CLOCK 2
SET 2
Q1
Q1
5
10
6
9
Q2
GND
7
8
Q2
FUNCTION TABLE
PIN 14 = VCC
PIN 7 = GND
13
Inputs
Outputs
Set Reset Clock Data
12
9
11
8
Q2
Q2
10
Design Criteria
Value
Units
Internal Gate Count*
34
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
µW
.0075
pJ
Speed Power Product
*Equivalent to a two–input NAND gate.
 Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 8
Q1
Q1
4
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SET 2
HCT74A
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
LOGIC DIAGRAM
RESET 1
MC74HCT74AN
AWLYYWW
1
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
L
H
X
X
X
H
L
X
X
X
Q
Q
H
L
L
H
H*
H*
H
L
L
H
No Change
No Change
No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously.
ORDERING INFORMATION
Package
Shipping
MC74HCT74AN
Device
PDIP–14
2000 / Box
MC74HCT74AD
SOIC–14
55 / Rail
MC74HCT74ADR2
SOIC–14
2500 / Reel
Publication Order Number:
MC74HCT74A/D
MC74HCT74A
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MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: –10mW/_C from 65_ to 125_C
SOIC Package: –7mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or VIL
|Iout|
4.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout|
4.0 mA
4.5
0.26
0.33
0.4
Maximum Input Leakage
Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
µA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
5.5
2.0
20
80
µA
∆ICC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND,
GND Other In
Inputs
uts
lout = 0 µA
VOH
VOL
Iin
Maximum Low–Level Output
Voltage
5.5
≥ – 55_C
25_C to 125_C
2.9
2.4
V
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
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2
MC74HCT74A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to
25_C
v 85_C
v 125_C
Unit
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Symbol
Parameter
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
24
30
36
ns
tPLH,
tPHL
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
24
30
36
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
15
19
22
ns
Maximum Input Capacitance
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Enabled Output)*
pF
32
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to
25_C
Symbol
Parameter
Fig.
Min
Max
85_C
Min
Max
125_C
Min
Max
Units
tsu
Minimum Setup Time, Data to Clock
3
15
19
22
ns
th
Minimum Hold Time, Clock to Data
3
3
3
3
ns
Minimum Recovery Time, Set or Reset Inactive to Clock
2
6
8
9
ns
tw
Minimum Pulse Width, Clock
1
15
19
22
ns
tw
Minimum Pulse Width, Set or Reset
2
15
19
22
ns
tr, tf
Maximum Input Rise and Fall Times
1
trec
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3
500
500
500
ns
MC74HCT74A
SWITCHING WAVEFORMS
tw
tr
CLOCK
3V
tf
SET OR
RESET
3V
2.7 V
1.3 V
0.3 V
1.3 V
GND
tPHL
GND
Q OR Q
tw
1.3 V
1/fmax
tPLH
Q OR Q
tPLH
tPHL
1.3 V
Q OR Q
trec
90%
1.3 V
10%
3V
1.3 V
CLOCK
tTLH
tTHL
GND
Figure 1.
Figure 2.
VALID
TEST POINT
3V
DATA
1.3 V
OUTPUT
GND
tsu
DEVICE
UNDER
TEST
th
3V
1.3 V
CL*
GND
CLOCK
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
EXPANDED LOGIC DIAGRAM
SET
4, 10
2, 12
5, 9
Q
DATA
3, 11
CLOCK
6, 8
Q
1, 13
RESET
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4
MC74HCT74A
PACKAGE DIMENSIONS
PDIP–14
N SUFFIX
CASE 646–06
ISSUE L
14
8
1
7
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
B
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
J
N
H
G
D
SEATING
PLANE
K
M
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
SOIC–14
D SUFFIX
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
8
–B–
1
P 7 PL
0.25 (0.010)
7
G
B
M
M
R X 45 _
C
F
–T–
SEATING
PLANE
D 14 PL
0.25 (0.010)
M
K
M
T B
S
A
S
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5
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
MC74HCT74A
Notes
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6
MC74HCT74A
Notes
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7
MC74HCT74A
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Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: [email protected]
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor – European Support
German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)
Email: ONlit–[email protected]
French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)
Email: ONlit–[email protected]
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)
Email: [email protected]
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
*Available from Germany, France, Italy, England, Ireland
CENTRAL/SOUTH AMERICA:
Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email: ONlit–[email protected]
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Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:
001–800–4422–3781
Email: ONlit–[email protected]
JAPAN: ON Semiconductor, Japan Customer Focus Center
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Phone: 81–3–5740–2745
Email: [email protected]
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
http://onsemi.com
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