3 nV/√Hz, Ultralow Distortion, High Speed Op Amp AD8045 Data Sheet FEATURES CONNECTION DIAGRAMS AD8045 Ultralow distortion SFDR −101 dBc at 5 MHz −90 dBc at 20 MHz −63 dBc at 70 MHz Third-order intercept 43 dBm at 10 MHz Low noise 3 nV/√Hz 3 pA/√Hz High speed 1 GHz, −3 dB bandwidth (G = +1) 1350 V/µs slew rate 7.5 ns settling time to 0.1% Standard and low distortion pinout Supply current: 15 mA Offset voltage: 1.0 mV max Wide supply voltage range: 3.3 V to 12 V TOP VIEW (Not to Scale) NIC 1 8 +VS –IN 3 6 NIC +IN 4 5 –VS 04814-0-001 7 OUTPUT FEEDBACK 2 NOTES 1. NIC = NO INTERNAL CONNECTION. Figure 1. 8-Lead AD8045 LFCSP (CP-8) AD8045 TOP VIEW (Not to Scale) 8 NIC –IN 2 7 +VS +IN 3 6 OUTPUT –VS 4 5 NIC NOTES 1. NIC = NO INTERNAL CONNECTION. 04814-0-002 FEEDBACK 1 Figure 2. 8-Lead AD8045 SOIC/EP (RD-8) APPLICATIONS Instrumentation IF and baseband amplifiers Active filters ADC drivers DAC buffers The AD8045 features a low distortion pinout for the LFCSP, which improves second harmonic distortion and simplifies the layout of the circuit board. The AD8045 has a 1 GHz bandwidth, a 1350 V/µs slew rate, and settles to 0.1% in 7.5 ns. With a wide supply voltage range (3.3 V to 12 V) and a low offset voltage (200 µV), the AD8045 is an ideal candidate for systems that require high dynamic range, precision, and high speed. The AD8045 amplifier is available in a 3 mm × 3 mm LFCSP and the standard 8-lead SOIC. Both packages feature an exposed Rev. B paddle that provides a low thermal resistance path to the printed circuit board (PCB). This enables more efficient heat transfer and increases reliability. The AD8045 works over the extended industrial temperature range (−40°C to +125°C). –20 G = +1 –30 VS = ±5V VOUT = 2V p-p –40 RL = 1kΩ RS = 100Ω –50 –60 –70 –80 HD3 LFCSP –90 HD2 LFCSP –100 –110 –120 0.1 1 10 FREQUENCY (MHz) 100 04814-0-079 The AD8045 is a unity-gain stable voltage feedback amplifier with ultralow distortion, low noise, and high slew rate. With a spurious-free dynamic range of −90 dBc at 20 MHz, the AD8045 is an ideal solution in a variety of applications, including ultrasound, automated test equipment (ATE), active filters, and analog-todigital converter (ADC) drivers. The Analog Devices, Inc., proprietary next generation XFCB process and innovative architecture enable such high performance amplifiers. HARMONIC DISTORTION (dBc) GENERAL DESCRIPTION Figure 3. Harmonic Distortion vs. Frequency for Various Packages Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8045* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE MATERIALS View a parametric search of comparable parts. Product Selection Guide EVALUATION KITS Tutorials • Universal Evaluation Board for Single High Speed Operational Amplifiers • MT-032: Ideal Voltage Feedback (VFB) Op Amp • High Speed Amplifiers Selection Table DOCUMENTATION • MT-033: Voltage Feedback Op Amp Gain and Bandwidth • MT-047: Op Amp Noise Application Notes • MT-048: Op Amp Noise Relationships: 1/f Noise, RMS Noise, and Equivalent Noise Bandwidth • AN-0993: Active Filter Evaluation Board for Analog Devices, Inc., - Low Distortion Pinout Op Amps • MT-049: Op Amp Total Output Noise Calculations for Single-Pole System • AN-402: Replacing Output Clamping Op Amps with Input Clamping Amps • MT-050: Op Amp Total Output Noise Calculations for Second-Order System • AN-417: Fast Rail-to-Rail Operational Amplifiers Ease Design Constraints in Low Voltage High Speed Systems • MT-052: Op Amp Noise Figure: Don't Be Misled • AN-581: Biasing and Decoupling Op Amps in Single Supply Applications Data Sheet • AD8045: 3 nV/√Hz Ultra Low Distortion, High Speed Op Amp Data Sheet User Guides • UG-084: Evaluation Board for Single, High Speed Operational Amplifiers (8-Lead, SOIC with Dedicated Feedback Pin and Exposed Paddle) • UG-919: Universal Evaluation Board for Single, 8-Lead LFCSP Operational Amplifiers TOOLS AND SIMULATIONS • Analog Filter Wizard • Analog Photodiode Wizard • Power Dissipation vs Die Temp • VRMS/dBm/dBu/dBV calculators • AD8045 SPICE Macro Model • MT-053: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR • MT-056: High Speed Voltage Feedback Op Amps • MT-058: Effects of Feedback Capacitance on VFB and CFB Op Amps • MT-059: Compensating for the Effects of Input Capacitance on VFB and CFB Op Amps Used in Current-toVoltage Converters • MT-060: Choosing Between Voltage Feedback and Current Feedback Op Amps DESIGN RESOURCES • AD8045 Material Declaration • PCN-PDN Information • Quality And Reliability • Symbols and Footprints DISCUSSIONS View all AD8045 EngineerZone Discussions. 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AD8045 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Frequency Response .................................................................. 17 Applications ....................................................................................... 1 DC Errors .................................................................................... 17 Connection Diagrams ...................................................................... 1 Output Noise ............................................................................... 18 General Description ......................................................................... 1 Applications Information .............................................................. 19 Revision History ............................................................................... 2 Low Distortion Pinout ............................................................... 19 Specifications with ±5 V Supply ..................................................... 3 High Speed ADC Driver ........................................................... 19 Specifications with +5 V Supply ..................................................... 4 90 MHz Active Low-Pass Filter (LPF) ..................................... 20 Absolute Maximum Ratings............................................................ 5 Printed Circuit Board Layout ....................................................... 22 Thermal Resistance ...................................................................... 5 Signal Routing............................................................................. 22 ESD Caution .................................................................................. 5 Power Supply Bypassing ............................................................ 22 Pin Configurations and Function Descriptions ........................... 6 Grounding ................................................................................... 22 Typical Performance Characteristics ............................................. 7 Exposed Paddle........................................................................... 23 Circuit Configurations ................................................................... 16 Driving Capacitive Loads .......................................................... 23 Wideband Operation ................................................................. 16 Outline Dimensions ....................................................................... 24 Theory of Operation ...................................................................... 17 Ordering Guide .......................................................................... 24 REVISION HISTORY 5/2016—Rev. A to Rev. B Changed CP-8-2 to CP-8-13 ........................................ Throughout Changes to Figure 1 and Figure 2 ................................................... 1 Changes to Figure 5, Figure 6, and Table 5 ................................... 6 Deleted Table 6; Renumbered Sequentially .................................. 6 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 9/2004—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Specifications Section .................................................. 4 Changes to Figure 58 ...................................................................... 15 Changes to Figure 63 ...................................................................... 17 Changes to Frequency Response Section .................................... 17 Changes to Figure 64 ...................................................................... 17 Changes to DC Errors Section ...................................................... 17 Changes to Figure 65 ...................................................................... 17 Changes to Figure 66 ...................................................................... 18 Changes to Output Noise Section ................................................ 18 Changes to Ordering Guide .......................................................... 24 7/2004—Revision 0: Initial Version Rev. B | Page 2 of 24 Data Sheet AD8045 SPECIFICATIONS WITH ±5 V SUPPLY TA = 25°C, G = +1, RS = 100 Ω, RL = 1 kΩ to ground, unless noted otherwise. The exposed paddle must be left floating or connected to −VS. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Harmonic Distortion (dBc) HD2/HD3 Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Positive Power Supply Rejection Negative Power Supply Rejection Test Conditions/Comments G = +1, VOUT = 0.2 V p-p G = +1, VOUT = 2 V p-p G = +2, VOUT = 0.2 V p-p G = +2, VOUT = 2 V p-p, RL = 150 Ω G = +1, VOUT = 4 V step G = +2, VOUT = 2 V step Min 300 320 1000 fC = 5 MHz, VOUT = 2 V p-p LFCSP SOIC fC = 20 MHz, VOUT = 2 V p-p LFCSP SOIC fC = 70 MHz, VOUT = 2 V p-p LFCSP SOIC f = 100 kHz f = 100 kHz NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 150 Ω Typ Max Unit 1000 350 400 55 1350 7.5 MHz MHz MHz V/µs ns −102/−101 −106/−101 dBc dBc −98/−90 −97/−90 dBc dBc −71/−71 −60/−71 3 3 0.01 0.01 dBc dBc nV/√Hz pA/√Hz % Degrees 62 0.2 8 2 8 0.2 64 VCM = ±1 V −83 3.6/1.0 1.3 ±3.8 −91 MΩ pF V dB VIN = ±3 V, G = +2 RL = 1 kΩ RL = 100 Ω −3.8 to +3.8 −3.4 to +3.5 8 −3.9 to +3.9 −3.6 to +3.6 70 90/170 18 ns V V mA mA pF See Figure 54 VOUT = −3 V to +3 V Common-mode/differential Common-mode Sinking/sourcing 30% overshoot, G = +2 ±1.65 +VS = +5 V to +6 V, −VS = −5 V +VS = +5 V, −VS = −5 V to −6 V Rev. B | Page 3 of 24 −61 −66 ±5 16 −68 −73 1.0 6.3 1.3 ±6 19 mV µV/°C µA nA/°C µA dB V mA dB dB AD8045 Data Sheet SPECIFICATIONS WITH +5 V SUPPLY TA = 25°C, G = +1, RS = 100 Ω, RL = 1 kΩ to midsupply, unless otherwise noted. Exposed paddle must be floating or connected to −VS. Table 2. Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Harmonic Distortion (dBc) HD2/HD3 Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Positive Power Supply Rejection Negative Power Supply Rejection Test Conditions/Comments G = +1, VOUT = 0.2 V p-p G = +1, VOUT = 2 V p-p G = +2, VOUT = 0.2 V p-p G = +2, VOUT = 2 V p-p, RL = 150 Ω G = +1, VOUT = 2 V step G = +2, VOUT = 2 V step Min 160 320 480 fC = 5 MHz, VOUT = 2 V p-p LFCSP SOIC fC = 20 MHz, VOUT = 2 V p-p LFCSP SOIC fC = 70 MHz, VOUT = 2 V p-p LFCSP SOIC f = 100 kHz f = 100 kHz NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 150 Ω Typ Max Unit 900 200 395 60 1060 10 MHz MHz MHz MHz V/µs ns −89/−83 −92/−83 dBc dBc −81/−70 −83/−70 dBc dBc −57/−46 −57/−46 3 3 0.01 0.01 dBc dBc nV/√Hz pA/√Hz % Degrees 61 0.5 7 2 7 0.2 63 VCM = 2 V to 3 V −78 3/0.9 1.3 1.2 to 3.8 −94 MΩ pF V dB VIN = −0.5 V to +3 V, G = +2 RL = 1 kΩ RL = 100 Ω 2.2 to 3.7 2.5 to 3.5 10 1.1 to 4.0 1.2 to 3.8 55 70/140 15 ns V V mA mA pF See Figure 54 VOUT = 2 V to 3 V Common-mode/differential Common-mode Sinking/sourcing 30% overshoot, G = +2 3.3 +VS = +5 V to +6 V, −VS = 0 V +VS = +5 V, −VS = 0 V to −1 V Rev. B | Page 4 of 24 −65 −70 5 15 −67 −73 1.4 6.6 1.3 12 18 mV µV/°C µA nA/°C µA dB V mA dB dB Data Sheet AD8045 ABSOLUTE MAXIMUM RATINGS PD = Quiescent Power + (Total Drive Power – Load Power) Table 3. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions; that is, θJA is specified for the device soldered in the circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type SOIC LFCSP θJA 80 93 θJC 30 35 Unit °C/W °C/W Maximum Power Dissipation The maximum safe power dissipation for the AD8045 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8045. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in silicon devices, potentially causing degradation or loss of functionality. V V PD = (VS × I S ) + S × OUT RL 2 VOUT 2 – RL RMS output voltages should be considered. If RL is referenced to −VS, as in single-supply operation, the total drive power is VS × IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply. PD = (VS × I S ) + (VS / 4 )2 RL In single-supply operation with RL referenced to −VS, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads and exposed paddle from metal traces, through holes, ground, and power planes reduces θJA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the exposed paddle SOIC (80°C/W) and LFCSP (93°C/W) package on a JEDEC standard 4-layer board. θJA values are approximations. 4.0 3.5 3.0 2.5 2.0 1.5 SOIC 1.0 LFCSP 0.5 0.0 –40 –20 0 20 40 60 80 AMBIENT TEMPERATURE (°C) 100 120 04814-0-080 Rating 12.6 V See Figure 4 −VS − 0.7 V to +VS + 0.7 V ±VS −VS −65°C to +125°C −40°C to +125°C 300°C 150°C MAXIMUM POWER DISSIPATION (Watts) Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Exposed Paddle Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the AD8045 drive at the output. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Rev. B | Page 5 of 24 AD8045 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS –IN 2 AD8045 8 NIC NIC 1 7 +VS FEEDBACK 2 TOP VIEW 6 OUTPUT (Not to Scale) 5 NIC –VS 4 +IN 3 +IN 4 TOP VIEW (Not to Scale) 7 OUTPUT 6 NIC 5 –VS NOTES 1. NIC = NO INTERNAL CONNECTION. 2. THE EXPOSED PADDLE MUST BE CONNECTED TO −VS OR LEFT ELECTRICALLY ISOLATED (FLOATING). 04814-0-003 NOTES 1. NIC = NO INTERNAL CONNECTION. 2. THE EXPOSED PADDLE MUST BE CONNECTED TO −VS OR LEFT ELECTRICALLY ISOLATED (FLOATING). –IN 3 8 +VS AD8045 Figure 5. 8-Lead SOIC Pin Configuration 04814-0-004 FEEDBACK 1 Figure 6 . 8-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No. SOIC LFCSP 1 2 2 3 3 4 4 5 5, 8 1, 6 6 7 7 8 Mnemonic FEEDBACK −IN +IN −VS NIC OUTPUT +VS EPAD Description Feedback Pin. Inverting Input. Noninverting Input. Negative Supply. No Internal Connection. Output. Positive Supply. Exposed Paddle. The exposed paddle must be connected to −VS or left electrically isolated (floating). Rev. B | Page 6 of 24 Data Sheet AD8045 TYPICAL PERFORMANCE CHARACTERISTICS 12 VS = ±5V RL = 1k 0 G = +2 11 VS = ±5V RL = 1k 10 R = 499 F G = +2 –2 CLOSED-LOOP GAIN (dB) –1 G = –1 G = +10 –3 –4 –5 7 6 5 5pF 4 0pF 3 10 100 FREQUENCY (MHz) 1000 0 10 4 G = +1 3 VS = ±5V RL = 1k RL = 1k 2 RL = 500 1 0 –1 RL = 100 –2 –3 –4 1000 +125°C –3 –4 100 FREQUENCY (MHz) 1000 Figure 11. Small Signal Frequency Response for Various Temperatures 6.3 G = +2 VS = ±5V RF = 499 6.2 R = 150 L VS = ±2.5V CLOSED-LOOP GAIN (dB) 2 –40°C –2 –6 10 5 3 0 –1 +25°C 04814-0-050 100 FREQUENCY (MHz) Figure 8. Small Signal Frequency Response for Various Loads G = +1 4 RL = 1k RS = 100 1 –5 –5 –6 10 1000 Figure 10. Small Signal Frequency Response for Various Capacitive Loads CLOSED-LOOP GAIN (dB) G = +1 3 VS = ±5V RS = 100 2 100 FREQUENCY (MHz) 04814-0-048 1 4 VS = ±5V 1 0 –1 –2 –3 6.1 VOUT = 2V p-p 6.0 VOUT = 200mV p-p 5.9 5.8 –5 10 100 FREQUENCY (MHz) 1000 04814-0-051 –4 Figure 9. Small Signal Frequency Response for Various Supplies 5.7 1 10 FREQUENCY (MHz) 100 Figure 12. 0.1 dB Flatness vs. Frequency for Various Output Voltages Rev. B | Page 7 of 24 04814-0-039 CLOSED-LOOP GAIN (dB) 8 1 Figure 7. Small Signal Frequency Response for Various Gains CLOSED-LOOP GAIN (dB) 9 04814-0-052 –7 18pF 10pF 2 –6 04814-0-049 NORMALIZED CLOSED-LOOP GAIN (dB) 1 Data Sheet –1 60 OPEN-LOOP GAIN (dB) VS = ±5V –2 –3 –4 VS = ±2.5V –5 –6 –7 –8 100 FREQUENCY (MHz) 1000 04814-0-043 –9 –90 40 –135 30 –180 20 –225 10 –270 0 –315 –10 0.01 RL = 1k –2 –3 –4 RL = 100 –5 –6 –7 –8 1000 04814-0-042 100 FREQUENCY (MHz) HARMONIC DISTORTION (dBc) –1 G = –1 –3 –4 –5 –70 –80 –90 HD3 SOIC AND LFCSP HD2 LFCSP –100 HD2 SOIC 1 10 FREQUENCY (MHz) 100 G = +1 V = ±5V –40 VS = 4V p-p OUT RL = 1k –50 HD2 SOIC HD2 LFCSP –60 –70 HD3 LFCSP AND SOIC –80 –90 –100 –110 10 100 FREQUENCY (MHz) 1000 04814-0-041 NORMALIZED CLOSED-LOOP GAIN (dB) 0 –6 V = ±5V S RF = 499 –7 R = 1k L VOUT = 2V p-p –8 1 –60 –30 G = +2 G = +10 –360 Figure 17. Harmonic Distortion vs. Frequency for Various Packages 1 –2 1000 –50 –120 0.1 Figure 14. Large Signal Frequency Response for Various Loads 2 100 G = +1 –30 VS = ±5V VOUT = 2V p-p –40 RL = 1k RS = 100 –110 –9 –10 10 1 10 FREQUENCY (MHz) –20 HARMONIC DISTORTION (dBc) CLOSED-LOOP GAIN (dB) 0 –1 0.1 Figure 16. Open-Loop Gain and Phase vs. Frequency G = +1 VS = ±5V RS = 100 VOUT = 2V p-p 1 –45 50 Figure 13. Large Signal Frequency Response for Various Supplies 2 0 Figure 15. Large Signal Frequency Response for Various Gains –120 0.1 1 10 FREQUENCY (MHz) 100 Figure 18. Harmonic Distortion vs. Frequency for Various Packages Rev. B | Page 8 of 24 04814-0-028 –10 10 VS = ±5V RL = 1k OPEN-LOOP PHASE (Degrees) 0 CLOSED-LOOP GAIN (dB) 70 G = +1 RL = 1k RS = 100 VOUT = 2V p-p 1 04814-0-030 2 04814-0-064 AD8045 Data Sheet AD8045 –30 HARMONIC DISTORTION (dBc) G = +1 V = ±5V –30 S VOUT = 2V p-p RL = 100 –40 RS = 100 –50 –60 –70 HD2 SOIC –80 –90 HD2 LFCSP 10 FREQUENCY (MHz) 100 HD3 SOIC AND LFCSP 1 10 FREQUENCY (MHz) 100 –40 G = +10 VS = ±5V –50 VOUT = 2V p-p RL = 1k –50 –60 –70 –80 HD2 –90 HD3 10 FREQUENCY (MHz) 100 04814-0-036 1 HD2 SOIC –60 HD2 LFCSP –70 –80 –90 HD3 SOIC AND LFCSP –100 –110 0.1 1 10 FREQUENCY (MHz) 100 04814-0-034 G = –1 V = ±5V –30 S VOUT = 2V p-p RL = 1k –40 SOIC AND LFCSP HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) HD2 LFCSP –90 Figure 22. Harmonic Distortion vs. Frequency for Various Packages –100 Figure 23. Harmonic Distortion vs. Frequency for Various Packages Figure 20. Harmonic Distortion vs. Frequency for Various Packages –30 –50 HARMONIC DISTORTION (dBc) G = –1 VS = ±5V –40 RL = 150 VOUT = 2V p-p –50 HD2 LFCSP –60 HD2 SOIC –80 –90 –100 G = +1 VS = ±5V –60 RL = 1k RS = 100 f = 10MHz –70 HD3 SOIC AND LFCSP –80 –90 –100 HD2 SOIC –110 HD2 LFCSP HD3 SOIC AND LFCSP 1 10 FREQUENCY (MHz) 100 Figure 21. Harmonic Distortion vs. Frequency for Various Packages 04814-0-037 HARMONIC DISTORTION (dBc) –80 –110 0.1 –20 –110 0.1 HD2 SOIC –70 04814-0-033 1 Figure 19. Harmonic Distortion vs. Frequency for Various Packages –70 –60 –100 HD3 SOIC AND LFCSP –110 0.1 –110 0.1 G = +2 VS = ±5V –40 VOUT = 2V p-p RL = 150 R = 499 –50 F –120 0 1 2 3 4 5 6 OUTPUT AMPLITUDE (V p-p) 7 8 04814-0-025 –100 04814-0-032 HARMONIC DISTORTION (dBc) –20 Figure 24. Harmonic Distortion vs. Output Voltage for Various Packages Rev. B | Page 9 of 24 AD8045 Data Sheet –30 HD2 LFCSP HD2 SOIC –80 –90 –100 –60 HD3 SOIC AND LFCSP –70 –80 HD2 LFCSP –90 HD2 SOIC 0 1 2 3 4 5 6 OUTPUT AMPLITUDE (V p-p) 7 8 –100 Figure 25. Harmonic Distortion vs. Output Voltage for Various Packages HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) –70 –80 HD2 –90 HD3 –100 G = +1 VS = ±2.5V –30 VOUT = 2V p-p RL = 100 –40 RS = 100 –50 –60 HD3 SOIC AND LFCSP –70 –80 HD2 LFCSP –90 –110 1 2 3 4 5 6 OUTPUT VOLTAGE (V p-p) 7 8 HD2 SOIC 04814-0-026 0 –100 1 10 FREQUENCY (MHz) 100 Figure 29. Harmonic Distortion vs. Frequency for Various Packages Figure 26. Harmonic Distortion vs. Output Voltage –20 –40 –70 HD2 SOIC HARMONIC DISTORTION (dBc) G = –1 VS = ±5V –50 R = 150 L f = 10MHz –60 HD2 LFCSP –80 –90 HD3 SOIC AND LFCSP –100 G = –1 VS = ±2.5V –30 VOUT = 2V p-p RL = 1k SOIC AND LFCSP –40 –50 –60 HD3 –70 –80 HD2 –90 –110 0 1 2 3 4 5 6 OUTPUT VOLTAGE (V p-p) 7 8 04814-0-027 HARMONIC DISTORTION (dBc) 100 –20 G = –1 VS = ±5V –50 RL = 1k f = 10MHz SOIC AND LFCSP –60 –120 10 FREQUENCY (MHz) Figure 28. Harmonic Distortion vs. Frequency for Various Packages –40 –120 1 –100 0.1 1 10 FREQUENCY (MHz) 100 Figure 30. Harmonic Distortion vs. Frequency for Various Packages Figure 27. Harmonic Distortion vs. Output Voltage Rev. B | Page 10 of 24 04814-0-035 –110 04814-0-024 HD3 SOIC AND LFCSP 04814-0-031 –70 G = +1 VS = ±2.5 V –40 OUT = 2V p-p RL = 1k RS = 100 –50 04814-0-029 G = +1 VS = ±5V R –50 L = 150 RS = 100 f = 10MHz –60 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) –40 Data Sheet –40 0.15 RS = 100 RL = 150 G = +1 0.10 V = ±2.5 S OR VS = ±5V G = +1 VS = +5V RL = 1k RS = 100 f = 10MHz –50 –60 OUTPUT VOLTAGE (V) HARMONIC DISTORTION (dBc) AD8045 HD3 SOIC AND LFCSP –70 –80 –90 HD2 SOIC 0.05 0 –0.05 –0.10 –100 1.0 1.5 2.0 OUTPUT VOLTAGE (V p-p) 2.5 3.0 Figure 31. Harmonic Distortion vs. Output Voltage for Various Packages –0.15 5 10 15 20 25 TIME (ns) Figure 34. Small Signal Transient Response for Various Supplies and Loads –40 0.15 RL = 1k CL = 10pF RSNUB = 30 0.10 V = ±5V S G = +1 HD3 SOIC AND LFCSP –80 –90 0.05 0 –0.05 RSNUB 30 –0.10 –100 HD2 SOIC –110 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 OUTPUT VOLTAGE (V p-p) 2.1 2.3 2.5 Figure 32. Harmonic Distortion vs. Output Voltage for Various Packages 1600 1400 –0.15 0 5 RL 1k 10 15 20 25 TIME (ns) Figure 35. Small Signal Transient Response for Various Supplies and Loads 0.15 POSITIVE SLEW RATE RL = 1k VS = ±5V CL 10pF HD2 LFCSP 04814-0-013 –70 OUTPUT VOLTAGE (V) G = +1 VS = +5V –50 RL = 150 RS = 100 f = 10MHz –60 04814-0-023 HARMONIC DISTORTION (dBc) 0 04814-0-012 –110 0.5 04814-0-022 HD2 LFCSP VS = ±2.5V G = +2 RC = 1k OR RC = 150k 0.10 1200 OUTPUT VOLTAGE (V) 800 600 400 0 –0.05 0 1 2 3 OUTPUT VOLTAGE STEP (V) 4 5 Figure 33. Slew Rate vs. Output Voltage –0.15 0 5 10 15 20 25 TIME (ns) Figure 36. Small Signal Transient Response for Various Loads Rev. B | Page 11 of 24 04814-0-014 0 0.05 –0.10 200 04814-0-076 SLEW RATE (V/s) NEGATIVE SLEW RATE 1000 AD8045 Data Sheet 3 VS = ±5V RL = 1k G = +2 18pF 0.15 2 OUTPUT VOLTAGE (V) 0pF 0.05 0 –0.05 –0.10 –0.15 G = +2 VS = ±5V RL = 1k –0.20 0 5 10 15 20 25 TIME (ns) 10pF 0 25 1 0 –1 –2 10 15 20 25 TIME (ns) –3 G = –1 VS = ±5V RL = 1k 0 5 10 20 25 200 TIME (ns) Figure 38. Large Signal Transient Response for Various Loads Figure 41. Large Signal Transient Response, Inverting 6 RL = 1k RS = 100 G = +1 15 04814-0-019 5 04814-0-016 –2 INPUT AND OUTPUT VOLTAGE (V) VS = ±5V 1 VS = ±2.5V 0 –1 –2 G = +1 5 VS = ±5V f = 5MHz 4 INPUT 3 OUTPUT 2 1 0 –1 –2 –3 –4 –5 –3 0 5 10 15 20 25 TIME (ns) 04814-0-017 OUTPUT VOLTAGE (V) 20 04814-0-061 –1 2 15 2 0 3 10 Figure 40. Large Signal Transient Response with Capacitive Load LOAD = 1k OR 150 0 5 TIME (ns) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0pF –2 3 1 –3 –1 18pF VS = ±5V RS = 100 G = +2 2 0 –4 Figure 37. Small Signal Transient Response with Capacitive Load 3 1 –3 04814-0-015 OUTPUT VOLTAGE (V) 0.10 04814-0-018 0.20 Figure 39. Large Signal Transient Response for Various Supplies –6 0 20 40 60 80 100 120 TIME (ns) 140 160 Figure 42. Input Overdrive Recovery Rev. B | Page 12 of 24 180 Data Sheet AD8045 G = +2 5 VS = ±5V f = 5MHz 4 0 2 × INPUT OUTPUT 1 0 –1 –2 –3 –4 20 40 60 80 100 120 TIME (ns) 140 160 180 200 –30 –PSR –40 +PSR –50 –60 –70 –80 0.01 Figure 43. Output Overdrive Recovery COMMON-MODE REJECTION (dB) 10 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G 04814-0-053 VOLTAGE NOISE (nV/ Hz) –30 100 –50 –60 –70 –80 CLOSED-LOOP INPUT IMPEDANCE () 100M 04814-0-078 CURRENT NOISE (pA/ Hz) 10 10M 1 10 FREQUENCY (MHz) 100 1000 1000 Figure 47. Common-Mode Rejection vs. Frequency 100k 10k 100k 1M FREQUENCY (Hz) 1000 –40 –90 0.1 100 1k 100 VS = ±5V RF = 499 Figure 44. Voltage Noise vs. Frequency 1 100 1 10 FREQUENCY (MHz) Figure 46. Power Supply Rejection vs. Frequency 100 1 10 0.1 04814-0-020 0 04814-0-062 –5 –20 04814-0-054 2 04814-0-045 3 –6 VS = ±5V –10 POWER SUPPLY REJECTION (dB) INPUT AND OUTPUT VOLTAGE (V) 6 Figure 45. Current Noise vs. Frequency VS = ±5V G = +1 10k 1000 100 10 1 10 100 FREQUENCY (MHz) Figure 48. Input Impedance vs. Frequency Rev. B | Page 13 of 24 AD8045 G = +1 VS = ±5V 100 100 VS = ±5V N = 450 X = 50V = 180V 80 COUNT 10 1 0.1 20 1 10 100 FREQUENCY (MHz) 1000 0 –900 –600 Figure 49. Output Impedance vs. Frequency 50 80 46 THIRD-ORDER INTERCEPT (dBm) 0 VOFFSET (V) 300 600 900 Figure 52. VOS Distribution for VS = ±5 V G = +10 VS = ±5V RL = 1k 48 –300 04814-0-063 0.01 60 40 04814-0-055 CLOSED-LOOP OUTPUT IMPEDANCE () 1000 Data Sheet 44 VS = +5V N = 450 X = 540V = 195V 60 COUNT 42 40 38 40 36 20 34 10 20 FREQUENCY (MHz) 30 40 0 –300 0 Figure 50. Third-Order Intercept vs. Frequency 0 0.15 –0.10 0.10 –0.14 –0.16 PHASE 0.05 100 OFFSET VOLTAGE (V) –0.06 –0.20 0 10 1 1500 NUMBER OF 150 LOADS 125 VS = +5V –100 –300 –500 VS = ±5V –700 –900 –0.18 04814-0-021 DIFFERENTIAL GAIN (%) 0.20 –0.12 1200 300 GAIN –0.08 900 500 DIFFERENTIAL PHASE (Degrees) G = +2 VS = ±5V –0.04 600 VOFFSET (V) Figure 53. VOS Distribution for VS = +5 V 0.25 –0.02 300 04814-0-077 5 04814-0-040 30 04814-0-058 32 –1100 –40 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 Figure 54. Offset Voltage vs. Temperature for Various Supplies Figure 51. Differential Gain and Phase vs. Number of 150 Ω Loads Rev. B | Page 14 of 24 Data Sheet AD8045 –1.0 1.5 –1.2 IB–, VS = ±5V –1.6 –1.8 IB+, VS = ±5V –2.0 –2.2 IB–, VS = 5V –2.4 IB+, VS = 5V –2.6 –3.0 –40 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 04814-0-059 –2.8 –1.0 –VS – VOUT 1 LOAD (k) 10 3 2 –VS + VOUT 1.10 VOS (mV) 1 1.05 1.00 +VS – VOUT RL = 150 –3 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 Figure 56. Output Saturation Voltage vs. Temperature for Various Supplies –4 –4 –3 –2 –1 0 VOUT (V) 1 2 3 4 Figure 59. Input Offset Voltage vs. Output Voltage for Various Loads 17.0 0.30 G = +2 VS = ±5V VOUT = 2V p-p RL = 150 RF = 499 0.20 16.5 VS = ±5V 0.10 SETTLING (%) 16.0 VS = 5V 15.5 15.0 0 –0.10 –0.20 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 04814-0-056 14.5 –40 RL = 1k –1 –2 –VS + VOUT +VS – VOUT 0.95 0 04814-0-047 VS = 5V 04814-0-057 OUTPUT SATURATION VOLTAGE (V) –0.5 4 1.15 0.90 –40 SUPPLY CURRENT (mA) VS = +5V Figure 58. Output Saturation Voltage vs. Load for Various Supplies RL = 1k VS = ±5V VS = ±5V 0 –1.5 0.1 Figure 55. Input Bias Current vs. Temperature for Various Supplies 1.20 0.5 –0.30 0 2.5 5.0 7.5 10.0 12.5 TIME (ns) 15.0 17.5 Figure 60. Short Term 0.1% Settling Time Figure 57. Supply Current vs. Temperature for Various Supplies Rev. B | Page 15 of 24 20.0 22.5 04814-0-046 INPUT BIAS CURRENT (A) –1.4 04814-0-044 OUTPUT SATURATION VOLTAGE (V) +VS – VOUT 1.0 AD8045 Data Sheet CIRCUIT CONFIGURATIONS RF WIDEBAND OPERATION The resistor at the output of the amplifier, labeled RSNUB, is used only when driving large capacitive loads. Using RSNUB improves stability and minimizes ringing at the output. For more information, see the Driving Capacitive Loads section. 0.1µF VOUT 0.1µF 10µF + –VS 04814-0-074 VIN RSNUB VIN RSNUB AD8045 Figure 61. Noninverting Configuration Rev. B | Page 16 of 24 VOUT 0.1µF 10µF + Figure 62. Inverting Configuration 10µF + AD8045 0.1µF –VS RG RS 10µF + RG R = RG||RF RF +VS +VS 04814-0-075 Figure 61 and Figure 62 show the recommended circuit configurations for noninverting and inverting amplifiers. In unity-gain (G = +1) applications, RS helps to reduce high frequency peaking. It is not needed for any other configurations. For more information on layout, see the Printed Circuit Board Layout section. Data Sheet AD8045 THEORY OF OPERATION The AD8045 is a high speed voltage feedback amplifier fabricated on the Analog Devices second generation extra fast complementary bipolar (XFCB) process. An H-bridge input stage is used to attain a 1400 V/µs slew rate and low distortion in addition to a low 3 nV/√Hz input voltage noise. Supply current and offset voltage are laser trimmed for optimum performance. RS + VOUT – VIN 04814-0-009 RF RG FREQUENCY RESPONSE The open-loop response of the AD8045 over the frequency can be approximated by the integrator response shown in Figure 63. VIN Figure 64. Noninverting Configuration DC ERRORS Figure 65 shows the dc error contributions. The total output error voltage is VOUT VOUT/VIN (dB) VOUT (ERROR) R +R R +R = − I B + RS G F + I B − R F + VOS G F RG RG VOS RS IB+ fCROSSOVER fCROSSOVER = 400MHz f 10 1 100 FREQUENCY (MHz) 1000 RF RG Figure 63. Open-Loop Response The closed-loop transfer function for the noninverting configuration is shown in Figure 64 and is written as 2 π × f CROSSOVER × (RG + RF ) VOUT = (RF + RG )s + 2 π × f CROSSOVER × RG VIN where: s is (2 πj)f. fCROSSOVER is the frequency where the open-loop gain of the amplifier equals 1 (0 dB). DC gain is therefore VOUT (RG + RF ) = VIN RG Closed-loop −3 dB bandwidth equals VOUT RG = f CROSSOVER × (RG + RF ) VIN 04814-0-010 0 04814-0-008 VOUT/VIN = + VOUT – IB– Figure 65. Amplifier DC Errors The voltage error due to IB+ and IB− is minimized if RS = RF||RG. To include the effects of common-mode and power supply rejection, model VOS as VOS = VOS nom + ∆VS ∆VCM + PSR CMR where: Vos nom is the offset voltage at nominal conditions. ΔVS is the change in the power supply voltage from nominal conditions. PSR is the power supply rejection. CMR is the common-mode rejection. ΔVCM is the change in common-mode voltage from nominal conditions. The closed-loop bandwidth is inversely proportional to the noise gain of the op amp circuit, (RF + RG)/RG. This simple model can be used to predict the −3 dB bandwidth for noise gains above +2. The actual bandwidth of circuits with noise gains at or below +2 is higher due to the influence of other poles present in the real op amp. Rev. B | Page 17 of 24 AD8045 Data Sheet OUTPUT NOISE VOUT _ EN = Figure 66 shows the contributors to the noise at the output of a noninverting configuration. VRS VEN RS (Gn × Ven)2 + (IN + × RS × Gn )2 + (IN − × RF||RG × Gn )2 + 4kTR f + 4kTRG (Gn )2 + 4kTRS (Gn )2 where: R F + RG . RG Gn is the noise gain IEN+ + VOUT – Ven is the op amp input voltage noise. IEN– IN is the op amp input current noise. Table 6 lists the expected output voltage noise spectral density for several gain configurations. RF RG VRG 04814-0-011 VRF Table 6. Noise and Bandwidth for Various Gains Figure 66. Amplifier DC Errors Ven , IN+, and IN− are due to the amplifier. VR F , VRG , and VR S are due to the feedback network resistors, RG and RF, and the source resistor, RS. The total output voltage noise, VOUT _ EN , is the rms sum of all the contributions. Gain +1 +2 +5 +10 −1 1 2 RF 0 499 499 499 499 RG − 499 124 56 499 RS 100 0 0 0 N/A2 RL = 1 kΩ. N/A means not applicable. Rev. B | Page 18 of 24 −3 dB Bandwidth 1 1 GHz 400 MHz 90 MHz 40 MHz 300 MHz Output Noise (nV/√Hz) 3.3 7.4 16.4 31 7.4 Data Sheet AD8045 APPLICATIONS INFORMATION 511Ω 511Ω 33Ω VIN The traditional SOIC pinout has been slightly modified as well to incorporate a dedicated feedback pin. Pin 1, previously a no connect pin on the amplifier, is now a dedicated feedback pin. The new pinout reduces parasitics and simplifies the board layout. HIGH SPEED ADC DRIVER When used as an ADC driver, the AD8045 offers results comparable to transformers in distortion performance. Many ADC applications require that the analog input signal be dc-coupled and operate over a wide frequency range. Under these requirements, operational amplifiers are very effective interfaces to ADCs. An op amp interface provides the ability to amplify and level shift the input signal to be compatible with the input range of the ADC. Unlike transformers, operational amplifiers can be operated over a wide frequency range down to and including dc. 511Ω 511Ω 511Ω 511Ω VINA 20pF 33Ω 511Ω AD9244 VCML + VIN AD8045 511Ω VINB 2.5kΩ 0.1µF 100Ω CML 0.1µF 1µF OP27 Figure 67. High Speed ADC Driver The outputs of the AD8045 devices are centered about the 2.5 V common-mode range of the AD9244. The common-mode reference voltage from the AD9244 is buffered and filtered via the OP27 and fed to the noninverting resistor network used in the level shifting circuit. The spurious-free dynamic range (SFDR) performance is shown in Figure 68. Figure 69 shows a 50 MHz single-tone FFT performance. 120 100 AD8045 80 SFDR (dBc) Existing applications that use the traditional SOIC pinout can take full advantage of the outstanding performance offered by the AD8045. An electrical insulator may be required if the SOIC rests on the ground plane or other metal trace. This is covered in more detail in the Exposed Paddle section of this data sheet. In existing designs, which have Pin 1 tied to ground or to another potential, simply lift Pin 1 of the AD8045 or remove the potential on the Pin 1 solder pad. The designer does not need to use the dedicated feedback pin to provide feedback for the AD8045. The output pin of the AD8045 can still be used to provide feedback to the inverting input of the AD8045. VCML – VIN AD8045 04814-0-066 The AD8045 LFCSP features an Analog Devices new low distortion pinout. The new pinout provides two advantages over the traditional pinout. First, improved second harmonic distortion performance, which is accomplished by the physical separation of the noninverting input pin and the negative power supply pin. Second, the simplification of the layout due to the dedicated feedback pin and easy routing of the gain set resistor back to the inverting input pin. This allows a compact layout, which helps to minimize parasitics and increase stability. This dc-coupled differential driver is best suited for ±5 V operation in which optimum distortion performance is required and the input signal is ground referenced. Figure 67 shows the AD8045 as a dc-coupled differential driver for the AD9244, a 14-bit 65 MSPS ADC. The two amplifiers are configured in noninverting and inverting modes. Both amplifiers are set with a noise gain of +2 to provide better bandwidth matching. The inverting amplifier is set for a gain of –1, while the noninverting is set for a gain of +2. The noninverting input is divided by 2 in order to normalize its output and make it equal to the inverting output. Rev. B | Page 19 of 24 60 40 20 0 1 10 INPUT FREQUENCY (MHz) Figure 68. SFDR vs. Frequency 100 04814-0-067 LOW DISTORTION PINOUT AD8045 Data Sheet 0 –20 –40 fc = –60 1 2πRC The quality factor, or Q, is shown in the equation –80 Q= –100 1 3−K 5 10 20 15 FREQUENCY (MHz) 25 30 Figure 69. Single-Tone FFT, FIN = 50 MHz, Sample Rate = 65 MSPS Shown in the First Nyquist Zone 90 MHZ ACTIVE LOW-PASS FILTER (LPF) Active filters are used in many applications such as antialiasing filters and high frequency communication IF strips. With a 400 MHz gain bandwidth product and high slew rate, the AD8045 is an ideal candidate for active filters. Figure 70 shows the frequency response of the 90 MHz LPF. In addition to the bandwidth requirements, the slew rate must be capable of supporting the full power bandwidth of the filter. In this case, a 90 MHz bandwidth with a 2 V p-p output swing requires at least 1200 V/µs. This performance is achievable only at 90 MHz because of the wide bandwidth and high slew rate of the AD8045. The circuit shown in Figure 73 is a 90 MHz, 4-pole, Sallen-Key, LPF. The filter comprises two identical cascaded Sallen-Key LPF sections, each with a fixed gain of G = +2. The net gain of the filter is equal to G = +4 or 12 dB. The actual gain shown in Figure 70 is only 6 dB. This is due to the output voltage being divided in half by the series matching termination resistor, RT, and the load resistor. First Stage K = R3 R8 + 1, Second Stage K = +1 R4 R7 Resistor values are kept low for minimal noise contribution, offset voltage, and optimal frequency response. Due to the low capacitance values used in the filter circuit, the PCB layout and minimization of parasitics is critical. A few picofarads can detune the filters corner frequency, fc. The capacitor values shown in Figure 73 actually incorporate some stray PCB capacitance. Capacitor selection is critical for optimal filter performance. Capacitors with low temperature coefficients, such as NPO ceramic capacitors and silver mica, are good choices for filter elements. 20 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 0.1 1 10 FREQUENCY (MHz) 100 Figure 70. 90 MHz Low-Pass Filter Response Rev. B | Page 20 of 24 1000 04814-0-006 0 04814-0-068 The gain, or K, of the circuits is –120 GAIN (dB) DISTORTION (dBc) Setting the resistors and capacitors equal to each other greatly simplifies the design equations for the Sallen-Key filter. The corner frequency, or −3 dB frequency, can be described by the equation AIN = –1dBFS SNR = 69.9dBc SFDR = 65.3dBc Data Sheet AD8045 M4.00ns A CH1 0.00V CH1 500mV Figure 71. Small Signal Transient Response of 90 MHz LPF C3 7.1pF 10µF +5V INPUT RT 49.9Ω R1 249Ω A CH1 10µF 0.1µF R2 249Ω U1 C2 7.1pF 0.1µF R6 249Ω 10µF R5 249Ω U1 C4 7.1pF RT 49.9Ω 10µF 0.1µF 0.1µF –5V R4 499Ω R3 499Ω 0.00V Figure 72. Large Signal Transient Response of 90 MHz LPF C1 7.1pF +5V M4.00ns OUTPUT R9 24.9Ω C5 5pF –5V R7 499Ω R8 499Ω Figure 73. 4-Pole, 90 MHz, Sallen-Key Low-Pass Filter Rev. B | Page 21 of 24 04814-0-005 CH1 50.0mV 04814-0-070 1 04814-0-069 1 AD8045 Data Sheet PRINTED CIRCUIT BOARD LAYOUT Laying out the printed circuit board (PCB) is usually the last step in the design process and often proves to be one of the most critical. A brilliant design can be rendered useless because of a poor or sloppy layout. Since the AD8045 can operate into the RF frequency spectrum, high frequency board layout considerations must be taken into account. The PCB layout, signal routing, power supply bypassing, and grounding all must be addressed to ensure optimal performance. SIGNAL ROUTING The AD8045 LFCSP features the new low distortion pinout with a dedicated feedback pin and allows a compact layout. The dedicated feedback pin reduces the distance from the output to the inverting input, which greatly simplifies the routing of the feedback network. When laying out the AD8045 as a unity-gain amplifier, it is recommended that a short, but wide, trace between the dedicated feedback pin and the inverting input to the amplifier be used to minimize stray parasitic inductance. To minimize parasitic inductances, ground planes should be used under high frequency signal traces. However, the ground plane should be removed from under the input and output pins to minimize the formation of parasitic capacitors, which degrades phase margin. Signals that are susceptible to noise pickup should be run on the internal layers of the PCB, which can provide maximum shielding. POWER SUPPLY BYPASSING Power supply bypassing is a critical aspect of the PCB design process. For best performance, the AD8045 power supply pins need to be properly bypassed. A parallel connection of capacitors from each of the power supply pins to ground works best. Paralleling different values and sizes of capacitors helps to ensure that the power supply pins see a low ac impedance across a wide band of frequencies. This is important for minimizing the coupling of noise into the amplifier. Starting directly at the power supply pins, the smallest value and sized component should be placed on the same side of the board as the amplifier, and as close as possible to the amplifier, and connected to the ground plane. This process should be repeated for the next larger value capacitor. It is recommended for the AD8045 that a 0.1 µF ceramic 0508 case be used. The 0508 offers low series inductance and excellent high frequency performance. The 0.1 µF case provides low impedance at high frequencies. A 10 µF electrolytic capacitor should be placed in parallel with the 0.1 µF. The 10 µf capacitor provides low ac impedance at low frequencies. Smaller values of electrolytic capacitors may be used depending on the circuit requirements. Additional smaller value capacitors help to provide a low impedance path for unwanted noise out to higher frequencies but are not always necessary. Placement of the capacitor returns (grounds), where the capacitors enter into the ground plane, is also important. Returning the capacitors grounds close to the amplifier load is critical for distortion performance. Keeping the capacitors distance short, but equal from the load, is optimal for performance. In some cases, bypassing between the two supplies can help to improve PSRR and to maintain distortion performance in crowded or difficult layouts. It is brought to the attention of the designer here as another option to improve performance. Minimizing the trace length and widening the trace from the capacitors to the amplifier reduce the trace inductance. A series inductance with the parallel capacitance can form a tank circuit, which can introduce high frequency ringing at the output. This additional inductance can also contribute to increased distortion due to high frequency compression at the output. The use of vias should be minimized in the direct path to the amplifier power supply pins since vias can introduce parasitic inductance, which can lead to instability. When required, use multiple large diameter vias because this lowers the equivalent parasitic inductance. GROUNDING The use of ground and power planes is encouraged as a method of proving low impedance returns for power supply and signal currents. Ground and power planes can also help to reduce stray trace inductance and to provide a low thermal path for the amplifier. Ground and power planes should not be used under any of the pins of the AD8045. The mounting pads and the ground or power planes can form a parasitic capacitance at the amplifiers input. Stray capacitance on the inverting input and the feedback resistor form a pole, which degrades the phase margin, leading to instability. Excessive stray capacitance on the output also forms a pole, which degrades phase margin. Rev. B | Page 22 of 24 Data Sheet AD8045 The AD8045 features an exposed paddle, which lowers the thermal resistance by 25% compared to a standard SOIC plastic package. The exposed paddle of the AD8045 is internally connected to the negative power supply pin. Therefore, when laying out the board, the exposed paddle must either be connected to the negative power supply or left floating (electrically isolated). Soldering the exposed paddle to the negative power supply metal ensures maximum thermal transfer. Figure 74 and Figure 75 show the proper layout for connecting the SOIC and LFCSP exposed paddle to the negative supply. THERMAL CONDUCTIVE INSULATOR 04814-0-072 EXPOSED PADDLE Figure 76. SOIC with Thermal Conductive Pad Material The thermal pad provides high thermal conductivity but isolates the exposed paddle from ground or other potential. It is recommended, when possible, to solder the paddle to the negative power supply plane or trace for maximum thermal transfer. Note that soldering the paddle to ground shorts the negative power supply to ground and can cause irreparable damage to the AD8045. 04814-0-071 DRIVING CAPACITIVE LOADS Figure 74. SOIC Exposed Paddle Layout 04814-0-073 The use of thermal vias or heat pipes can also be incorporated into the design of the mounting pad for the exposed paddle. These additional vias help to lower the overall theta junction to ambient (θJA). Using a heavier weight copper on the surface to which the exposed paddle of the amplifier is soldered can greatly reduce the overall thermal resistance seen by the AD8045. Figure 75. LFCSP Exposed Paddle Layout For existing designs that want to incorporate the AD8045, electrically isolating the exposed paddle is another option. If the exposed paddle is electrically isolated, the thermal dissipation is primarily through the leads, and the thermal resistance of the package now approaches 125°C/W, the standard SOIC θJA. However, a thermally conductive and electrically isolated pad material may be used. A thermally conductive spacer, such as the Bergquist Company Sil-Pad, is an excellent solution to this problem. Figure 76 shows a typical implementation using thermal pad material. In general, high speed amplifiers have a difficult time driving capacitive loads. This is particularly true in low closed-loop gains, where the phase margin is the lowest. The difficulty arises because the load capacitance, CL, forms a pole with the output resistance, RO, of the amplifier. The pole can be described by the equation fP = 1 2πRO C L If this pole occurs too close to the unity-gain crossover point, the phase margin degrades. This is due to the additional phase loss associated with the pole. The AD8045 output can drive 18 pF of load capacitance directly, in a gain of +2 with 30% overshoot, as shown in Figure 37. Larger capacitance values can be driven but must use a snubbing resistor (RSNUB) at the output of the amplifier, as shown in Figure 61 and Figure 62. Adding a small series resistor, RSNUB, creates a zero that cancels the pole introduced by the load capacitance. Typical values for RSNUB can range from 25 Ω to 50 Ω. The value is typically arrived at empirically and based on the circuit requirements. Rev. B | Page 23 of 24 AD8045 Data Sheet OUTLINE DIMENSIONS 5.00 4.90 4.80 2.29 0.356 5 8 6.20 6.00 5.80 4.00 3.90 3.80 2.29 0.457 4 1 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. BOTTOM VIEW 1.27 BSC 3.81 REF TOP VIEW SEATING PLANE 0.50 0.25 0.10 MAX 0.05 NOM COPLANARITY 0.10 0.51 0.31 8° 0° 45° 0.25 0.17 1.04 REF 1.27 0.40 06-02-2011-B 1.65 1.25 1.75 1.35 COMPLIANT TO JEDEC STANDARDS MS-012-A A Figure 77. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters 1.84 1.74 1.64 3.10 3.00 SQ 2.90 0.50 BSC 8 5 1.55 1.45 1.35 EXPOSED PAD 0.50 0.40 0.30 0.80 0.75 0.70 SEATING PLANE 1 4 BOTTOM VIEW TOP VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.30 0.25 0.20 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-229-WEED 12-07-2010-A PIN 1 INDEX AREA Figure 78. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-13) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD8045ARDZ AD8045ARDZ-REEL7 AD8045ACPZ-R2 AD8045ACPZ-REEL7 1 Minimum Ordering Quantity 1 1,000 250 1,500 Temperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Package Description 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead LFCSP 8-Lead LFCSP Z = RoHS Compliant Part. ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04814-0-5/16(B) Rev. B | Page 24 of 24 Package Option RD-8-1 RD-8-1 CP-8-13 CP-8-13 Branding H8B H8B