HD74BC373A Octal D Type Transparent Latches With 3 State Outputs REJ03D0283–0300Z (Previous ADE-205-009A (Z)) Rev.3.00 Jul.16.2004 Description The HD74BC373A provides high drivability and operation equal to or better than high speed bipolar standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5 of high speed bipolar logic IC, when the frequency is 10 MHz. The device has eight D type latches with three state outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Features • Input/Output are at high impedance state when power supply is off. • Built in input pull up circuit can make input pins be open, when not used. • TTL level input • Wide operating temperature range input pins Ta = –40 to + 85°C • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74BC373AFPEL SOP-20 pin (JEITA) FP-20DAV FP EL (2,000 pcs/reel) HD74BC373ATELL TSSOP-20 pin T ELL (2,000 pcs/reel) TTP-20DAV Note: Please consults the sales office for the above package availability. Function Table Inputs LE G D Output Q H L X H X L Z L L L H L H X H No change H L X Z : : : : High level Low level Immaterial High impedance Rev.3.00, Jul.16.2004, page 1 of 8 HD74BC373A Pin Arrangement G 1 20 VCC 1Q 2 19 8Q 1D 3 18 8D 2D 4 17 7D 2Q 5 16 7Q 3Q 6 15 6Q 3D 7 14 6D 4D 8 13 5D 4Q 9 12 5Q GND 10 11 LE (Top view) Absolute Maximum Ratings Item Supply voltage Input diode current Input voltage Output voltage Off state output voltage Symbol VCC Rating –0.5 to +7.0 Unit V IIK VIN ±30 –0.5 to +7.5 mA V VOUT VOUT(off) –0.5 to +7.5 –0.5 to +5.5 V V Storage temperature Tstg –65 to +150 °C Note: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage VCC 4.5 5.0 5.5 V Input voltage Output voltage VIN VOUT 0 0 — — VCC VCC V V Operating temperature Input rise/fall time*1 Topr tr, tf –40 0 — — 85 8 °C ns/V Note: Symbol Min Typ 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.3.00, Jul.16.2004, page 2 of 8 Max Unit HD74BC373A Logic Diagram G 1D D Q 1Q 2D D Q 2Q 7D D Q 7Q 8D D Q 8Q LE Rev.3.00, Jul.16.2004, page 3 of 8 HD74BC373A Electrical Characteristics (Ta = –40°C to +85°C) Item Symbol Input voltage VIH VIL Output voltage VOH Input diode voltage Input current VCC(V) Min Max Unit Test Conditions 2.0 — — 0.8 V V 4.5 4.5 2.4 2.0 — — V V IOH = –3 mA IOH = –15 mA VOL 4.5 4.5 — — 0.4 0.5 V V IOL = 24 mA IOL = 48 mA VIK II 4.5 5.5 — — –1.2 –250 V µA IIN = –18 mA VIN = 0 V 5.5 5.5 — — 1.0 100 µA µA VIN = 5.5 V VIN = 7.0 V Short circuit output current*1 Off state output current IOS IOZH 5.5 5.5 –100 — –225 50 mA µA VIN = 0 or 5.5 V VO = 2.7 V Supply current IOZL ICCL 5.5 5.5 — — –50 29.5 µA mA VO = 0.5 V VIN = 0 or 5.5 V All outputs is “L” ICCH 5.5 — 2.5 mA ICCZ 5.5 — 2.5 mA VIN = 0 or 5.5 V All outputs is “H” VIN = 0 or 5.5 V All outputs is “Z” ICCT*2 5.5 — 1.5 mA VIN = 3.4 or 0.5 V Notes : 1. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. 2. When input by the TTL level, it shows ICC increase at per one input pin. Switching Test Method (CL = 50 pF) Ta = 25°C VCC = 5.0 V Ta = –40 to 85°C VCC = 5.0 V ±10% Item Propagation D→Q Symbol Min tPLH 3.0 Max 8.0 Min 3.0 Max 10.0 Unit Test Conditions ns See under figure delay time tPHL tPLH 3.0 3.0 8.0 8.0 3.0 3.0 10.0 10.0 ns Output enable time tPHL tZH 3.0 3.0 8.0 9.0 3.0 3.0 10.0 11.0 ns Output disable time tZL tHZ 3.0 3.0 9.0 8.0 3.0 3.0 11.0 10.0 ns Setup time tLZ tS(H) 3.0 2.0 8.0 — 3.0 2.0 10.0 — ns Hold time tS(L) th(H) 2.0 2.0 — — 2.0 2.0 — — ns Pulse width th(L) tw 2.0 6.0 — — 2.0 6.0 — — Input capacitanse Output capacitance CIN CO 3.0(Typ) 15.0(Typ) LE → Q Rev.3.00, Jul.16.2004, page 4 of 8 — — ns pF pF VIN = VCC or GND VO = VCC or GND HD74BC373A Test Circuit Input Pulse Generator Zout = 50 Ω Input Pulse Generator Zout = 50 Ω Notes: VCC See Function Table VCC G Output 1D to 8D 1Q to 8Q LE 1. CL includes probe and jig capacitance. 2. Open: tPLH, tPHL, tZH, tHZ, th, tSU, tw 7 V: tZL, tLZ Rev.3.00, Jul.16.2004, page 5 of 8 500 Ω CL = 50 pF 450 Ω 50 Ω Scope *2 OPEN 7V HD74BC373A Waveforms-1 tr tf 90% 1.5 V Input LE 3V 90% 1.5 V 10% 10% tr 3V 90% 90% Input D 0V tf 10% 10% t PLH 0V t PHL VOH 1.5 V Output Q 1.5 V VOL Waveforms-2 tr 3V 90% Input LE 10% 0V tr tf 90% Input D 3V 90% 1.5 V 1.5 V 10% 10% t PLH t PHL 0V VOH Output Q Rev.3.00, Jul.16.2004, page 6 of 8 1.5 V 1.5 V VOL HD74BC373A Waveforms-3 tr Input LE tf 90% 1.5 V 10% 3V 90% 1.5 V tw 10% 0V th ts 3V Input D Notes: 1.5 V 1.5 V 0V 1. tr = 2.5 ns, tf = 2.5 ns 2. Input waveform: PRR =1 MHz, duty cycle 50% Waveforms-4 tf Input G tr 90% 1.5 V 90% 1.5 V 10% 10% 3V 0V t ZL t LZ 3.5 V 1.5 V Waveform–A VOL + 0.3 V t ZH Waveform–B VOL t HZ VOH – 0.3 V VOH 1.5 V 0V Notes: 1. tr = 2.5 ns, tf = 2.5 ns 2. Input waveform: PRR = 1 MHz, duty cycle 50% 3. Waveform-A shows input conditions such that the output is “L” level when enable by the output control. 4. Waveform-B shows input conditions such that the output is “H” level when enable by the output control. Rev.3.00, Jul.16.2004, page 7 of 8 HD74BC373A Package Dimensions As of January, 2003 Unit: mm 12.6 13 Max 11 1 10 5.5 20 *0.20 ± 0.05 2.20 Max 1.15 0˚ – 8 ˚ 0.10 ± 0.10 0.80 Max 0.20 7.80 +– 0.30 1.27 *0.40 ± 0.06 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-20DAV — Conforms 0.31 g As of January, 2003 Unit: mm 6.50 6.80 Max 11 1 10 4.40 20 0.65 *0.20 ± 0.05 1.0 0.13 M 6.40 ± 0.20 *Ni/Pd/Au plating Rev.3.00, Jul.16.2004, page 8 of 8 0.07 +0.03 –0.04 0.10 *0.15 ± 0.05 1.10 Max 0.65 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-20DAV — — 0.07 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. 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