Cadeka CLC2000 High output current dual amplifier Datasheet

Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
Comlinear CLC2000
®
High Output Current Dual Amplifier
Applications
n ADSL PCI modem cards
n ADSL external modems
n Cable drivers
n Video line driver
n Twisted pair driver/receiver
General Description
The Comlinear CLC2000 is a dual voltage feedback amplifier that offers
±200mA of output current at 9.4Vpp. The CLC2000 is capable of driving
signals to within 1V of the power rails. When connected as a differential line
driver, the dual amplifier drives signals up to 18.8Vpp into a 25Ω load, which
supports the peak upstream power levels for upstream full-rate ADSL CPE
applications.
The Comlinear CLC2000 can operate from single or dual supplies from 5V to
12V. It consumes only 7mA of supply current per channel. The combination
of wide bandwidth, low noise, low distortion, and high output current capability makes the CLC2000 ideally suited for Customer Premise ADSL or video line
driving applications.
Typical Application - ADSL Application
+Vs
+
1/2
CLC2000
Rf+
Ro+=12.5Ω
Vo+
1:2
Rg
RL=100Ω
Rf-
-
VOUT
Rev 1A
VIN
Vo-
Ro-=12.5Ω
1/2
CLC2000
-Vs
Ordering Information
Part Number
Package
Pb-Free
Operating Temperature Range
Packaging Method
CLC2000ISO8X
SOIC-8
Yes
-40°C to +85°C
Reel
CLC2000ISO8
SOIC-8
Yes
-40°C to +85°C
Rail
Moisture sensitivity level for all parts is MSL-1.
©2008 CADEKA Microcircuits LLC Comlinear CLC2000 High Output Current Dual Amplifier
features
n 9.4V
pp output drive into RL= 25Ω
n Using both amplifiers, 18.8V
pp
differential output drive into RL= 25Ω
n ±200mA @ V = 9.4V
o
pp
n 0.009%/0.06˚ differential gain/
phase error
n 250MHz -3dB bandwidth at G = 2
n 510MHz -3dB bandwidth at G = 1
n 210V/μs slew rate
n 4.5nV/√Hz input voltage noise
n 2.7pA/√Hz input current noise
n 7mA supply current
n Fully specified at 5V and 12V supplies
n Pb-free SOIC-8 package
www.cadeka.com
Data Sheet
CLC2000 Pin Configuration
1
8
+VS
-IN1
2
7
OUT2
+IN1
3
6
-IN2
-V S
4
5
+IN2
Comlinear CLC2000 High Output Current Dual Amplifier
OUT1
CLC2000 Pin Assignments
Pin No.
Pin Name
Description
1
OUT1
Output, channel 1
2
-IN1
Negative input, channel 1
3
+IN1
Positive input, channel 1
4
-VS
5
+IN2
Positive input, channel 2
6
-IN2
Negative input, channel 2
7
OUT2
Output, channel 2
8
+VS
Negative supply
Positive supply
Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should
not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating
conditions noted on the tables and plots.
Supply Voltage
Input Voltage Range
Min
Max
Unit
0
-Vs -0.5V
±7 or 14
+Vs +0.5V
V
V
Comlinear CLC2000 High Output Current Dual Amplifier
Parameter
Reliability Information
Parameter
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Package Thermal Resistance
8-Lead SOIC
Min
Typ
-65
Max
Unit
150
150
260
°C
°C
°C
100
°C/W
Notes:
Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air.
ESD Protection
Product
SOIC-8
Human Body Model (HBM)
Charged Device Model (CDM)
2.5kV
2kV
Recommended Operating Conditions
Parameter
Min
Operating Temperature Range
Supply Voltage Range
-40
±2.5
Typ
Max
Unit
+85
±6.5
°C
V
Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com
3
Data Sheet
Electrical Characteristics
TA = 25°C, Vs = 5V, Rf = Rg = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
-3dB Bandwidth
G = +1, VOUT = 0.2Vpp, Rf = 0
422
MHz
BWSS
BWLS
-3dB Bandwidth
G = +2, VOUT = 0.2Vpp
236
MHz
Large Signal Bandwidth
G = +2, VOUT = 2Vpp
68
BW0.1dB
MHz
0.1dB Gain Flatness
G = +2, VOUT = 0.2Vpp
77
MHz
Time Domain Response
tR, tF
Rise and Fall Time
VOUT = 1V step; (10% to 90%)
3.7
ns
tS
Settling Time to 0.1%
VOUT = 2V step
20
ns
OS
Overshoot
VOUT = 0.2V step
6
%
SR
Slew Rate
VOUT = 2V step
200
V/µs
2Vpp, 100KHz, RL = 25Ω
-83
dBc
2Vpp, 1MHz, RL = 100Ω
-85
dBc
2Vpp, 100KHz, RL = 25Ω
-86
dBc
2Vpp, 1MHz, RL = 100Ω
-82
dBc
%
Distortion/Noise Response
HD2
2nd Harmonic Distortion
HD3
3rd Harmonic Distortion
DG
Differential Gain
NTSC (3.58MHz), DC-coupled, RL = 150Ω
0.01
DP
Differential Phase
NTSC (3.58MHz), DC-coupled, RL = 150Ω
0.05
°
en
Input Voltage Noise
> 1MHz
4.2
nV/√Hz
in
Input Current Noise
> 1MHz
2.7
pA/√Hz
XTALK
Crosstalk
Channel-to-channel 5MHz
-63
dB
DC Performance
VIO
Input Offset Voltage
0.3
mV
dVIO
Average Drift
0.383
µV/°C
IIO
Input Offset Current
0.2
µA
Ib
Input Bias Current
10
µA
Average Drift
2.5
nA/°C
81
dB
dIbni
Power Supply Rejection Ratio
DC
AOL
Open-Loop Gain
RL = 25Ω
76
dB
IS
Supply Current
per channel
6.75
mA
Non-inverting
2.5
MΩ
1
pF
0.4 to
4.6
V
80
dB
Input Characteristics
RIN
Input Resistance
CIN
Input Capacitance
CMIR
Common Mode Input Range
CMRR
Common Mode Rejection Ratio
DC
Output Characteristics
RO
VOUT
ISC
Output Resistance
Closed Loop, DC
0.01
Ω
RL = 25Ω
0.95 to
4.05
V
RL = 1kΩ
0.75 to
4.25
V
1000
mA
Output Voltage Swing
Short-Circuit Output Current
©2004-2008 CADEKA Microcircuits LLC VOUT = VS / 2
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4
Rev 1A
PSRR
Comlinear CLC2000 High Output Current Dual Amplifier
UGBW
Data Sheet
Electrical Characteristics
TA = 25°C, Vs = 12V, Rf = Rg = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
-3dB Bandwidth
G = +1, VOUT = 0.2Vpp, Rf = 0
510
MHz
BWSS
BWLS
-3dB Bandwidth
G = +2, VOUT = 0.2Vpp
250
MHz
Large Signal Bandwidth
G = +2, VOUT = 4Vpp
35
BW0.1dB
MHz
0.1dB Gain Flatness
G = +2, VOUT = 0.2Vpp
32
MHz
13.3
ns
20
ns
Time Domain Response
tR, tF
Rise and Fall Time
VOUT = 4V step; (10% to 90%)
tS
Settling Time to 0.1%
VOUT = 2V step
OS
Overshoot
VOUT = 0.2V step
2
%
SR
Slew Rate
VOUT = 4V step
210
V/µs
2Vpp, 100KHz, RL = 25Ω
-84
dBc
2Vpp, 1MHz, RL = 100Ω
-86
dBc
8.4Vpp, 100KHz, RL = 25Ω
-63
dBc
8.4Vpp, 1MHz, RL = 100Ω
-82
dBc
2Vpp, 100KHz, RL = 25Ω
-88
dBc
2Vpp, 1MHz, RL = 100Ω
-80
dBc
8.4Vpp, 100KHz, RL = 25Ω
-63
dBc
Distortion/Noise Response
HD2
2nd Harmonic Distortion
HD3
3rd Harmonic Distortion
DG
Differential Gain
DP
8.4Vpp, 1MHz, RL = 100Ω
-83
dBc
NTSC (3.58MHz), DC-coupled, RL = 150Ω
0.009
%
Differential Phase
NTSC (3.58MHz), DC-coupled, RL = 150Ω
0.06
°
en
Input Voltage Noise
> 1MHz
4.5
nV/√Hz
in
Input Current Noise
> 1MHz
2.7
pA/√Hz
Crosstalk
Channel-to-channel 5MHz
-62
dB
XTALK
DC Performance
VIO
dVIO
Input Offset Voltage(1)
Input Offset Current(1)
Ib
Input Bias Current(1)
0.3
6
0.383
-2
Average Drift
73
mV
µV/°C
0.2
2
10
20
µA
µA
2.5
nA/°C
81
dB
PSRR
Power Supply Rejection Ratio(1)
DC
AOL
Open-Loop Gain
RL = 25
76
IS
Supply Current(1)
per channel
7
dB
12
mA
Input Characteristics
RIN
Input Resistance
CIN
Input Capacitance
CMIR
Common Mode Input Range
CMRR
Common Mode Rejection Ratio(1)
Non-inverting
2.5
MΩ
1
pF
0.6 to
11.4
V
70
79
dB
Closed Loop, DC
0.01
Ω
RL = 25Ω (1)
1.5
1.2 to
10.8
DC
Output Characteristics
RO
VOUT
ISC
Output Resistance
Output Voltage Swing
Short-Circuit Output Current
10.5
V
RL = 1kΩ
0.8 to
11.2
V
VOUT = VS / 2
1000
mA
Notes:
1. 100% tested at 25°C
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com
5
Rev 1A
IIO
dIbni
-6
Average Drift
Comlinear CLC2000 High Output Current Dual Amplifier
UGBW
Data Sheet
Typical Performance Characteristics
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Non-Inverting Frequency Response (VS=5V)
1
2
0
1
Normalized Gain (dB)
-1
G = 10
-2
G=2
G=5
-3
-4
G=1
Rf = 0
-5
-6
G=1
Rf = 0
0
-1
G = 10
G=5
-3
-4
-5
VOUT = 0.2Vpp
-7
VOUT = 0.2Vpp
-6
0.1
1
10
100
1000
0.1
1
Frequency (MHz)
10
1000
Inverting Frequency Response (VS=5V)
1
1
G = -1
0
G = -1
0
-1
-1
Normalized Gain (dB)
G = -2
-2
G = -10
-3
-4
G = -5
-5
G = -2
-2
G = -10
-3
-4
G = -5
-5
-6
-6
VOUT = 0.2Vpp
-7
VOUT = 0.2Vpp
-7
0.1
1
10
100
1000
0.1
1
10
100
1000
100
1000
Frequency (MHz)
Frequency Response vs. RL
Rev 1A
Frequency (MHz)
Frequency vs. RL (VS = 5V)
2
2
RL = 5kΩ
1
RL = 5kΩ
1
RL = 1kΩ
0
Normalized Gain (dB)
Normalized Gain (dB)
100
Frequency (MHz)
Inverting Frequency Response
Normalized Gain (dB)
G=2
-2
-1
-2
RL = 150Ω
-3
RL = 50Ω
-4
-5
RL = 1kΩ
0
-1
-2
RL = 150Ω
-3
RL = 50Ω
-4
-5
VOUT = 0.2Vpp
VOUT = 0.2Vpp
RL = 25Ω
-6
RL = 25Ω
-6
0.1
1
10
Frequency (MHz)
©2004-2008 CADEKA Microcircuits LLC 100
1000
0.1
1
10
Comlinear CLC2000 High Output Current Dual Amplifier
Normalized Gain (dB)
Non-Inverting Frequency Response
Frequency (MHz)
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6
Data Sheet
Typical Performance Characteristics
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Frequency vs. CL
Frequency vs. CL (VS = 5V)
1
0
0
CL = 1000pF
Rs = 5Ω
CL = 500pF
Rs = 6Ω
-2
-3
CL = 100pF
Rs = 13Ω
-4
CL = 50pF
Rs = 20Ω
-5
-6
CL = 1000pF
Rs = 5Ω
-1
Normalized Gain (dB)
Normalized Gain (dB)
-1
-3
CL = 100pF
Rs = 13Ω
-4
CL = 50pF
Rs = 25Ω
-5
-6
CL = 10pF
Rs = 30Ω
VOUT = 0.2Vpp
CL = 500pF
Rs = 6Ω
-2
-7
VOUT = 0.2Vpp
-7
0.1
1
10
100
1000
0.1
1
Frequency (MHz)
100
1000
Recommended RS vs. CL (VS = 5V)
45
40
35
30
RS (Ω)
RS (Ω)
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
10
Frequency (MHz)
Recommended RS vs. CL
25
20
15
10
VOUT = 0.2Vpp
RS optimized for <1dB peaking
10
VOUT = 0.2Vpp
RS optimized for <1dB peaking
5
0
100
1000
10
100
1000
CL (pF)
Frequency Response vs. VOUT
Rev 1A
CL (pf)
Frequency Response vs. VOUT (VS = 5V)
1
1
VOUT = 1Vpp
-1
VOUT = 5Vpp
VOUT = 2Vpp
-2
-3
VOUT = 4Vpp
-4
VOUT = 1Vpp
0
-5
-6
Normalized Gain (dB)
0
Normalized Gain (dB)
CL = 10pF
Rs = 45Ω
-1
VOUT = 2Vpp
-2
-3
VOUT = 3Vpp
-4
-5
-6
-7
-7
0.1
1
10
Frequency (MHz)
©2004-2008 CADEKA Microcircuits LLC 100
1000
0.1
1
10
Comlinear CLC2000 High Output Current Dual Amplifier
1
100
1000
Frequency (MHz)
www.cadeka.com
7
Data Sheet
Typical Performance Characteristics - Continued
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Frequency Response vs. Temperature
Frequency vs. Temperature (VS = 5V)
1
- 40degC
0
+ 25degC
-1
Normalized Gain (dB)
Normalized Gain (dB)
0
+ 85degC
-2
-3
-4
-5
-6
-1
-2
-3
+ 25degC
-4
- 40degC
-5
+ 85degC
-6
VOUT = 2V
0.2V
pp pp
-7
VOUT = 0.2V
.2Vpppp
-7
0.1
1
10
100
1000
0.1
1
Frequency (MHz)
-3dB Bandwidth vs. Output Voltage
275
250
250
225
225
200
200
175
1000
150
125
100
75
175
150
125
100
75
50
50
25
25
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0
0.5
1.0
Open Loop Transimpendance Gain/Phase vs. Frequency
-60
-80
Phase
30
-100
20
-120
10
-140
0
-160
-10
-180
-20
1k
10k
100k
1M
10M
Frequency (Hz)
©2004-2008 CADEKA Microcircuits LLC 2.5
3.0
100M
1G
-200
Input Voltage Noise
Input Voltage Noise (nV/√Hz)
-40
50
Open Loop Phase (deg)
-20
Gain
60
40
2.0
50
0
80
70
1.5
VOUT (VPP)
Rev 1A
VOUT (VPP)
Open Loop Gain (dB)
100
-3dB Bandwidth vs. Output Voltage (VS=5V)
-3dB Bandwidth (MHz)
-3dB Bandwidth (MHz)
10
Frequency (MHz)
40
30
20
10
0
0.0001 0.001
0.01
0.1
Comlinear CLC2000 High Output Current Dual Amplifier
1
1
10
100
Frequency (MHz)
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8
Data Sheet
Typical Performance Characteristics - Continued
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
2nd Harmonic Distortion vs. RL
3rd Harmonic Distortion vs. RL
-20
-30
-30
RL = 25Ω
RL = 25Ω
-40
RL = 100Ω
Distortion (dBc)
Distortion (dBc)
-40
-50
-60
-70
RL = 1kΩ
-80
RL = 100Ω
-50
-60
-70
RL = 1kΩ
-80
-90
-90
VOUT = 2Vpp
-100
VOUT = 2Vpp
-100
0
5
10
15
20
0
5
10
Frequency (MHz)
-20
-20
-30
-30
-40
-40
10MHz
-60
-70
5MHz
-80
-90
-50
10MHz
-60
-70
5MHz
-80
-90
1MHz
1MHz
-100
-100
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
Output Amplitude (Vpp)
Differential Gain & Phase AC Coupled
Rev 1A
Output Amplitude (Vpp)
Differential Gain & Phase DC Coupled
0.01
0.06
RL = 150Ω
AC coupled into 220µF
0.0075
0.005
0.05
Diff Gain (%) and Diff Phase (°)
Diff Gain (%) and Diff Phase (°)
20
3rd Harmonic Distortion vs. VOUT
Distortion (dBc)
Distortion (dBc)
2nd Harmonic Distortion vs. VOUT
-50
15
Frequency (MHz)
DG
0.0025
0
-0.0025
-0.005
DP
-0.0075
-0.01
DP
0.04
0.03
0.02
0.01
0
-0.01
DG
-0.02
RL = 150Ω
DC coupled
VOUT = 2Vpp
-0.03
-0.7
-0.5
-0.3
-0.1
0.1
Input Voltage (V)
©2004-2008 CADEKA Microcircuits LLC 0.3
0.5
0.7
-0.7
-0.5
-0.3
-0.1
0.1
Comlinear CLC2000 High Output Current Dual Amplifier
-20
0.3
0.5
0.7
Input Voltage (V)
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9
Data Sheet
Typical Performance Characteristics - Continued
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
2nd Harmonic Distortion vs. RL (VS=5V)
-20
-30
-30
Distortion (dBc)
-50
RL = 25Ω
-40
RL = 25Ω
RL = 100Ω
-60
-70
RL = 1kΩ
-80
RL = 100Ω
-50
-60
-70
RL = 1kΩ
-80
-90
-90
VOUT = 2Vpp
-100
VOUT = 2Vpp
-100
0
5
10
15
20
0
5
10
Frequency (MHz)
2nd Harmonic Distortion vs. VOUT (VS=5V)
-45
-50
-50
10MHz
-55
-55
-60
5MHz
Distortion (dBc)
Distortion (dBc)
20
3rd Harmonic Distortion vs. VOUT (VS=5V)
-45
-65
-70
-75
-80
10MHz
-60
-65
-70
5MHz
-75
1MHz
-80
1MHz
-85
-85
-90
-90
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
0.5
0.75
1
1.25
Output Amplitude (Vpp)
1.5
1.75
2
2.25
2.5
2.75
3
Rev 1A
Output Amplitude (Vpp)
Differential Gain & Phase AC Coupled (VS=5V)
Differential Gain & Phase DC Coupled (VS=5V)
0.01
0.04
RL = 150Ω
AC coupled into 220µF
0.0075
DG
Diff Gain (%) and Diff Phase (°)
Diff Gain (%) and Diff Phase (°)
15
Frequency (MHz)
0.005
0.0025
0
-0.0025
-0.005
DP
-0.0075
RL = 150Ω
DC coupled
0.03
0.02
DG
0.01
0
-0.01
DP
-0.01
-0.02
-0.4
-0.3
-0.2
-0.1
0
0.1
Input Voltage (V)
©2004-2008 CADEKA Microcircuits LLC 0.2
0.3
0.4
-0.4
-0.2
0
0.2
0.4
Input Voltage (V)
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Comlinear CLC2000 High Output Current Dual Amplifier
-20
-40
Distortion (dBc)
3rd Harmonic Distortion vs. RL (VS=5V)
10
Data Sheet
Typical Performance Characteristics - Continued
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Large Signal Pulse Response
9.0
6.1
8.0
6.05
7.0
Voltage (V)
6.15
6
VOUT = 2Vpp
6.0
5.95
5.0
5.9
4.0
5.85
VOUT = 4Vpp
3.0
0
20
40
60
80
100
120
140
160
180
200
0
20
40
60
80
Time (ns)
100
120
140
160
180
200
Time (ns)
Small Signal Pulse Response (VS=5V)
Large Signal Pulse Response (VS=5V)
2.65
4.5
VOUT = 3Vpp
4.0
2.60
3.5
VOUT = 2Vpp
Voltage (V)
Voltage (V)
2.55
2.50
2.45
3.0
2.5
2.0
1.5
2.40
1.0
2.35
0.5
0
20
40
60
80
100
120
140
160
180
200
0
20
40
60
80
Crosstalk vs. Frequency
120
140
160
180
200
Crosstalk vs. Frequency (VS=5V)
-30
-30
-35
-35
-40
-40
-45
-45
-50
-50
Crosstalk (dB)
Crosstalk (dB)
100
Time (ns)
Rev 1A
Time (ns)
-55
-60
-65
-70
-75
-55
-60
-65
-70
-75
-80
-80
VOUT = 2Vpp
-85
VOUT = 2Vpp
-85
-90
-90
0.1
1
10
Frequency (MHz)
©2004-2008 CADEKA Microcircuits LLC 100
0.1
1
Comlinear CLC2000 High Output Current Dual Amplifier
Voltage (V)
Small Signal Pulse Response
10
100
Frequency (MHz)
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11
Data Sheet
Typical Performance Characteristics - Continued
TA = 25°C, Vs = 12V, Rf = 510Ω, RL = 100Ω to VS/2, G = 2; unless otherwise noted.
Closed Loop Output Impedance vs. Frequency
CMRR vs. Frequency
1
-30
CMRR (dB)
Output Impedance (Ω)
-20
0.1
0.01
-40
-50
-60
-70
-80
0.001
1k
10k
100k
1M
10M
-90
100M
10
100
1k
PSRR vs. Frequency
1M
10M 100M
1.25
1.00
-40
0.75
-50
0.50
-60
0.25
IOUT (A)
PSRR (dB)
100k
Input Voltage vs. Output Current
-30
-70
-80
IOUT+
0.00
-0.25
-0.50
-0.75
-90
-100
10k
Frequency (Hz)
Frequency (Hz)
-1.00
IOUTRL = 2.668Ω
G = -1
VS = ±6V
-1.25
10
100
1k
10k
100k
©2004-2008 CADEKA Microcircuits LLC 10M 100M
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VIN (±V)
Rev 1A
Frequency (Hz)
1M
Comlinear CLC2000 High Output Current Dual Amplifier
-10
10
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12
Data Sheet
Application Information
Basic Operation
+Vs
6.8μF
Power Dissipation
Input
0.1μF
+
Output
-
RL
0.1μF
Rg
Rf
6.8μF
G = 1 + (Rf/Rg)
-Vs
Figure 1. Typical Non-Inverting Gain Circuit
+Vs
R1
Input
Rg
6.8μF
Output
0.1μF
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction temperature, the package thermal resistance value ThetaJA
(ӨJA) is used along with the total die power dissipation.
TJunction = TAmbient + (ӨJA × PD)
0.1μF
+
Power dissipation is an important consideration in applications with low impedance DC, coupled loads. Guidelines
listed below can be used to verify that the particular application will not cause the device to operate beyond its
intended operating range. Calculations below relate to a
single amplifier. For the CLC2000, both amplifiers power
contribution needs to be added for the total power dissipation.
RL
Rf
6.8μF
G = - (Rf/Rg)
For optimum input offset
voltage set R1 = Rf || Rg
Figure 2. Typical Inverting Gain Circuit
In order to determine PD, the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
PD = Psupply - Pload
Supply power is calculated by the standard power equation.
Power Supply and Decoupling
Psupply = Vsupply × I(RMS supply)
The CLC2000 can be powered with a low noise supply
anywhere in the range from +5V to +13V. Ensure adequate metal connections to power pins in the PC board
layout with careful attention paid to decoupling the power
supply.
Vsupply = V(S+) - V(S-)
High quality capacitors with low equivalent series resistance (ESR) such as multilayer ceramic capacitors (MLCC)
should be used to minimize supply voltage ripple and
power dissipation.
©2004-2008 CADEKA Microcircuits LLC Power delivered to a purely resistive load is:
Pload = ((VLOAD)RMS2) / Rloadeff
The effective load resistor will need to include the effect
of the feedback network. For instance,
Rloadeff in figure 1 would be calculated as:
RL || (Rf + Rg)
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13
Rev 1A
-Vs
Where TAmbient is the temperature of the working environment.
Comlinear CLC2000 High Output Current Dual Amplifier
Figures 1 and 2 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
Two decoupling capacitors should be placed on each power pin with connection to a local PC board ground plane.
A large, usually tantalum, 10μF to 47μF capacitor is required to provide good decoupling for lower frequency
signals and to provide current for fast, large signal changes at the CLC2000 outputs. It should be within 0.25” of
the pin. A secondary smaller 0.1μF MLCC capacitor should
located within 0.125” to reject higher frequency noise on
the power line.
Data Sheet
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, PD can be found from
Quiescent power can be derived from the specified IS values along with known supply voltage, VSupply. Load power
can be calculated as above with the desired signal amplitudes using:
(VLOAD)RMS = VPEAK / √2
( ILOAD)RMS = (VLOAD)RMS / Rloadeff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
Driving Capacitive Loads
Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
RS, between the amplifier and the load to help improve
stability and settling performance. Refer to Figure 4.
Input
+
PDYNAMIC = (VS+ - VLOAD)RMS × (ILOAD)RMS
-
Output
CL
Rf
Assuming the load is referenced in the middle of the power rails or Vsupply/2.
RL
Rg
Figure 3 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the 8 Lead
SOIC packages.
Figure 4. Addition of RS for Driving
Capacitive Loads
Table 1 provides the recommended RS for various capacitive loads. The recommended RS values result in <=1dB
peaking in the frequency response. The Frequency Response vs. CL plots, on page 7, illustrates the response of
the CLC2000.
2.5
2
1.5
SOIC-8
1
0.5
0
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
CL (pF)
RS (Ω)
-3dB BW (MHz)
10
40
275
20
24.5
250
50
20
175
100
13.5
135
500
6
75
1000
5
45
Rev 1A
Maximum Power Dissipation (W)
Rs
Figure 3. Maximum Power Derating
Table 1: Recommended RS vs. CL
Better thermal ratings can be achieved by maximizing
PC board metallization at the package pins. However, be
careful of stray capacitance on the input pins.
In addition, increased airflow across the package can also
help to reduce the effective ӨJA of the package.
©2004-2008 CADEKA Microcircuits LLC For a given load capacitance, adjust RS to optimize the
tradeoff between settling time and bandwidth. In general,
reducing RS will increase bandwidth at the expense of additional overshoot and ringing.
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Comlinear CLC2000 High Output Current Dual Amplifier
PD = PQuiescent + PDynamic - PLoad
In the event of a short circuit condition, the CLC2000 has
circuitry to limit output drive capability to ±1000mA. This
will only protect against a momentary event. Extended
duration under these conditions will cause junction temperatures to exceed 150°C. Due to internal metallization
constraints, continuous output current should be limited
to ±100mA.
14
Data Sheet
Overdrive Recovery
+Vs
3
Rf+
VIN
-
4
Input
1
2
0
0
-1
-2
Output
-2
Ro+=12.5Ω
Vo+
1:2
Rg
RL=100Ω
Rf-
Output Voltage (V)
Input Voltage (V)
1/2
CLC2000
6
VIN = 2.5Vpp
G=5
2
+
Ro-=12.5Ω
VOUT
Vo-
1/2
CLC2000
-Vs
Figure 6: Typical Differential Transmission Line Driver
-4
-3
-6
0
20
40
60
80
100
120
140
160
180
200
Time (ns)
Figure 5. Overdrive Recovery
Using the CLC2000 as a Differential Line Driver
Differential circuits have several advantages over singleended configurations. These include better rejection of
common mode signals and improvement of power-supply
rejection. The use of differential signaling also improves
overall dynamic performance. Total harmonic distortion
(THD) is reduced by the suppression of even signal harmonics and the larger signal swings allow for an improved
signal to noise ratio (SNR).
©2004-2008 CADEKA Microcircuits LLC Data transmission techniques, such as ADSL, utilize amplitude modulation techniques which are sensitive to output
clipping. A signal’s PEAK to RMS ratio, or Crest Factor (CF),
can be used to determine the adequate peak signal levels
to insure fidelity for a given signal.
For an ADSL system, the signal consists of 256 independent frequencies with varying amplitudes. This results in
a noise-like signal with a crest factor of about 5.3. If the
driver does not have enough swing to handle the signal
peaks, clipping will occur and amplitude modulated information can be corrupted, causing degradation in the signals Bit Error Rate.
To determine the required swing, first use the specified
load impedance to convert the RMS power to an RMS voltage. Then, multiply the RMS voltage by the crest factor to
get the peak values. For example 13dBm, as referenced to
1mW, is ~20mW. 20mW into the 100Ω CAT5 impedance
yields a RMS voltage of 1.413 VRMS . Using the ADSL crest
factor of 5.3 yields ~ ±7.5V peak signals.
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15
Rev 1A
The combination of good large signal bandwidth and high
output drive capability makes the CLC2000 well suited for
low impedance line driver applications, such as the upstream data path for a ADSL CPE modem. The dual channel configuration of the CLC2000 provides better channel
matching than a typical single channel device, resulting
in better overall performance in differential applications.
When configured as a differential amplifier as in figure 6, it
can easily deliver the 13dBm to a standard 100Ω twistedpair CAT3 or CAT5 cable telephone network, as required in
a ADSL CPE application.
For any transmission requirement, the fundamental design parameters needed are the effective impedance of
the transmission line, the power required at the load, and
knowledge concerning the content of the transmitted signal. The basic design of such a circuit is briefly outlined
below, using the ADSL parameters as a guideline.
Comlinear CLC2000 High Output Current Dual Amplifier
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the
amplifier to return to its normal or linear operating point.
The recovery time varies, based on whether the input or
output is overdriven and by how much the range is exceeded. The CLC2000 will typically recover in less than
40ns from an overdrive condition. Figure 5 shows the
CLC2000 in an overdriven condition.
Data Sheet
Evalutaion Board Schematics
Evaluation board schematics and layouts are shown in Figures 7-9. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -VS pin of the amplifier is not
directly connected to the ground plane.
In general, the CLC2000 can be used in any application
where an economical and local hardwired connection is
needed. For example, routing analog or digital video information for a in-cabin entertainment system. Networking of
a local surveillance system also could be considered.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
Figure 7. CEB006 Schematic
Rev 1A
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce parasitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more information.
Evaluation Board Information
The following evaluation board is available to aid in the
testing and layout of this device:
Evaluation Board #
CEB006
Products
CLC2000
Figure 8. CEB006 Top View
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com
Comlinear CLC2000 High Output Current Dual Amplifier
Line coupling through a 1:2 transformer is used to realize
these levels. Standard back termination is used to match
the characteristic 100Ω impedance of the CAT5 cable. For
proper power transfer, this requires an effective 1:4 impedance match of 25Ω at the inputs of the transformer. To
account for the voltage drop of the impedance matching
resistors, the signal levels at the output of the amplifier
need to be doubled. Thus each amplifier will swing ±3.75V
about a centered common mode output voltage.
16
Data Sheet
Comlinear CLC2000 High Output Current Dual Amplifier
Figure 9. CEB006 Bottom View
Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com
17
Data Sheet
Mechanical Dimensions
SOIC-8 Package
Comlinear CLC2000 High Output Current Dual Amplifier
Rev 1A
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
T: 877.663.5415 (toll free)
CADEKA, the CADEKA logo design, and Comlinear and the Comlinear logo design, are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved.
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