IDT IDT74FCT163373PF 3.3v cmos 16-bit transparent latch Datasheet

IDT74FCT163373/A/C
3.3V CMOS
16-BIT TRANSPARENT
LATCH
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V
components
The FCT163373/A/C 16-bit transparent D-type latches are
built using advanced dual metal CMOS technology. These
high-speed, low-power latches are ideal for temporary storage of data. They can be used for implementing memory
address latches, I/O ports, and bus drivers. The Output
Enable and Latch Enable controls are organized to operate
each device as two 8-bit latches or one 16-bit latch. Flowthrough organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.
The inputs of FCT163373/A/C can be driven from either
3.3V or 5V devices. This feature allows the use of these
transparent latches as translators in a mixed 3.3V/5V supply
system. With xLE inputs HIGH, the FCT163373/A/C can be
used as buffers to connect 5V components to a 3.3V bus.
FUNCTIONAL BLOCK DIAGRAM
1OE
2OE
1LE
2LE
1D1
D
2D1
D
1O1
2O1
C
C
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
2601 drw 02
2601 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1996 Integrated Device Technology, Inc.
AUGUST 1996
8.4
DSC-2601/6
1
IDT74FCT163373/A/C
3.3V 16-BIT TRANSPARENT LATCH
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
PIN CONFIGURATIONS
Pin Names
xDx
1OE
1
48
1 LE
xLE
Latch Enable Input (Active HIGH)
xOE
Output Enable Input (Active LOW)
xOx
3-State Outputs
1 O1
2
47
1 D1
1 O2
3
46
1 D2
GND
4
45
GND
1 O3
5
44
1 D3
1 O4
6
43
1 D4
VCC
7
42
VCC
1 O5
8
41
1 D5
1 O6
9
40
1 D6
GND
10
39
GND
1 O7
11
38
1 D7
37
1 D8
2 O1
12 SO48-1
SO48-2
13 SO48-3
36
2 D1
2 O2
14
35
2 D2
GND
15
34
GND
2 O3
16
33
2 D3
2 O4
17
32
2 D4
VCC
18
31
VCC
2 O5
19
30
2 D5
2 O6
20
29
2 D6
GND
21
28
GND
2 O7
22
27
2 D7
2 O8
23
26
2 D8
2OE
24
25
2 LE
1 O8
Description
Data Inputs
2601 tbl 01
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
TSTG
Description
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Storage Temperature
I OUT
DC Output Current
VTERM(3)
VTERM(4)
Max.
–0.5 to +4.6
Unit
V
–0.5 to +7.0
V
–0.5 to
VCC + 0.5
–65 to +150
V
°C
–60 to +60
mA
2601 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
CIN
Input
Capacitance
COUT
Output
Capacitance
Conditions
VIN = 0V
Typ.
3.5
VOUT = 0V
3.5
Max. Unit
6.0
pF
8.0
pF
2601 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE(1)
SSOP/
TSSOP/TVSOP
TOP VIEW
2601 drw 03
xDx
Inputs
xLE
xOE
Outputs
xOx
H
H
L
H
L
H
L
L
X
X
H
Z
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
8.4
2601 tbl 02
2
IDT74FCT163373/A/C
3.3V 16-BIT TRANSPARENT LATCH
COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V
Symbol
VIH
Parameter
Input HIGH Level (Input pins)
Test Conditions(1)
Guaranteed Logic HIGH Level
Input HIGH Level (I/O pins)
VIL
Input LOW Level
Guaranteed Logic LOW Level
Min.
2.0
Typ.(2)
—
Max.
5.5
2.0
—
VCC+0.5
–0.5
—
0.8
V
—
—
±1
µA
Unit
V
(Input and I/O pins)
II H
II L
Input HIGH Current (Input pins)
VCC = Max.
VI = 5.5V
Input HIGH Current (I/O pins)
VI = VCC
—
—
±1
Input LOW Current (Input pins)
VI = GND
—
—
±1
Input LOW Current (I/O pins)
VI = GND
—
—
±1
VO = V CC
—
—
±1
VO = GND
—
—
±1
—
–0.7
–1.2
V
–36
–60
–110
mA
50
90
200
mA
VCC– 0.2
—
—
V
I OZH
High Impedance Output Current
I OZL
(3-State Output pins)
VIK
Clamp Diode Voltage
VCC = Max.
VCC = Min., IIN = –18mA
1.5V(3)
µA
I ODH
Output HIGH Current
VCC = 3.3V, V IN = VIH or VIL, VO =
I ODL
Output LOW Current
VCC = 3.3V, V IN = VIH or VIL, VO = 1.5V(3)
VOH
Output HIGH Voltage
VCC = Min.
I OH = –0.1mA
VIN = VIH or V IL
I OH = –3mA
2.4
3.0
—
VCC = 3.0V
VIN = VIH or V IL
VCC = Min.
I OH = –8mA
2.4 (5)
3.0
—
I OL = 0.1mA
—
—
0.2
VIN = VIH or V IL
I OL = 16mA
—
0.2
0.4
I OL = 24mA
—
0.3
0.55
VCC = 3.0V
I OL = 24mA
VIN = VIH or V IL
VCC = Max., VO = GND(3)
—
0.3
0.50
–60
–135
–240
mA
—
150
—
mV
—
0.1
10
µA
VOL
Output LOW Voltage
I OS
Short Circuit Current(4)
VH
Input Hysteresis
I CCL
I CCH
I CCZ
Quiescent Power Supply Current
—
VCC = Max.,
VIN = GND or VCC
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC –0.6V at rated current.
8.4
V
2601 lnk 05
3
IDT74FCT163373/A/C
3.3V 16-BIT TRANSPARENT LATCH
COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current(4)
ICCD
IC
Total Power Supply Current (6)
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
VCC = Max.
VIN = VCC – 0.6V(3)
—
2.0
30
µA
VCC = Max.
Outputs Open
xOE = GND
One Input Toggling
50% Duty Cycle
VIN = VCC
VIN = GND
—
50
75
µA/
MHz
VCC = Max.
VIN = VCC
—
0.5
0.8
mA
Outputs Open
VIN = GND
—
0.5
0.8
fi =10MHz
50% Duty Cycle
VIN = VCC –0.6V
xOE = GND
xLE = VCC
One Bit Toggling
VIN = GND
VCC = Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
xOE = GND
xLE = VCC
Sixteen Bits Toggling
VIN = VCC
VIN = GND
—
2.0
3.0 (5)
VIN = VCC –0.6V
VIN = GND
—
2.0
3.3 (5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
8.4
2601 tbl 06
4
IDT74FCT163373/A/C
3.3V 16-BIT TRANSPARENT LATCH
COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(4)
FCT163373
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
tH
tW
tSK(o)
FCT163373C
Min.(2)
1.5
Max.
8.0
Min.(2)
1.5
Max.
5.2
Min.(2)
1.5
Max.
4.2
Unit
ns
2.0
13.0
2.0
8.5
2.0
5.5
ns
1.5
12.0
1.5
6.5
1.5
5.5
ns
Output Disable Time
1.5
7.5
1.5
5.5
1.5
5.0
ns
Set-up Time HIGH
or LOW, xDx to xLE
Hold Time HIGH
or LOW, xDx to xLE
xLE Pulse Width
HIGH
Output Skew (3)
2.0
—
2.0
—
2.0
—
ns
1.5
—
1.5
—
1.5
—
ns
6.0
—
5.0
—
5.0
—
ns
—
0.5
—
0.5
—
0.5
ns
Parameter
Propagation Delay
xDx to xOx
Propagation Delay
xLE to xOx
Output Enable Time
Condition(1)
CL = 50pF
RL = 500Ω
FCT163373A
2601 tbl 07
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays
and Enable/Disable times should be degraded by 20%.
8.4
5
IDT74FCT163373/A/C
3.3V 16-BIT TRANSPARENT LATCH
COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
6V
←
V
CC
500Ω
V
V
IN
Pulse
Generator
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Open
GND
OUT
D.U.T.
50pF
R
T
C
Switch
6V
GND
Open
2601 lnk 08
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
L
2601 drw 05
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
tH
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tREM
tSU
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
HIGH-LOW-HIGH
PULSE
1.5V
3V
1.5V
0V
tH
2601 drw 07
2601 drw 06
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
DISABLE
3V
CONTROL
INPUT
1.5V
tPZL
VOH
1.5V
VOL
OUTPUT
NORMALLY SWITCH
6V
LOW
tPZH
3V
1.5V
0V
OUTPUT
NORMALLY
HIGH
2601 drw 08
SWITCH
GND
0V
tPLZ
3V
3V
1.5V
0.3V
VOL
tPHZ
0.3V
VOH
1.5V
0V
0V
2601 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. If VCC is below 3V, input voltage swings should be adjusted not to exceed
VCC.
8.4
6
IDT74FCT163373/A/C
3.3V 16-BIT TRANSPARENT LATCH
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT
XXXX
Temp. Range
Device Type
X
Package
PV
PA
PF
Shrink Small Outline Package (SO48-1)
Thin Shrink Small Outline Package (SO48-2)
Thin Very Small Outline Package (SO48-3)
163373
163373A
163373C
Non-Inverting 16-Bit Transparent Latch
74
–40°C to +85°C
2601 drw 10
8.4
7
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