BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Product Description Figure 2. Package Type The BVA305 is a digitally controlled variable gain amplifier (DVGA) is featuring high linearity using the voltage 3V supply with a broadband frequency range of 40 to 4000 MHz. Both stages are internally matched to 50 Ohms and It is easy to use with no external matching components required. A serial output port enables cascading with other serial controlled devices. An integrated digital control interface supports both serial and parallel programming of the attenuation, including the capability to program an initial attenuation state at power-up. Covering a 31.5 dB attenuation range in 0.5 dB steps. The BVA305 is targeted for use in wireless infrastructure, point-topoint, or can be used for any general purpose wireless application. Figure 1. Functional Block Diagram 3 C16 4 GND 5 AMPOUT 6 C2 C4 C8 RF2 P/S VSS/GND 19 6-Bit Digital Step Attenuator Gain Block AMPLIFIER 7 BeRex 8 9 10 11 18 GND 17 GND 16 VDD 15 PUP2 14 PUP1 13 LE 12 CLOCK C0.5 20 DATA 2 21 RF1 C1 22 GND 1 23 AMPIN GND 24-lead 4x4 mm QFN Device Features • • • • • • • • • • • • • • Small 24-Pin 4 x 4 mm QFN Package • • 1.8V control logic compatible Integrate DSA to Amp Functionality Wide Power supply range of +2.7 to +5.5V(DSA) Single Fixed +3V supply(Amp) 40-4000MHz Broadband Performance 13.8dB Gain at 2.14GHz 4.1dB Noise Figure at 2.14GHz with max gain setting 14.2dBm P1dB at 2.14GHz 27.6dBm OIP3 at 2.14GHz No matching circuit needed Attenuation: 0.5 dB steps to 31.5 dB Safe attenuation state transitions Monotonicity: 0.5 dB up to 4 GHz High attenuation accuracy(DSA to Amp) ±(0.15 + 5% x Atten) @ 2.14GHz 24 GND Preliminary Datasheet The BVA305 integrates a high performance digital step attenuator and a high linearity, broadband gain block. using the small package(4x4mm QFN package) and operating VDD 3V voltage. and designed for use in 3G/4G wireless infrastructure and other high performance RF applications. ●website: www.berex.com • Programming modes - Direct Parallel - Latched Parallel - Serial Unique power-up state selection Application • • • 3G/4G Wireless infrastructure and other high performance RF application Microwave and Satellite Radio General purpose Wireless ●email: [email protected] 1 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Table 1. Electrical Specifications1 Parameter Condition Operational Frequency Range Min Typ 40 Gain2 Attenuation = 0dB, at 1900MHz Attenuation Control range 0.5dB step 13.2 Attenuation Step 14.2 Preliminary Datasheet Return loss Unit 4000 MHz 15.2 dB 31.5 dB 0.5 dB ±(0.15 + 3% of atten setting) 40MHz — 1GHz Attenuation Accuracy Max ±(0.15 + 5% of atten setting) >1GHz — 2.2GHz Any bit or bit combination dB >2.2GHz — 3GHz ±(0.15 + 8% of atten setting) >3GHz — 4GHz ±(0.15 + 11% of atten setting) 1GHz — 2.2GHz 16 19 11 16 Attenuation = 0dB (input or output >2.2GHz — 4GHz port) Output Power for 1dB Compression dB Attenuation = 0dB , at 1900MHz 14.8 dBm 28 dBm dB Attenuation = 0dB, at 1900MHz Output Third Order Intercept Point3 two tones at an output of 0 dBm per tone separated by 1 MHz. Noise Figure Attenuation = 0dB, at 1900MHz 4.1 Switching time 50% CTRL to 90% or 10% RF 500 DSA 2.7 800 ns 5.5 V Supply voltage AMP Supply Current Control Interface 3 46 Serial / parallel mode 52 V 58 6 mA Bit Digital input high 1.17 3.6 V Digital input low -0.3 0.6 V Control Voltage Impedance 1 2 3 50 Ω Device performance _ measured on a BeRex Evaluation board at 25°C, 50 Ω system, VDD=+3V, measure on Evaluation Board (DSA to AMP) Gain data has PCB & connectors insertion loss de-embedded OIP3 _ measured with two tones at an output of 0 dBm per tone separated by 1 MHz. BeRex ●website: www.berex.com ●email: [email protected] 2 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Table 2. Typical RF Performance1 Frequency Parameter 70 Gain 3 S11 S22 Unit 900 1900 2140 2650 MHz 16.9 15.6 14.2 13.8 12.5 dB -15.3 -12.3 -15.6 -16.4 -17.3 dB -20.7 -15.5 -25.6 -18.7 -12.9 dB 4 32.3 31.3 28.0 27.6 25.5 dBm P1dB 15.2 15.6 14.8 14.2 13.4 dBm Noise Figure 3.4 3.6 4.1 4.1 4.2 dB OIP3 Preliminary Datasheet 2 1 Device performance _ measured on a BeRex evaluation board at 25°C, VDD=+3V,50 Ω system. measure on Evaluation Board (DSA to AMP) 2 70MHz measured with application circuit refer to table 10 3 Gain data has PCB & connectors insertion loss de-embedded 4 OIP3 _ measured with two tones at an output of 0 dBm per tone separated by 1 MHz. Table 3. Absolute Maximum Ratings Parameter Condition Supply Voltage(VDD) Amp/DSA Supply Current Amp Digital input voltage Min Typ Amp/DSA Operating Temperature Amp/DSA Storage Temperature Unit 3.6/5.5 V 110 -0.3 Maximum input power Max mA 3.6 V +12/+30 dBm -40 85/105 ℃ -55 150 ℃ Junction Temperature 150 ℃ Operation of this device above any of these parameters may result in permanent damage. BeRex ●website: www.berex.com ●email: [email protected] 3 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER Parallel/Serial Selection Either a parallel or serial interface can be used to control the BVA305. The P/S bit provides this selection, with P/S = LOW selecting the parallel interface and P/S = HIGH selecting the serial interface. Serial Interface The serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. It is controlled by three CMOScompatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the LE input. Parallel Mode Interface The parallel interface consists of six CMOS compatible control lines that select the desired attenuation state, as shown in Table 4. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The parallel interface timing requirements are defined by Figure 4 (Parallel Interface Timing Diagram), Table 7 (Parallel Interface AC Characteristics), and switching speed (Table 1). The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The timing for this operation is defined by Figure 3 (Serial Interface Timing Diagram) and Table 6 (Serial Interface AC Characteristics). Programming Options Preliminary Datasheet 40-4000 MHz For latched parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Figure 3) to latch the new attenuation state into the device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Power-up Control Settings The BVA305 always assumes a specifiable attenuation setting on power-up. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. When the attenuator powers up in Serial mode (P/S = 1), the six control bits are set to whatever data is present on the six parallel data inputs (C0.5 to C16). This allows any one of the 64 attenuation settings to be specified as the power-up state. When the attenuator powers up in Parallel mode (P/S = 0) with LE = 0, the control bits are automatically set to one of four possible values. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in Table 5 (Power-Up Truth Table, Parallel Mode). Table 4. Truth Table P/S C16 C8 C4 C2 C1 C0.5 Attenuation state 0 0 0 0 0 0 0 Reference Loss 0 0 0 0 0 0 1 0.5 dB 0 0 0 0 0 1 0 1 dB 0 0 0 0 1 0 0 2 dB 0 0 0 1 0 0 0 4 dB 0 0 1 0 0 0 0 8 dB 0 1 0 0 0 0 0 16 dB 0 1 1 1 1 1 1 31.5 dB Note: Not all 64 possible combinations of C0.5-C16 are shown in table Table 5. Parallel PUP Truth Table P/S LE PUP2 PUP1 Attenuation state 0 0 0 0 Reference Loss 0 0 1 0 8 dB 0 0 0 1 16 dB 0 0 1 1 31.5 dB 0 1 X X Defined by C0.5-C16 Note: Power up with LE = 1 provides normal parallel operation with C0.5-C16, and PUP1 and PUP2 are not active BeRex ●website: www.berex.com ●email: [email protected] 4 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Figure 3. Serial Interface Timing Diagram Table 8. 6-Bit Attenuator Serial Programming Register Map B5 B4 B3 B3 B1 B0 C16 C8 C4 C2 C1 C0.5 MSB (first in) LSB (Last in) P/S VSS/GND 20 19 C2 C4 C8 RF2 Figure 4. Parallel Interface Timing Diagram 24 23 22 21 GND 1 18 GND C1 2 17 GND C0.5 3 16 VDD C16 4 15 PUP2 GND 5 14 PUP1 AMPOUT 6 13 LE VDD = 3.3V with DSA only, -40°C < TA < 105°C, unless otherwise specified Symbol fClk Parameter Min Max Serial data clock frequency 10 Unit MHz tClkH Serial clock HIGH time 30 ns tClkL Serial clock LOW time 30 ns LE set-up time after last tLESUP clock falling edge 10 ns tLEPW LE minimum pulse width 30 ns Serial data set-up time tSDSUP before clock rising edge 10 ns 10 ns tSDHLD Serial data hold time after clock falling edge Note: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification Table 7. Parallel Interface AC Characteristics VDD = 3.3V with DSA only, -40°C < TA < 105°C, unless otherwise specified Symbol tLEPW Parameter Min Max LE minimum pulse width Data set-up time before tPDSUP rising edge of LE Data hold time after falling tPDHLD edge of LE BeRex Unit 10 ns 10 ns 10 ns ●website: www.berex.com 11 12 Data 10 Clock 9 RF1 Table 6. Serial Interface AC Characteristics 8 GND 7 AMPIN EXPOSED Grounnd Pad GND Preliminary Datasheet Figure 5. Pin Configuration(Top View) Table 9. Pin Description Pin 1,5,7,9,17,18 2 3 4 6 8 10 11 12 13 14 15 16 Pin name GND C1 C0.55 C163,5 AMPOUT AMPIN RF11 DATA3 Clock LE4 PUP15 PUP2 VDD 19 VSS/GND2 20 21 22 23 24 P/S RF21 C8 C4 C2 Description Ground Attenuation control bit, 1dB Attenuation control bit, 0.5dB Attenuation control bit, 16dB RF Amp out Port RF Amp in port RF port(DSA output) Serial interface data input Serial interface clock input Latch Enable input Power-up selection bit 1 Power-up selection bit 2 Supply voltage (nominal 3V) External VSS negative voltage control or ground Parallel/Serial mode select RF port(DSA input) Attenuation control bit, 8dB Attenuation control bit, 4dB Attenuation control bit, 2dB Note: 1. RF pins 10 and 21 must be at 0V DC. The RF pins do not require DC blocking capacitors for proper Operation if the 0V DC requirement is met 2. Use VssEXT (pin 19) to bypass and disable internal negative voltage generator. Connect VssEXT (pin 19, VssEXT = GND) to enable internal negative voltage generator 3.Place a 10 kΩ resistor in series, as close to pin as possible to avoid frequency resonance 4. This pin has an internal 2 MΩ resistor to internal positive digital supply 5. This pin has an internal 200 kΩ resistor to GND ●email: [email protected] 5 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Typical Performance Plot - BVA305 EVK - PCB (Application Circuit : 500~4000MHz) Typical Performance Data @ 25°C, Maximum gain state and VDD = 3.0V unless otherwise noted and Application Circuit refer to Table 10 Preliminary Datasheet Figure 6. Gain1 vs Frequency @ Temperature (Max Gain State) Figure 7. Gain vs Frequency @ Major Attenuation Steps Note: 1. Gain data has PCB & connectors insertion loss de-embedded Figure 8. Input Return Loss vs Frequency @ Temperature (Max Gain State) Figure 9. Input Return Loss vs Frequency @ Max Gain & Min Gain1 State Note: 1. Min Gain was measured in the state is set with attenuation 31.5dB Figure 10. output Return Loss vs. Frequency @ Temperature (Max Gain State) Figure 11. output Return Loss vs. Frequency @ Max Gain & Min Gain1 State Note: 1. Min Gain was measured in the state is set with attenuation 31.5dB BeRex ●website: www.berex.com ●email: [email protected] 6 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Typical Performance Plot - BVA305 EVK - PCB (Application Circuit : 500~4000MHz) Preliminary Datasheet Typical Performance Data @ 25°C, Maximum gain state and VDD = 3.0V unless otherwise noted and Application Circuit refer to Table 10 Figure 12. OIP3 vs Frequency @ Temperature (Max Gain State) Figure 13. P1dB vs Frequency @ Temperature (Max Gain State) Figure 14. Noise Figure vs Frequency @ Temperature (Max Gain State) Figure 15. Attenuation Error vs Frequency @ Major Attenuation Steps Figure 16. Attenuation Error vs Attenuation Setting @Major Frequency (Max Gain State) Figure 17. 0.5dB Step Attenuation vs Attenuation Setting @Major Frequency (Max Gain State) BeRex ●website: www.berex.com ●email: [email protected] 7 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Typical Performance Plot - BVA305 EVK - PCB (Application Circuit : 500~4000MHz) Preliminary Datasheet Typical Performance Data @ 25°C, Maximum gain state and VDD = 3.0V unless otherwise noted and Application Circuit refer to Table 10 Figure 18. Attenuation Error @ 900MHz vs Temperature Figurae 19. Attenuation Error @ 1.9GHz vs Figure 20. Attenuation Error @ 2.14GHz vs Temperature Figure 21. Attenuation Error @ 2.65GHz vs Temperature Temperature Figure 22. Attenuation Error @ 3.9GHz vs Temperature BeRex ●website: www.berex.com ●email: [email protected] 8 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Typical Performance Plot - BVA305 EVK - PCB (Application Circuit : 40~500MHz) Typical Performance Data @ 25°C, Maximum gain state and VDD = 3.0V unless otherwise noted and Application Circuit refer to Table 10 Preliminary Datasheet Figure 23. Gain1 vs Frequency @ Temperature (Max Gain State) Figure 24. Gain vs Frequency @ Major Attenuation Steps Note: 1. Gain data has PCB & connectors insertion loss de-embedded Figure 25. Input Return Loss vs Frequency @ Temperature (Max Gain State) Figure 26. Input Return Loss vs Frequency @ Max Gain & Min Gain1 State Note: 1. Min Gain was measured in the state is set with attenuation 31.5dB Figure 27. output Return Loss vs. Frequency @ Temperature (Max Gain State) Figure 28. output Return Loss vs. Frequency @ Max Gain & Min Gain1 State Note: 1. Min Gain was measured in the state is set with attenuation 31.5dB BeRex ●website: www.berex.com ●email: [email protected] 9 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Typical Performance Plot - BVA305 EVK - PCB (Application Circuit : 40~500MHz) Preliminary Datasheet Typical Performance Data @ 25°C, Maximum gain state and VDD = 3.0V unless otherwise noted and Application Circuit refer to Table 10 Figure 29. OIP3 vs Frequency @ Temperature (Max Gain State) Figure 30. P1dB vs Frequency @ Temperature (Max Gain State) Figure 31. Noise Figure vs Frequency @ Temperature (Max Gain State) Figure 32. Attenuation Error vs Frequency @ Major Attenuation Steps Figure 33. Attenuation Error vs Attenuation Setting @Major Frequency (Max Gain State) Figure 34. 0.5dB Step Attenuation vs Attenuation Setting @Major Frequency (Max Gain State) BeRex ●website: www.berex.com ●email: [email protected] 10 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Typical Performance Plot - BVA305 EVK - PCB (Application Circuit : 40~500MHz) Preliminary Datasheet Typical Performance Data @ 25°C, Maximum gain state and VDD = 3.0V unless otherwise noted and Application Circuit refer to Table 10 Figure 35. Attenuation Error @ 40MHz vs Temperature Figure 36. Attenuation Error @ 70MHz vs Temperature Figure 37. Attenuation Error @ 100MHz vs Temperature Figure 38. Attenuation Error @ 200MHz vs Temperature Figure 39. Attenuation Error @ 300MHz vs Temperature Figure 40. Attenuation Error @ 400MHz vs Temperature BeRex ●website: www.berex.com ●email: [email protected] 11 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Evaluation Board PCB Information Figure 41. Evaluation Board PCB Layer Information COPPER :1oz + 0.5oz (plating), Top Layer EM825B ER: 4.6~4.8 P.P : (0.2+0.06+0.06) TOTAL = 0.32mm COPPER :1oz (GND), Inner Layer Preliminary Datasheet MTC Er:4.6 CORE : 0.73mm FINISH TICKNESS :1.55T COPPER :1oz, Inner Layer EM825B Er:4.6~4.8 P.P : (0.2+0.06+0.06) TOTAL = 0.32mm COPPER :1oz + 0.5oz (plating), Bottom Layer Figure 42. Evaluation Board PCB BeRex ●website: www.berex.com ●email: [email protected] 12 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Preliminary Datasheet Figure 43. Evaluation Board Schematic Table 10. Application Circuit Application Circuit Values Example Freq. C1/C3 L3(1005 Chip Ind) IF Circuit RF Circuit 50~500MHz 500MHz ~ 4GHz 2nF 100pF 820nH 12nH Table 11. Bill of Material - Evaluation Board No. Ref Des Part 1 2 3 C1,C3 C4,C15 C5 2 2 1 4 C6 1 TANTAL 3216 10UF 16V 5 6 7 C22 L3 R2,R3 1 1 2 TANTAL 3216 0.1uF 35V IND 1608 12nH IF circuit refer to table 10 RES 1005 J 10K 8 R1,R4,R6 3 RES 1608 J 0ohm 9 CON1 1 15P-MALE-D-sub con- 10 U1 1 QFN4X4_24L_BVA305 11 J1,J3 2 SMA_END_LAUNCH Part Number REMARK CAP 0402 100pF J 50V IF circuit refer to table 10 CAP 0402 100pF J 50V CAP 0402 1000pF J 50V Notice: Evaluation Board for Marketing Release was set to 500MHz to 4GHz application circuit (Refer to Table 10) BeRex ●website: www.berex.com ●email: [email protected] 13 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Preliminary Datasheet Figure 44. Application Circuit schematic* (Use only Serial mode) * notice. The serial mode PUP state of this Figure 44. is setting in Reference Loss (Refer to Table 5.) and each combinations of C0.5-C16 are shown in the Table 4. Truth Table. BeRex ●website: www.berex.com ●email: [email protected] 14 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Preliminary Datasheet Figure 45. Package Outline Dimension Figure 46. Recommend Land Pattern BeRex ●website: www.berex.com ●email: [email protected] 15 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5 BVA305 DIGITAL VARIABLE GAIN AMPLIFIER 40-4000 MHz Preliminary Datasheet Figure 47. Tape & Reel Packaging information: Figure 48. Package Marking Marking information: BVA305 YYWWXX BVA305 Device Name YY Year WW Work Week XX LOT Number Tape Width Reel Size Device Cavity Pitch Devices Per Reel 12mm 7” 8mm 1K Lead plating finish 100% Tin Matte finish MSL / ESD Rating ESD Rating: Class 1C Value: Passes ≤ 2000V Test: Human Body Model(HBM) Standard: JEDEC Standard JESD22-A114B MSL Rating: Level 1 at +265°C convection reflow Standard: JEDEC Standard J-STD-020 C a u t i o n : ESD Sensitive Appropriate precautions in handling, packaging and testing devices must be observed. Proper ESD procedures should be followed when handling this device. NATO CAGE code: 2 BeRex N 9 6 F ●website: www.berex.com ●email: [email protected] 16 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2018 BeRex Rev. 0.5