Altera EP5368QI 600ma powersoc synchronous buck regulator with integrated inductor Datasheet

Enpirion® Power Datasheet
EP5368QI 600mA PowerSoC
Synchronous Buck Regulator
With Integrated Inductor
Description
Features
The EP5368QI is a synchronous buck converter
with integrated Inductor, PWM controller,
MOSFETS, and Compensation providing the
smallest possible solution size. The EP5368QI
requires only two small MLCC capacitors to
make a complete solution. Integration of the
inductor greatly simplifies design, contains noise,
reduces part count, and reduces solution
footprint. Low output ripple ensures compatibility
with RF systems.
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The EP5368QI operates at a switching frequency
of 4 MHz, enabling this unprecedented level of
integration and small external components. Type
III voltage mode control is used to provide high
noise immunity and wide control loop bandwidth.
The device can source 600mA of current over
the industrial temperature range and up to
700mA over the commercial temperature range.
The small footprint makes this part ideal for
space constrained applications. Output voltage
is programmed via a 3-pin VID selector providing
seven pre-programmed output voltages along
with an option for external resistor divider.
Integrated Inductor
3mm x 3mm x 1.1mm QFN package
Only two low cost MLCC caps required
4 MHz switching frequency
High efficiency, up to 94%
Up to 700mA continuous output current
Wide 2.4V to 5.5V input range
VOUT Range 0.603V to VIN – 0.4V
100% duty cycle capable
Less than 1 µA standby current
Low VOUT ripple for RF compatibility
Short circuit and over current protection
UVLO and thermal protection
Stable over entire operating range
RoHS compliant; MSL 3 260°C reflow
Application
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Noise sensitive RF applications
Area constrained applications
Smart phones and PDAs
Personal Media Players
Advanced Mobile Processors, DSP, IO,
Memory, Video, Multimedia Engines
VSense
ENABLE
VIN
Vin
4.7µF
0603
VOUT
Vout
22µF
0805
EP5368QI
VFB
Voltage
Select
Figure 1: Features INTEGRATED INDUCTOR
TECHNOLOGY
VS0
V S1
VS2
GND
Figure 2: Typical Application Schematic
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Ordering Information
Part Number
EP5368QI
EVB-EP5368QI
Pin Assignments (Top View)
Temp Rating
(°C)
Package
-40 to +85
16-pin QFN T&R
EP5368QI Evaluation Board
Figure 3: Pin Out Diagram (Top View)
Pin Description
PIN
NAME
FUNCTION
1, 15,
16
NC (SW)
NO CONNECT – These pins are internally connected to the common switch node of the
internal MOSFETs. NC(SW) pins are not to be electrically connected to any external signal,
voltage, or ground. These pins must be soldered to the PCB. Failure to follow this guideline
may result in part malfunction or damage.
2
PGND
3,9
NC
NO CONNECT - These pins are not electrically connected internally. They may be
connected to ground externally if necessary to increase trace width in layout. These pins
must be soldered to the PCB.
4
VFB
Feed back pin for external divider option. When using the external divider option
(VS0=VS1=VS2= high) connect this pin to the center of the external divider. Set the divider
such that VFB = 0.6V. The “ground” side of the external divider should be connected to
AGND.
5
VSENSE
Sense pin for preset output voltages. Connect to the output capacitor.
6
AGND
Analog ground. This is the quiet ground for the internal control circuitry.
7, 8
VOUT
10, 11,
12
VS2, VS1,
VS0
Output voltage select. VS2=pin10 VS1=pin11, VS0=pin12. Selects one of seven preset
output voltages or choose external divider by connecting pins to logic high or low. Logic low
is defined as VLOW ≤ 0.4V. Logic high is defined as V HIGH ≥ 1.4V. Any level between these
two values is indeterminate. (Refer to section on output voltage select for more detail).
13
ENABLE
Output enable: Enable = logic high, disable = logic low. Logic low is defined as V LOW ≤ 0.4V.
Logic high is defined as VHIGH ≥ 1.4V. Any level between these two values is indeterminate.
14
VIN
Power Ground
Regulated Output Voltage
Input voltage pin. Supplies power to the IC.
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Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the
recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods may affect device reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
VIN
-0.3
7.0
V
Voltages on: ENABLE, VSENSE, VS0 – VS2
-0.3
VIN +0.3
V
Voltage on: VFB
-0.3
2.7
V
-65
150
°C
260
°C
2000
V
Input Supply Voltage
Storage Temperature Range
TSTG
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020C
ESD Rating (based on Human Body Mode)
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Supply Voltage
VIN
2.4
5.5
V
Operating Ambient Temperature
TA
- 40
85
°C
Operating Junction Temperature
TJ
- 40
125
°C
SYMBOL
TYP
UNITS
θJA
85
°C/W
TJ-TP
150
°C
15
°C
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient (0 LFM)
Thermal Overload Trip Point
Thermal Overload Trip Point Hysteresis
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Electrical Characteristics
NOTE: TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.6V
CIN = 4.7µF 0603 MLCC, COUT = 22µF 0805 MLCC
PARAMETER
SYMBOL
Operating Input Voltage
Range
VIN
Under Voltage Lock-out –
VIN Rising
VUVLO_R
Under Voltage Lock-out –
VIN Falling
VUVLO_F
Drop Out Resistance
RDO
Input to Output Resistance in 100%
duty cycle operation.
Output Voltage Range
VOUT
External Feedback Mode
VID Mode
Dynamic Voltage Slew
Rate (VID Change)
VSLEW
VOUT Initial Accuracy (VID
Preset Mode)
∆VOUT_INITIAL
TA = 25°C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
∆VOUT_ALL
-40°C ≤ TA ≤ +85°C
2.4V ≤ VIN ≤ 5.5V;
0.8V ≤ VOUT ≤ 3.3V
0A ≤ ILOAD ≤ 700A
∆VFB_INITIAL
TA = 25°C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
0.591
Feedback Pin Voltage
Accuracy over line, load,
and temperature variations
∆VFB_ALL
-40°C ≤ TA ≤ +85°C
2.4V ≤ VIN ≤ 5.5V;
0.8V ≤ VOUT ≤ 3.3V
0A ≤ ILOAD ≤ 700A
0.585
Feedback Pin Input
Current
IFB
VOUT Accuracy (VID
Preset Mode)
over line, load and
temperature variation
Feedback Pin Voltage
Initial Accuracy
TEST CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
2.2
2.3
V
2.1
2.2
V
400
500
mΩ
2.4
*
0.603
0.8
V IN-V DO
3.3
V
2.025
V/mS
-2
+2
%
-3
+3
%
.603
0.615
V
.603
0.621
V
100
nA
0.975
1.5
Continuous Output Current IOUT
VIN = 5V, 0.603V <VOUT < 3.3V,
TA = -40°C to +85°C
600
mA
Continuous Output Current IOUT
VIN = 5V, 0.603V <VOUT < 3.3V,
TA = -10°C to +85°C
(Application Circuit Figure 6)
700
mA
Shut-Down Current
ISD
Enable = Low
PFET OCP Threshold
IILM
2.4V ≤VIN ≤5.5V, 0.6V ≤ VIN ≤ 3.3V
1.4
VS0-VS2, Enable Voltage
Threshold
VTH
Pin = Low
0.0
0.4
Pin = High
1.4
VIN
0.75
µA
2
A
VS0-VS2 Pin Input Current IVSX
1
nA
Operating Frequency
FOSC
4
MHz
Soft-Start Slew Rate
VSS
VID programming mode
0.975
1.5
2.025
V/mS
VOUT Rise Time
TSS
VFB programming mode
0.784
1.2
1.628
mS
*: VDO = IOUT x RDO
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100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
Typical Performance Characteristics
80
75
70
80
75
70
65
65
60
60
55
55
50
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70
50
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70
Load Current (A)
Load Current (A)
Efficiency Versus Load; VIN = 3.7V,
VOUT (from top to bottom) 2.5V, 1.8V, 1.5V, 1.2V.
Efficiency Versus Load; VIN = 3.3V,
VOUT (from top to bottom) 2.5V, 1.8V, 1.5V, 1.2V.
100
95
90
Efficiency (%)
85
80
75
70
65
60
55
50
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70
Load Current (A)
Efficiency Versus Load; VIN = 5V,
VOUT (from top to bottom) 3.3V, 2.5V, 1.8V, 1.5V, 1.2V.
Transient, VIN = 3.6V, VOUT = 1.2V, Load = 0-500mA
Startup, VIN = 3.6V, VOUT = 1.5V, Load = 500mA
Shutdown, VIN = 3.6V, VOUT = 1.5V, Load = 500mA
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Voltage Ripple, VIN = 3.3V, VOUT = 1.8V, Load = 0mA
COUT = 1x 22µF, 0805, 2.0mV/Div.
Voltage Ripple, VIN = 3.3V, VOUT = 1.8V, Load = 600mA
COUT = 1x 22µF, 0805, 2.0mV/Div.
Voltage Ripple, VIN = 3.3V, VOUT = 1.8V, Load = 0mA
COUT = 2x 10µF, 0805, 2.0mV/Div.
Voltage Ripple, VIN = 3.3V, VOUT = 1.8V, Load = 600mA
COUT = 2x 10µF, 0805, 2.0mV/Div.
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Functional Block Diagram
VIN
UVLO
Thermal Limit
Current Limit
ENABLE
NC(SW)
Soft Start
P-Drive
(-)
Logic
VOUT
PWM
Comp
(+)
N-Drive
GND
VSENSE
Sawtooth
Generator
Compensation
Network
Switch
(-)
Error
Amp
VFB
(+)
DAC
Voltage
Select
VREF
Package Boundry
VS0 VS1 VS2
Figure 4: Functional Block Diagram
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Detailed Description
Functional Overview
The EP5368QI is a complete DCDC converter
solution requiring only two low cost MLCC
capacitors.
MOSFET switches, PWM
controller, Gate-drive, compensation, and
inductor are integrated into the tiny 3mm x
3mm x 1.1mm package to provide the smallest
footprint possible while maintaining high
efficiency, low ripple, and high performance.
The converter uses voltage mode control to
provide the simplest implementation and high
noise immunity. The device operates at a
4MHz switching frequency. The high switching
frequency allows for a wide control loop
bandwidth
providing
excellent
transient
performance. The high switching frequency
further enables the use of very small
components
making
possible
this
unprecedented level of integration.
Altera Enpirion’s proprietary power MOSFET
technology provides very low switching loss at
frequencies of 4 MHz and higher, allowing for
the use of very small internal components, and
high performance. Integration of the magnetics
virtually eliminates the design/layout issues
normally associated with switch-mode DCDC
converters. All of this enables much easier
and
faster
incorporation
into
various
applications
to
meet
demanding
EMI
requirements.
Output voltage is chosen from seven preset
values via a three pin VID voltage select
scheme. An external divider option enables
the selection of any voltage in VIN to 0.603V
range.
This
reduces
the number of
components that must be qualified and
reduces inventory burden. The VID pins can
be toggled on the fly to implement glitch free
dynamic voltage scaling.
Protection features include under-voltage lockout (UVLO), over-current protection (OCP),
short circuit protection, and thermal overload
protection.
Integrated Inductor
family featuring integrated inductors.
The
EP5368QI utilizes a proprietary low loss
integrated inductor. The use of an internal
inductor localizes the noises associated with
the output loop currents. The inherent shielding
and compact construction of the integrated
inductor reduces the radiated noise that
couples into the traces of the circuit board.
Further, the package layout is optimized to
reduce the electrical path length for the AC
ripple currents that are a major source of
radiated emissions from DCDC converters.
The integrated inductor significantly reduces
parasitic effects that can harm loop stability,
and makes layout very simple.
Stable Over Wide Range of Operating
Conditions
The EP5368QI utilizes an internal type III
compensation network and is designed to
provide a high degree of stability over a wide
range of operating conditions. The device
operates over the entire input and output
voltage range with no external modifications
required. The very high switching frequency
allows for a very wide control loop bandwidth.
Soft Start
Internal soft start circuits limit in-rush current
when the device starts up from a power down
condition or when the “ENABLE” pin is
asserted “high”. Digital control circuitry limits
the VOUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated
inductor.
The EP5368QI has two soft start operating
modes. When VOUT is programmed using a
preset voltage in VID mode, the device has a
constant slew rate. When the EP5368QI is
configured in external resistor divider mode,
the device has a constant VOUT ramp time.
Output voltage slew rate and ramp time is
given in the Electrical Characteristics Table.
Excess bulk capacitance on the output of the
device can cause an over-current condition at
startup.
Altera has introduced the world’s first product
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When operating in VID mode, the maximum
total capacitance on the output, including the
output filter capacitor and bulk and decoupling
capacitance, at the load, is given as:
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 700uF
When the EP5368QI output voltage is
programmed using and external resistor divider
the maximum total capacitance on the output is
given as:
-3
COUT_TOTAL_MAX = 1.251x10 /VOUT Farads
The above number and formula assume a no
load condition at startup.
Over Current/Short Circuit Protection
The current limit function is achieved by
sensing the current flowing through a sense PMOSFET which is compared to a reference
current. When this level is exceeded the PFET is turned off and the N-FET is turned on,
pulling VOUT low. This condition is maintained
for a period of 1mS and then a normal soft start
is initiated. If the over current condition still
persists, this cycle will repeat in a “hiccup”
mode.
Under Voltage Lockout
During initial power up an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
the voltage drops below the UVLO threshold,
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
Enable
The ENABLE pin provides a means to shut
down the converter or enable normal
operation. A logic low will disable the converter
and cause it to shut down. A logic high will
enable the converter into normal operation. In
shutdown mode, the device quiescent current
will be less than 1 uA.
NOTE: This pin must not be left floating.
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 15C, the
device will go through the normal startup
process.
Application Information
Output Voltage Select
To provide the highest degree of flexibility in
choosing output voltage, the EP5368QI uses a
3 pin VID, or Voltage ID, output voltage select
arrangement.
This allows the designer to
choose one of seven preset voltages, or to use
an external voltage divider.
Internally, the
output of the VID multiplexer sets the value for
the voltage reference DAC, which in turn is
connected to the non-inverting input of the
error amplifier. This allows the use of a single
feedback divider with constant loop gain and
optimum compensation, independent of the
output
voltage
selected.
Table 1 shows the various VS0-VS2 pin logic
states and the associated output voltage
levels. A logic “1” indicates a connection to
VIN or to a “high” logic voltage level. A logic
“0” indicates a connection to ground or to a
“low” logic voltage level. These pins can be
either hardwired to VIN or GND or alternatively
can be driven by standard logic levels. Logic
low is defined as VLOW ≤ 0.4V. Logic high is
defined as VHIGH ≥ 1.4V. Any level between
these two values is indeterminate. These pins
must not be left floating.
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Dynamically Adjustable Output
Table 1 VID Voltage Select Settings
VS2
0
0
0
0
1
1
1
VS1
0
0
1
1
0
0
1
VS0
0
1
0
1
0
1
0
1
1
1
VOUT
3.3V
2.5V
1.8V
1.5V
1.25V
1.2V
0.8V
User
Selectable
As described above, the external voltage
divider option is chosen by connecting the
VS0, VS1, and VS2 pins to VIN or logic “high”.
The EP5368QI uses a separate feedback pin,
VFB, when using the external divider. VSENSE
must be connected to VOUT as indicated in
Figure 5.
VSense
ENABLE
Vin
4.7uF
0603
VOUT
Vout
Ra
EP5368QI
VS2
22µF
0805
VFB
VS0
VS1
GND
The output voltage is selected by the following
formula:
VOUT = 0.603V (1 +
Ra
Rb
The input capacitance requirement is 4.7uF
0603 MLCC. The input capacitor must be a
X5R/X7R MLCC. Y5V or equivalent dielectric
formulations lose capacitance with frequency,
bias, and with temperature, and are not
suitable for switch-mode DC-DC converter
input filter applications.
The output capacitance requirement is
approximately 20uF. Altera recommends a
single 22uF 0805 MLCC. Ripple performance
can be improved by using 2 x 10uF 0805 MLC
capacitors.
As described in the Soft Start section, there is
a limitation on the maximum bulk capacitance
that can be placed on the output of this device.
Please refer to that section for more details.
Rb
Figure 5: External Divider Application Circuit
)
Ra must be chosen as 200kΩ to maintain loop
gain. Then Rb is given as:
Rb =
Dynamic transitioning between internal VID
settings and the external divider is not allowed.
Input and Output Capacitors
External Voltage Divider
VIN
The EP5368QI is designed to allow for
dynamic switching between the predefined VID
voltage levels The inter-voltage slew rate is
optimized to prevent excess undershoot or
overshoot as the output voltage levels
transition. The slew rate is identical to the softstart slew rate and is provided in the electrical
characteristics table.
1.206 x10 5
Ω
VOUT − 0.603
The output capacitor must be a X5R/X7R or
equivalent MLCC. Y5V or equivalent dielectric
formulations lose capacitance with frequency,
bias, and temperature and are not suitable for
switch-mode DC-DC converter output filter
applications.
Please consult Power Applications support for
other capacitor case size combinations.
Operation at 700mA Output Current
VOUT can programmed over the range of 0.603V
to VIN-0.4V.
Operation at 700mA is supported by using the
application circuit shown in Figure 6. The
modification in the compensation is to ensure
stability over the entire set of input and output
voltage conditions.
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VIN
Vin
4.7uF
0603
VOUT
Vout
Ra
EP5368QI
22µF
0805
Ca
2) Ca = 15pF 0402 MLCC capacitor.
3) Then Rb is given as:
Rb =
VFB
VS0
VS1
VS2
1) Ra = 249kΩ
VSense
ENABLE
Rb
GND
1.501x10 5
Ω
VOUT − 0.603
VOUT can be programmed over the range of
0.603V to VIN-0.4V.
4) Do not connect the sense line.
Figure 6: Applications Circuit for Operation at
700mA
For 700mA operation,
component values:
use
the
NOTE: Stability cannot be assured if these
guidelines are not followed.
following
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Layout Recommendation
Figure 7 shows critical components and layer 1
traces of a recommended minimum footprint
EP5368QI layout. ENABLE configurations and
other small signal pins need to be connected
and routed according to specific customer
application. Please see the Gerber files on the
Altera website www.altera.com/enpirion for
exact dimensions and other layers. Please
refer to Figure 7 while reading the layout
recommendations in this section.
Recommendation 1: Input and output filter
capacitors should be placed on the same side
of the PCB, and as close to the EP5368QI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EP5368QI
should be as close to each other as possible
so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: Input and output grounds
are separated until they connect at the PGND
pins. The separation shown on Figure 7
between the input and output GND circuits
helps minimize noise coupling between the
converter input and output switching loops.
Recommendation 3: The system ground
plane should be the first layer immediately
below the surface layer. This ground plane
should be continuous and un-interrupted below
the converter and the input/output capacitors.
Please see the Gerber files on the Altera
website www.altera.com/enpirion.
Figure 7: Top PCB Layer Critical Components
and Copper for Minimum Footprint
Recommendation 4: Multiple small vias
should be used to connect the ground traces
under the device to the system ground plane
on another layer for heat dissipation. The drill
diameter of the vias should be 0.33mm, and
the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole
size around 0.20-0.26mm. Do not use thermal
reliefs or spokes to connect the vias to the
ground plane. It is preferred to put these vias
under the capacitors along the edge of the
GND copper closest to the +V copper. Please
see Figure 7. These vias connect the
input/output filter capacitors to the GND plane
and help reduce parasitic inductances in the
input and output current loops. If the vias
cannot be placed under CIN and COUT , then put
them just outside the capacitors along the
GND. Do not use thermal reliefs or spokes to
connect these vias to the ground plane.
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Recommended PCB Footprint
Figure 8: EP5368QI Package PCB Footprint
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Package Dimensions
Figure 9: EP5368QI Package Dimensions
NOTE: for details on product marking, please refer to the product marking guide which can be found
at www.altera.com/support/reliability/packing/rel-packing-and-marking.html.
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
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