ONSEMI NST3904DXV6T1

NST3904DXV6T1,
NST3904DXV6T5
Dual General Purpose
Transistor
The NST3904DXV6T1 device is a spin- off of our popular
SOT-23/SOT-323 three-leaded device. It is designed for general
purpose amplifier applications and is housed in the SOT- 563
six-leaded surface mount package. By putting two discrete devices in
one package, this device is ideal for low-power surface mount
applications where board space is at a premium.
• hFE, 100-300
• Low VCE(sat), ≤ 0.4 V
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• Lead-Free Solder Plating
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(3)
(2)
Q1
Q2
(4)
(5)
Symbol
Value
Unit
Collector - Emitter Voltage
VCEO
40
Vdc
Collector - Base Voltage
VCBO
60
Vdc
Emitter - Base Voltage
VEBO
6.0
Vdc
IC
200
mAdc
ESD
HBM>16000,
MM>2000
V
Collector Current - Continuous
Electrostatic Discharge
6
Total Device Dissipation
TA = 25°C
Symbol
Max
Unit
PD
357
(Note 1)
2.9
(Note 1)
mW
RJA
Characteristic
(Both Junctions Heated)
Total Device Dissipation
TA = 25°C
2
3
SOT-563
CASE 463A
PLASTIC
MARKING DIAGRAM
MA D
Derate above 25°C
Thermal Resistance
Junction-to-Ambient
54
1
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
(6)
NST3946DXV6T1
MAXIMUM RATINGS
Rating
(1)
MA = Specific Device Code
D = Date Code
mW/°C
°C/W
350
(Note 1)
ORDERING INFORMATION
Device
Symbol
Max
Unit
PD
500
(Note 1)
4.0
(Note 1)
mW
Derate above 25°C
mW/°C
Thermal Resistance
Junction-to-Ambient
RJA
250
(Note 1)
°C/W
Junction and Storage
Temperature Range
TJ, Tstg
- 55 to +150
°C
Package
Shipping
NST3904DXV6T1
SOT-563
4 mm pitch
4000/Tape & Reel
NST3904DXV6T5
SOT-563
2 mm pitch
8000/Tape & Reel
1. FR-4 @ Minimum Pad
 Semiconductor Components Industries, LLC, 2003
March, 2003 - Rev. 0
1
Publication Order Number:
NST3904DXV6T1/D
NST3904DXV6T1, NST3904DXV6T5
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Max
40
-
60
-
6.0
-
-
50
-
50
40
70
100
60
30
300
-
-
0.2
0.3
0.65
-
0.85
0.95
300
-
-
4.0
-
8.0
Unit
OFF CHARACTERISTICS
Collector - Emitter Breakdown Voltage (Note 2)
(IC = 1.0 mAdc, IB = 0)
V(BR)CEO
Collector - Base Breakdown Voltage
(IC = 10 Adc, IE = 0)
V(BR)CBO
Emitter - Base Breakdown Voltage
(IE = 10 Adc, IC = 0)
V(BR)EBO
Base Cutoff Current
(VCE = 30 Vdc, VEB = 3.0 Vdc)
IBL
Collector Cutoff Current
(VCE = 30 Vdc, VEB = 3.0 Vdc)
ICEX
Vdc
Vdc
Vdc
nAdc
nAdc
ON CHARACTERISTICS (Note 2)
DC Current Gain
(IC = 0.1 mAdc, VCE = 1.0 Vdc)
(IC = 1.0 mAdc, VCE = 1.0 Vdc)
(IC = 10 mAdc, VCE = 1.0 Vdc)
(IC = 50 mAdc, VCE = 1.0 Vdc)
(IC = 100 mAdc, VCE = 1.0 Vdc)
hFE
Collector - Emitter Saturation Voltage
(IC = 10 mAdc, IB = 1.0 mAdc)
(IC = 50 mAdc, IB = 5.0 mAdc)
VCE(sat)
Base - Emitter Saturation Voltage
(IC = 10 mAdc, IB = 1.0 mAdc)
(IC = 50 mAdc, IB = 5.0 mAdc)
VBE(sat)
-
Vdc
Vdc
SMALL- SIGNAL CHARACTERISTICS
Current - Gain - Bandwidth Product
(IC = 10 mAdc, VCE = 20 Vdc, f = 100 MHz)
fT
Output Capacitance
(VCB = 5.0 Vdc, IE = 0, f = 1.0 MHz)
Cobo
Input Capacitance
(VEB = 0.5 Vdc, IC = 0, f = 1.0 MHz)
Cibo
2. Pulse Test: Pulse Width ≤ 300 µs; Duty Cycle ≤ 2.0%.
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2
MHz
pF
pF
NST3904DXV6T1, NST3904DXV6T5
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)
Characteristic
Symbol
Input Impedance
(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
hie
Voltage Feedback Ratio
(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
hre
Small - Signal Current Gain
(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
hfe
Output Admittance
(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
hoe
Noise Figure
(VCE = 5.0 Vdc, IC = 100 Adc, RS = 1.0 k Ω, f = 1.0 kHz)
NF
Min
Max
1.0
2.0
10
12
0.5
0.1
8.0
10
100
100
400
400
1.0
3.0
40
60
-
5.0
4.0
Unit
kΩ
X 10- 4
-
mhos
dB
SWITCHING CHARACTERISTICS
Delay Time
(VCC = 3.0 Vdc, VBE = - 0.5 Vdc)
td
-
35
Rise Time
(IC = 10 mAdc, IB1 = 1.0 mAdc)
tr
-
35
Storage Time
(VCC = 3.0 Vdc, IC = 10 mAdc)
ts
-
200
Fall Time
(IB1 = IB2 = 1.0 mAdc)
tf
-
50
DUTY CYCLE = 2%
300 ns
+3 V
+10.9 V
10 < t1 < 500 s
275
t1
DUTY CYCLE = 2%
10 k
+3 V
275
10 k
Cs < 4 pF*
< 1 ns
1N916
−9.1 V′
< 1 ns
* Total shunt capacitance of test jig and connectors
Figure 1. Delay and Rise Time
Equivalent Test Circuit
Figure 2. Storage and Fall Time
Equivalent Test Circuit
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3
ns
+10.9 V
0
−0.5 V
ns
Cs < 4 pF*
NST3904DXV6T1, NST3904DXV6T5
TYPICAL TRANSIENT CHARACTERISTICS
TJ = 25°C
TJ = 125°C
10
CAPACITANCE (pF)
7.0
5.0
Cibo
3.0
Cobo
2.0
1.0
0.1
0.2 0.3
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20 30 40
REVERSE BIAS VOLTAGE (VOLTS)
Figure 3. Capacitance
500
500
IC/IB = 10
tr @ VCC = 3.0 V
50
30
20
40 V
15 V
10
7
5
1.0
2.0 3.0
5.0 7.0 10
20
30
50 70 100
300
200
IC/IB = 20
100
70
50
30
20
10
2.0 V
td @ VOB = 0 V
7
5
200
5.0 7.0 10
20
30
50 70 100
Figure 4. Turn - On Time
Figure 5. Rise Time
IC/IB = 10
IC/IB = 10
IC/IB = 20
100
70
50
10
7
5
7
5
20
30
50 70 100
200
IC/IB = 10
30
20
10
5.0 7.0 10
VCC = 40 V
IB1 = IB2
300
200
IC/IB = 20
30
20
200
500
t′s = ts − 1/8 tf
IB1 = IB2
50
2.0 3.0
2.0 3.0
IC, COLLECTOR CURRENT (mA)
100
70
1.0
1.0
IC, COLLECTOR CURRENT (mA)
500
t s′ , STORAGE TIME (ns)
t r, RISE TIME (ns)
100
70
VCC = 40 V
IC/IB = 10
300
200
t f , FALL TIME (ns)
TIME (ns)
300
200
1.0
2.0 3.0
5.0 7.0 10
20
30
50 70 100
IC, COLLECTOR CURRENT (mA)
IC, COLLECTOR CURRENT (mA)
Figure 6. Storage Time
Figure 7. Fall Time
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4
200
NST3904DXV6T1, NST3904DXV6T5
TYPICAL AUDIO SMALL- SIGNAL CHARACTERISTICS
NOISE FIGURE VARIATIONS
(VCE = 5.0 Vdc, TA = 25°C, Bandwidth = 1.0 Hz)
12
f = 1.0 kHz
SOURCE RESISTANCE = 200 IC = 0.5 mA
8
6
SOURCE RESISTANCE = 1.0 k
IC = 50 A
4
SOURCE RESISTANCE = 500 IC = 100 A
2
0
0.1
0.2
0.4
1.0
2.0
IC = 1.0 mA
12
NF, NOISE FIGURE (dB)
10
NF, NOISE FIGURE (dB)
14
SOURCE RESISTANCE = 200 IC = 1.0 mA
IC = 0.5 mA
10
IC = 50 A
8
IC = 100 A
6
4
2
4.0
10
20
40
0
100
0.1
0.2
0.4
1.0
2.0
4.0
10
20
f, FREQUENCY (kHz)
RS, SOURCE RESISTANCE (k OHMS)
Figure 8. Noise Figure
Figure 9. Noise Figure
40
100
5.0
10
5.0
10
h PARAMETERS
(VCE = 10 Vdc, f = 1.0 kHz, TA = 25°C)
100
hoe, OUTPUT ADMITTANCE ( mhos)
h fe , CURRENT GAIN
300
200
100
70
50
30
0.1
0.2
0.3
0.5
1.0
2.0 3.0
IC, COLLECTOR CURRENT (mA)
5.0
50
20
10
5
2
1
10
0.1
0.2
Figure 10. Current Gain
hre , VOLTAGE FEEDBACK RATIO (x 10 −4)
Figure 11. Output Admittance
h ie , INPUT IMPEDANCE (k OHMS)
20
10
5.0
2.0
1.0
0.5
0.2
0.1
0.2
0.3
0.5
1.0
2.0 3.0
IC, COLLECTOR CURRENT (mA)
0.3
0.5
1.0
2.0 3.0
IC, COLLECTOR CURRENT (mA)
5.0
10
10
7.0
5.0
3.0
2.0
1.0
0.7
0.5
0.1
Figure 12. Input Impedance
0.2
0.3
0.5
1.0
2.0 3.0
IC, COLLECTOR CURRENT (mA)
Figure 13. Voltage Feedback Ratio
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5
NST3904DXV6T1, NST3904DXV6T5
h FE, DC CURRENT GAIN (NORMALIZED)
TYPICAL STATIC CHARACTERISTICS
2.0
TJ = +125°C
VCE = 1.0 V
+25°C
1.0
0.7
−55 °C
0.5
0.3
0.2
0.1
0.1
0.2
0.3
0.5
0.7
1.0
2.0
3.0
5.0
7.0
10
20
30
70
50
100
200
IC, COLLECTOR CURRENT (mA)
VCE, COLLECTOR EMITTER VOLTAGE (VOLTS)
Figure 14. DC Current Gain
1.0
TJ = 25°C
0.8
IC = 1.0 mA
10 mA
30 mA
100 mA
0.6
0.4
0.2
0
0.01
0.02
0.03
0.05
0.07
0.1
0.2
0.3
0.5
0.7
1.0
2.0
3.0
5.0
7.0
10
IB, BASE CURRENT (mA)
Figure 15. Collector Saturation Region
1.0
1.2
TJ = 25°C
VBE(sat) @ IC/IB =10
0.8
VBE @ VCE =1.0 V
0.6
0.4
VCE(sat) @ IC/IB =10
VC FOR VCE(sat)
0
−55 °C TO +25°C
−0.5
−55 °C TO +25°C
−1.0
+25°C TO +125°C
VB FOR VBE(sat)
−1.5
0.2
0
+25°C TO +125°C
0.5
COEFFICIENT (mV/ °C)
V, VOLTAGE (VOLTS)
1.0
1.0
2.0
5.0
10
20
50
100
−2.0
200
0
20
40
60
80
100
120
140
160
IC, COLLECTOR CURRENT (mA)
IC, COLLECTOR CURRENT (mA)
Figure 16. “ON” Voltages
Figure 17. Temperature Coefficients
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6
180 200
NST3904DXV6T1, NST3904DXV6T5
INFORMATION FOR USING THE SOT-563 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.3
0.45
1.0
1.35
0.5
0.5
Dimensions in mm
SOT-563
SOT-563 POWER DISSIPATION
SOLDERING PRECAUTIONS
The power dissipation of the SOT-563 is a function of
the pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature
of the die, RθJA, the thermal resistance from the device
junction to ambient, and the operating temperature, TA.
Using the values provided on the data sheet for the
SOT-563 package, PD can be calculated as follows:
PD =
The melting temperature of solder is higher than the
rated temperature of the device. When the entire device is
heated to a high temperature, failure to complete soldering
within a short time could result in device failure. Therefore, the following items should always be observed in
order to minimize the thermal stress to which the devices
are subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
TJ(max) - TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 150 milliwatts.
PD =
150°C - 25°C
833°C/W
= 150 milliwatts
The 833°C/W for the SOT-563 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 150 milliwatts. There are other alternatives to achieving higher
power dissipation from the SOT-563 package. Another
alternative would be to use a ceramic substrate or an
aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
* Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage
to the device
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7
NST3904DXV6T1, NST3904DXV6T5
PACKAGE DIMENSIONS
SOT-563, 6 LEAD
CASE 463A-01
ISSUE O
A
-X-
5
6
1
2
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
C
K
4
B
-Y-
3
D
G
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
J
5 PL
6
0.08 (0.003)
EMITTER 1
BASE 1
COLLECTOR 2
EMITTER 2
BASE 2
COLLECTOR 1
DIM
A
B
C
D
G
J
K
S
S
M
X Y
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
EMITTER 1
EMITTER2
BASE 2
COLLECTOR 2
BASE 1
COLLECTOR 1
CATHODE 1
CATHODE 1
ANODE/ANODE 2
CATHODE 2
CATHODE 2
ANODE/ANODE 1
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
MILLIMETERS
MIN
MAX
1.50
1.70
1.10
1.30
0.50
0.60
0.17
0.27
0.50 BSC
0.08
0.18
0.10
0.30
1.50
1.70
INCHES
MIN
MAX
0.059
0.067
0.043
0.051
0.020
0.024
0.007
0.011
0.020 BSC
0.003
0.007
0.004
0.012
0.059
0.067
COLLECTOR
COLLECTOR
BASE
EMITTER
COLLECTOR
COLLECTOR
Thermal Clad is a registered trademark of the Bergquist Company.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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For additional information, please contact your local
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8
NST3904DXV6T1/D